32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F52220/HT32F52230
PxCFGn
Input
DMUX
Output
MUX
IP
AFIO
OEN
IP
Control
AFIO
PxDOUTn
PxRSTn
PxSETn
GPIO
Figure 19. AFIO/GPIO Control Signal
PxDINn/PxDOUTn (x=A ~ B): Data Input/Data Output
PxDIRn (x=A ~ B): Direction
PxDVn (x=A ~ B): Output Drive
PxPDn/PxPUn (x=A ~ B): Pull Down/Up
Table 20. AFIO, GPIO and IO Pad Control Signal True Table
Type
GPIO Input
(Note)
GPIO Output
(Note)
AFIO Input
AFIO Output
ADC Input
OSC Output
Note: The signals, IEN and OEN, for I/O pads are derived from the GPIO register bits PxINENn and
PxDIRn respectively when the associated pin is configured in the GPIO input/output mode.
Rev. 1.10
IEN
IOPAD
ADC
ADEN
PxDINn
PxINENn
PxDIRn
AFIO
ADEN
OEN
IEN
AFIO
AFIO
AFIO
1
1
1
1
1
1
1
1
0
1
0
1
0
1
1
0
1
1
106 of 366
PUN
PDN
OEN
DS
PxDVn
PxODn
PxPDn
PxPUn
PxRSTn/PxSETn (x=A ~ B): Reset/Set
PxINENn (x=A ~ B): Input Enable
PxODn (x=A ~ B): Open Drain
PxCFGn (x=A ~ B): AFIO Configuration
GPIO
PxDIRn
PxINENn
ADEN OEN IEN
0
1
1
1
0 (1 if need)
1
0
X
1
X
0 (1 if need)
1
0
0 (1 if need)
0
0
0 (1 if need)
0
November 09, 2018
PAD
1
0
0
1 (0)
1
0
0
1 (0)
1
1 (0)
1
1 (0)
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