Holtek HT32F52342 User Manual

32-bit microcontroller with arm cortex-m0+ core

page of 656

/ 656
Contents
Table of Contents
Bookmarks

Table of Contents

Quick Links

Download this manual

Holtek 32-Bit Microcontroller with Arm

Cortex

-M0+ Core

HT32F52342/HT32F52352

User Manual

Revision: V1.30

Date: September 28, 2018

Table of Contents

Need help?

Do you have a question about the HT32F52342 and is the answer not in the manual?

Questions and answers

Summary of Contents for Holtek HT32F52342

Page 1 Holtek 32-Bit Microcontroller with Arm ® Cortex ® -M0+ Core HT32F52342/HT32F52352 User Manual Revision: V1.30 Date: September 28, 2018...
Page 2: Table Of Contents
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Table of Contents 1 Introduction ......................26 Overview ..........................26 Features ..........................27 Device Information ....................... 32 Block Diagram ........................33 2 Document Conventions ..................34 3 System Architecture ..................... 35 ®...
Page 3 ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Flash Vector Mapping Control Register – VMCR ................62 Flash Manufacturer and Device ID Register – MDID ..............63 Flash Page Number Status Register – PNSR ................64 Flash Page Size Status Register – PSSR ..................65 Flash Cache &...
Page 4 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 PLL Control Register – PLLCR ....................... 99 AHB Configuration Register – AHBCFGR ..................100 AHB Clock Control Register – AHBCCR ..................101 APB Configuration Register – APBCFGR ..................103 APB Clock Control Register 0 – APBCCR0 .................. 104 APB Clock Control Register 1 –...
Page 5 ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port A Output Data Register – PADOUTR ..................139 Port A Output Set/Reset Control Register – PASRR ..............140 Port A Output Reset Register – PARR ..................141 Port B Data Direction Control Register – PBDIRCR ..............142 Port B Input Function Enable Control Register –...
Page 6 ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Descriptions ......................178 EXTI Source Selection Register 0 – ESSR0 ................178 EXTI Source Selection Register 1 – ESSR1 ................179 GPIO x Configuration Low Register – GPxCFGLR, x = A, B, C, D ..........180 GPIO x Configuration High Register –...
Page 7 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Map ........................205 Register Descriptions ......................206 ADC Conversion Control Register – ADCCR ................206 ADC Conversion List Register 0 – ADCLST0 ................208 ADC Conversion List Register 1 – ADCLST1 ................209 ADC Input Sampling Time Register –...
Page 8 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Quadrature Decoder ........................246 Output Stage ..........................248 Update Management ........................252 Single Pulse Mode ........................253 Asymmetric PWM Mode ....................... 255 Timer Interconnection ........................256 Trigger ADC Start.......................... 259 PDMA Request ..........................259 Register Map ........................
Page 9 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Map ........................307 Register Descriptions ......................307 BFTM Control Register – BFTMCR ....................307 BFTM Status Register – BFTMSR ....................308 BFTM Counter Register – BFTMCNTR ..................309 BFTM Compare Value Register – BFTMCMPR ................310 16 Motor Control Timer (MCTM) ................
Page 10 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer PDMA/Interrupt Control Register – DICTR ................. 379 Timer Event Generator Register – EVGR ..................381 Timer Interrupt Status Register – INTSR ..................383 Timer Counter Register – CNTR....................386 Timer Prescaler Register – PSCR ....................387 Timer Counter Reload Register –...
Page 11 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 18 Real Time Clock (RTC) ..................427 Introduction ........................427 Features ..........................427 Functional Descriptions ..................... 428 RTC Related Register Reset ......................428 Reading RTC Register ........................428 Low Speed Clock Configuration ....................428 RTC Counter Operation ........................
Page 12 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bus Error ............................453 Address Mask Enable ........................453 Address Snoop ..........................453 Operation Mode ..........................453 Conditions of Holding SCL Line ....................459 C Timeout Function ........................460 PDMA Interface ..........................460 Register Map ........................
Page 13 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Function Descriptions ......................500 Serial Data Format ........................500 Baud Rate Generation ........................501 Hardware Flow Control ......................... 502 IrDA ............................... 504 RS485 Mode ..........................506 Synchronous Master Mode ......................509 Interrupts and Status ........................511 PDMA Interface ..........................511...
Page 14 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Elementary Time Unit Counter ...................... 539 Guard Time Counter ........................541 Waiting Time Counter ........................542 Card Clock and Data Selection ..................... 543 Card Detection ..........................543 SCI Data Transfer Mode ....................... 544 Interrupt Generator ........................
Page 15 Cortex ® -M0+ MCU HT32F52342/HT32F52352 USB Endpoint 1 ~ 3 Control and Status Register – USBEPnCSR, n = 1 ~ 3 ....... 581 USB Endpoint 1 ~ 3 Interrupt Enable Register – USBEPnIER, n = 1 ~ 3 ........582 USB Endpoint 1 ~ 3 Interrupt Status Register –...
Page 16 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bus Turn-around and Idle Cycles ....................616 AHB Transaction Width Conversion ..................... 617 EBI Bank Access .......................... 619 PDMA Request ..........................620 Register Map ........................620 Register Descriptions ......................620 EBI Control Register – EBICR ...................... 620 EBI Status Register –...
Page 17 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 CRC Checksum Register – CRCCSR ..................654 CRC Data Register – CRCDR ...................... 655 Rev. 1.30 17 of 656 September 28, 2018...
Page 18 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 List of Tables Table 1. Series Features and Peripheral List ..................32 Table 2. Document Conventions ......................34 Table 3. Register Map ..........................39 Table 4. Flash Memory and Option Byte ....................44 Table 5.
Page 19 ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Table 40. Compare Match Output Setup ....................407 Table 41. SCTM Register Map ......................410 Table 42. LSE Startup Mode Operating Current and Startup Time ............428 Table 43. RTCOUT Output Mode and Active Level Setting ..............430 Table 44.
Page 20 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 List of Figures Figure 1. Block Diagram ......................... 33 Figure 2. Cortex -M0+ Block Diagram ....................36 ® Figure 3. Bus Architecture ........................37 Figure 4. Memory Map ..........................38 Figure 5. Flash Memory Controller Block Diagram ................. 42 Figure 6.
Page 21 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Figure 40. Trigger Controller Block ....................... 236 Figure 41. Slave Controller Diagram ....................237 Figure 42. GPTM in Restart Mode ......................237 Figure 43. GPTM in Pause Mode ......................238 Figure 44. GPTM in Trigger Mode ......................239 Figure 45.
Page 22 ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Figure 81. MCTM in Restart Mode ....................... 319 Figure 82. MCTM in Pause Mode ......................320 Figure 83. MCTM in Trigger Mode ......................320 Figure 84. Master MCTMn and Slave GPTMm Connection ..............321 Figure 85.
Page 23 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Figure 121. SCTM in Restart Mode ...................... 402 Figure 122. SCTM in Pause Mode ....................... 403 Figure 123. SCTM in Trigger Mode ...................... 403 Figure 124. Capture/Compare Block Diagram ..................404 Figure 125. Input Capture Mode ......................405 Figure 126.
Page 24 ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Figure 162. USART Clock CK_USART and Data Frame Timing ............501 Figure 163. Hardware Flow Control between 2 USARTs ..............502 Figure 164. USART RTS Flow Control ....................503 Figure 165. USART CTS Flow Control ....................503 Figure 166.
Page 25 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Figure 203. I S-justified Stereo Mode Waveforms (32-bit Channel Enabled) ........631 Figure 204. Left-justified Stereo Mode Waveforms ................632 Figure 205. Left-justified Stereo Mode Waveforms (32-bit Channel Enabled) ........632 Figure 206. Right-justified Stereo Mode Waveforms ................633 Figure 207.
Page 26: Introduction
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Introduction Overview This user manual provides detailed information including how to use the devices, system and bus architecture, memory organization and peripheral instructions. The target audiences for this document are software developers, application developers and hardware developers. For more information regarding pin assignment, package and electrical characteristics, please refer to the datasheet.
Page 27: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Features ▄ Core ● 32-bit Arm ® Cortex ® -M0+ processor core ● Up to 48 MHz operating frequency ● 0.93 DMIPS/MHz (Dhrystone v2.1) ● Single-cycle multiplication ● Integrated Nested Vectored Interrupt Controller (NVIC) ●...
Page 28 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 ▄ Analog to Digital Converter – ADC ● 12-bit SAR ADC engine ● Up to 1 MSPS conversion rate ● Up to 12 external analog input channels ▄ Analog Comparator – CMP ●...
Page 29 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 ▄ Single Channel Generation and Capture Timers – SCTM ● One 16-bit up and auto-reload counter ● One channel for each timer ● 16-bit programmable prescaler allowing dividing the counter clock frequency by any factor between 1 and 65536 ●...
Page 30 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 ▄ Universal Asynchronous Receiver Transmitter – UART ● Asynchronous serial communication operating baud-rate up to (f /16) MHz PCLK ● Capability of full duplex communication ● Fully programmable characteristics of serial communication including: word length, parity bit, stop bit and bit order ●...
Page 31 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 ▄ External Bus Interface – EBI ● Programmable interface for various memory types ● Translate the AHB transactions into the appropriate external device protocol ● Individual chip select signal for per memory bank ●...
Page 32: Device Information
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Device Information Table 1. Series Features and Peripheral List Peripherals HT32F52342 HT32F52352 Main Flash (KB) 127.5 Option Bytes Flash (KB) SRAM (KB) MCTM GPTM SCTM Timers BFTM USART Communication UART SCI (ISO7816-3)
Page 33: Block Diagram
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Block Diagram PA ~ PC[15:0], PD[3:0] SWCLK SWDIO BOOT Powered by V DD15 /PDR Flash Memory Flash SW-DP Interface Memory XTALIN XTALOUT GPIO 4 ~ 16 MHz ® Cortex -M0+ PDMA Processor...
Page 34: Document Conventions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Document Conventions The conventions used in this document are shown in the following table. Table 2. Document Conventions Notation Example Description The number string with a 0x prefix indicates a hexadecimal 0x5a05 number.
Page 35: System Architecture
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 System Architecture The system architecture of devices that includes the Arm ® Cortex ® -M0+ processor, bus architecture and memory organization will be described in the following sections. The Cortex ® -M0+ is a next generation processor core which offers many new features.
Page 36: Bus Architecture
Figure 2. Cortex ® -M0+ Block Diagram Bus Architecture The HT32F52342/52352 series consist of two masters and five slaves in the bus architecture. The Cortex -M0+ AHB-Lite bus and Peripheral Direct Memory Access (PDMA) are the masters while ® the internal SRAM access bus, the internal Flash memory access bus, the AHB peripherals access bus, External Bus Interface (EBI) and the AHB to APB bridges are the slaves.
Page 37: Memory Organization
Cortex -M0+ ® ® ® ® Technical Reference Manual for more information. The following figure shows the memory map of HT32F52342/52352 series of devices, including Code, SRAM, peripheral, and other pre-defined regions. Rev. 1.30 37 of 656 September 28, 2018...
Page 38: Memory Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Memory Map 0x400F_FFFF Reserved 0x400B_8000 0x400B_0000 GPIO A ～ D 0xFFFF_FFFF 0x400A_C000 Reserved 0x400A_A000 USB SRAM Reserved 0x400A_8000 0x4009_A000 Reserved 0xE010_0000 0x4009_8000 Private peripheral bus 0x4009_2000 Reserved 0xE000_0000 0x4009_0000 PDMA Reserved 0x4008_C000...
Page 39: Table 3. Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Table 3. Register Map Start Address End Address Peripheral 0x4000_0000 0x4000_0FFF USART0 0x4000_1000 0x4000_1FFF UART0 0x4000_2000 0x4000_3FFF Reserved 0x4000_4000 0x4000_4FFF SPI0 0x4000_5000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF 0x4001_1000 0x4002_1FFF Reserved 0x4002_2000 0x4002_2FFF AFIO...
Page 40 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Start Address End Address Peripheral 0x4008_0000 0x4008_1FFF 0x4008_2000 0x4008_7FFF Reserved 0x4008_8000 0x4008_9FFF CKCU/RSTCU 0x4008_A000 0x4008_BFFF 0x4008_C000 0x4008_FFFF Reserved PDMA Control 0x4009_0000 0x4009_1FFF Registers 0x4009_2000 0x4009_7FFF Reserved 0x4009_8000 0x4009_9FFF EBI Control Registers 0x4009_A000...
Page 41: Embedded Flash Memory
Programming (IAP) or In Circuit Programming (ICP). For more information, refer to the Flash Memory Controller section. Embedded SRAM Memory The HT32F52342/52352 series contain up to 16 KB on-chip SRAM which is located at address 0x2000_0000. It support byte, half-word and word access operations. AHB Peripherals The address of the AHB peripherals ranges from 0x4008_0000 to 0x400F_FFFF.
Page 42: Flash Memory Controller (Fmc)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Flash Memory Controller (FMC) Introduction The Flash Memory Controller (FMC) provides functions of flash operation and pre-fetch buffer for the embedded on-chip Flash memory. Figure below shows the block diagram of FMC which includes programming interface, control register, pre-fetch buffer, and access interface.
Page 43: Functional Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Functional Descriptions Flash Memory Map The following figure is the Flash memory map of the system. The address ranges from 0x0000_0000 to 0x1FFF_FFFF (0.5 GB). The address from 0x1F00_0000 to 0x1F00_0FFF is mapped to Boot Loader Block (4 KB).
Page 44: Flash Memory Architecture
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Flash Memory Architecture The Flash memory consists of up to 128 KB main Flash with 512 Bytes per page and 4 KB Information Block for Boot Loader. The main Flash memory contains totally 256 pages (or 128 pages for 64 KB device) which can be erased individually.
Page 45: Booting Configuration
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Booting Configuration The system provides two kinds of booting mode which can be selected through BOOT pin. The value of BOOT pin is sampled during the power-on reset or system reset. Once the value is decided, the first 4 words of vector will be remapped to the corresponding source according to the booting mode.
Page 46: Page Erase
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Page Erase The FMC provides a page erase function which is used to reset partial content of Flash memory. Any page can be erased independently without affecting others. The following steps show the access sequence of the register for page erase.
Page 47: Mass Erase
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Mass Erase The FMC provides a complete erase function which is used for resetting all the main Flash memory content. The following steps show the sequence of the register access for mass erase. ▄...
Page 48: Word Programming
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Word Programming The FMC provides a 32 bits word programming function which is used for modifying the Flash memory content. The following steps show the sequence of register access for word programming. ▄...
Page 49: Option Byte Description
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Option Byte Description The Option Byte can be treated as an independent Flash memory which base address is 0x1FF0_0000. The following table shows the function description and memory map of Option Byte.
Page 50: Table 8. Access Permission Of Protected Main Flash Page
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Table 8. Access Permission of Protected Main Flash Page Mode ISP/IAP ICP/Debug Mode Operation Read Program Page Erase Mass Erase Notes: 1. Note that the setting of write protection is based on page. The above access permission only affects the pages that enable protection function.
Page 51: Security Protection
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Security Protection FMC provides function of Security protection to prevent illegal code/data access of Flash memory. This function is useful for protecting the software / firmware from the illegal users. The function is activated by setting the Option Byte OB_CP [0]. Once the function has been enabled, all the main Flash data access through ICP/Debug mode, programming, and page erase will not be allowed except the user’s application.
Page 52: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Map The following table shows the FMC registers and reset values. Table 10. FMC Register Map Register Offset Description Reset Value FMC Base Address = 0x4008_0000 TADR 0x000 Flash Target Address Register...
Page 53: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Descriptions Flash Target Address Register – TADR This register specifies the target address of page erase and word programming operation. offset: 0x000 Reset value: 0x0000_0000 TADB Type/Reset 0 RW 0 RW...
Page 54: Flash Write Data Register - Wrdr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Flash Write Data Register – WRDR This register specifies the data to be written for programming operation. offset: 0x004 Reset value: 0x0000_0000 WRDB Type/Reset 0 RW 0 RW 0 RW 0 RW...
Page 55: Flash Operation Command Register - Ocmr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Flash Operation Command Register – OCMR This register is used to specify the Flash operation commands that include read, read ID, word program, page erase and mass erase. Offset: 0x00C Reset value: 0x0000_0000...
Page 56: Flash Operation Control Register - Opcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Flash Operation Control Register – OPCR This register is used for controlling the command commitment and checking the status of the FMC operations. Offset: 0x010 Reset value: 0x0000_000C Reserved Type/Reset Reserved Type/Reset...
Page 57: Flash Operation Interrupt Enable Register - Oier
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Flash Operation Interrupt Enable Register – OIER This register is used to enable or disable interrupt function of FMC. The FMC generates interrupt to the controller when corresponding interrupt enable bits are set. Offset:...
Page 58: Flash Operation Interrupt And Status Register - Oisr
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Flash Operation Interrupt and Status Register – OISR This register indicates the status of the FMC interrupt to check if an operation has been finished or an error occurs. The status bits (bit [4:0]) are available when the corresponding bits in the OIER register are set.
Page 59 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions ITADF Invalid Target Address Flag 0: The target address is valid 1: The target address TADR is invalid TADR field must be below 0x1FFF_FFFF. The ITAD interrupt will be occurred if the ITADIEN bit in the OIER register is set.
Page 60: Flash Page Erase/Program Protection Status Register - Ppsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Flash Page Erase/Program Protection Status Register – PPSR This register indicates the status of Flash page erase/program protection. Offset: 0x020 (0) ~ 0x02C (3) Reset value: 0xXXXX_XXXX PPSBn Type/Reset X RO X RO...
Page 61: Flash Security Protection Status Register - Cpsr
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Flash Security Protection Status Register – CPSR This register indicates the status of the Flash Security protection. The content of this register is not dynamically updated and will only be reloaded by the Option Byte loader (which is active when any kind of reset occurs).
Page 62: Flash Vector Mapping Control Register - Vmcr
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Flash Vector Mapping Control Register – VMCR This register is used to control the mapping of vector. The reset value of VMCR is determined by booting power on the reset setting BOOT pin. Offset:...
Page 63: Flash Manufacturer And Device Id Register - Mdid
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Flash Manufacturer and Device ID Register – MDID This register specifies the manufacture ID and device part number information which can be used as the product identity. Offset: 0x180 Reset value: 0x0376_XXXX...
Page 64: Flash Page Number Status Register - Pnsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Flash Page Number Status Register – PNSR This register specifies the page number of Flash memory. Offset: 0x184 Reset value: 0x0000_00XX PNSB Type/Reset 0 RO 0 RO 0 RO 0 RO 0 RO...
Page 65: Flash Page Size Status Register - Pssr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Flash Page Size Status Register – PSSR This register specifies the page size in bytes. Offset: 0x188 Reset value: 0x0000_0200 PSSB Type/Reset 0 RO 0 RO 0 RO 0 RO 0 RO...
Page 66: Flash Cache & Pre-Fetch Control Register - Cfcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Flash Cache & Pre-fetch Control Register – CFCR This register is used for controlling the pre-fetch module of FMC. Offset: 0x200 Reset value: 0x0000_13D1 Reserved Type/Reset Reserved Type/Reset Reserved Reserved Type/Reset Reserved...
Page 67: Custom Id Register N - Cidrn, N = 0 ~ 3
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Custom ID Register n – CIDRn, n = 0 ~ 3 This register specifies the custom ID information which can be used as the custom identity. Offset: 0x310 (0) ~ 0x31C (3) Reset value: Various depending on Flash Manufacture Privilege Information Block.
Page 68: Power Control Unit (Pwrcu)
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Power Control Unit (PWRCU) Introduction The power consumption can be regarded as one of the most important issues for many embedded system applications. Accordingly the Power Control Unit, PWRCU, provides many types of power saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2, and Power-Down modes.
Page 69: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Features ▄ Three power domains: Backup, V and 1.5 V power domains. ▄ Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down modes. ▄ Internal Voltage regulator supplies 1.5 V voltage source.
Page 70: Vdd Power Domain
Cortex ® -M0+ MCU HT32F52342/HT32F52352 LSE, LSI and RTC The Real Time Clock circuitry clock source can be derived from either the Low Speed Internal RC oscillator, LSI, or the Low Speed External Crystal oscillator, LSE. Before entering the power...
Page 71: Figure 12. Power On Reset / Power Down Reset Waveform
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Power On Reset (POR) / Power Down Reset (PDR) The device has an integrated POR/PDR circuitry that allows proper operation starting from/down to 2.0 V. The device remains in Power-Down mode when V is below a specified threshold V without the need for an external reset circuit.
Page 72: 1.5 V Power Domain
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 High Speed External Oscillator The High Speed External Oscillator, HSE, is located in the V power domain. The HSE crystal oscillator can be switched on or off using the HSEEN bit in the Global Clock Control Register (GCCR).
Page 73: Table 12. Enter/Exit Power Saving Modes
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Sleep Mode By default, only the CPU clock will be stopped in the Sleep mode. Clearing the FMCEN or SRAMEN bit in the CKCU AHBCCR register to 0 will have the effect of stopping the Flash clock or SRAM clock after the system enters the Sleep mode.
Page 74: Register Map
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Power-Down Mode The Power-Down mode is derived from the Deep-Sleep mode of the CPU together with the additional control bits LDOOFF and DMOSON. To enter the Power-Down mode, users can configure the registers shown in the preceding Mode-Entering table and execute the WFI or WFE instruction.
Page 75: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Descriptions Backup Domain Status Register – BAKSR This register indicates backup domain status. Offset: 0x100 Reset value: 0x0000_0001 (Reset only by Backup Domain reset) Reserved Type/Reset Reserved Type/Reset Reserved WUPF Type/Reset...
Page 76: Backup Domain Control Register - Bakcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Backup Domain Control Register – BAKCR This register provides power control bits for the Deep-Sleep and Power-Down modes. Offset: 0x104 Reset value: 0x0000_0000 (Reset only by Backup Domain reset) Reserved Type/Reset Reserved...
Page 77 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions WUPEN External WAKEUP Pin Enable 0: Disable WAKEUP pin function. 1: Enable WAKEUP pin function. The Software can set the WUPEN bit as 1 to enable the WAKEUP pin function before entering the power saving mode.
Page 78: Backup Domain Test Register - Baktest
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Backup Domain Test Register – BAKTEST This register specifies a read-only value for the software to recognize whether backup domain is ready for access. Offset: 0x108 Reset value: 0x0000_0027 Reserved Type/Reset Reserved...
Page 79: Low Voltage / Brown Out Detect Control And Status Register - Lvdcsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Low Voltage / Brown Out Detect Control and Status Register – LVDCSR This register specifies flags, enable bits and option bits for low voltage detector. Offset: 0x110 Reset value: 0x0000_0000 (Reset only by Backup Domain reset)
Page 80 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [16] LVDEN Low Voltage Detect Enable 0: Disable Low Voltage Detect 1: Enable Low Voltage Detect Setting this bit to 1 will generate a LVD event when the V power is lower than the voltage set by LVDS bits.
Page 81: Backup Register N - Bakregn, N = 0 ~ 9
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Backup Register n – BAKREGn, n = 0 ~ 9 This register specifies backup register n for storing data during the VDD15 power-off period. Offset: 0x200 ~ 0x224 Reset value: 0x0000_0000 (Reset only by Backup Domain reset)
Page 82: Clock Control Unit (Ckcu)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Clock Control Unit (CKCU) Introduction The Clock Control unit (CKCU) provides functions of high speed internal RC oscillator (HSI), High speed external crystal oscillator (HSE), Low speed internal RC oscillator (LSI), Low speed external crystal oscillator (LSE), Phase Lock Loop (PLL), HSE clock monitor, clock prescaler, clock multiplexer and clock gating.
Page 83: Figure 13. Ckcu Block Diagram
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Prescaler Divider CK_REF 1 ~ 32 CK_LSE HSI Auto CKREFPRE CKREFEN Trimming Controller USB REF Pulse = 48 MHz CK_USB CK_USB USBEN 8 MHz PLLSRC PLLEN HSI RC = 48 MHz CK_PLL,max...
Page 84: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Features ▄ 4 ~ 16 MHz external crystal oscillator (HSE) ▄ Internal 8 MHz RC oscillator (HSI) with configuration option calibration and custom trimming capability. ▄ PLL with selectable clock source (from HSE or HSI) for system clock.
Page 85: High Speed Internal Rc Oscillator - Hsi
The frequency accuracy of the high speed internal RC oscillator HSI can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by HOLTEK for ±2% accuracy at V = 3.3 V and T = 25°C.
Page 86: Figure 15. Hsi Auto Trimming Block Diagram
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Auto Trimming HSI Block Diagram Fine-Trimming Write Register ATCEN Counter Auto Trimming Register Controller TMSEL USB Frame Pulse 1KHz /1.024KHz 32.768KHz REFCLKSEL Fine-Trimming Factory Read Register Trimming Bits Fine [7:0] 8MHZ TRIMEN...
Page 87: Phase Locked Loop - Pll
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Phase Locked Loop – PLL This PLL can provide 4 ~ 48 MHz clock output which is 1 ~ 12 multiples of a fundamental reference frequency of 4 ~ 16 MHz. The rationale of the clock synthesizer relies on the digital...
Page 88: Table 15. Output Divider2 Value Mapping
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Table 15. Output Divider2 Value Mapping Output divider 2 setup bits S[1:0] NO2 (Output divider 2 value) (POTD bits in the PLLCFGR register) Table 16. Feedback Divider2 Value Mapping Feedback divider2 setup bits B[3:0]...
Page 89: Low Speed External Crystal Oscillator - Lse
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Low Speed External Crystal Oscillator – LSE The low speed external crystal or ceramic resonator oscillator with 32,768 Hz frequency produces a low power but highly accurate clock source for the Real-Time-Clock peripheral, Watchdog Timer or system clock.
Page 90: System Clock (Ck_Sys) Selection
Cortex ® -M0+ MCU HT32F52342/HT32F52352 System Clock (CK_SYS) Selection After the system reset occurs, the default system clock source CK_SYS will be the high speed internal RC oscillator HSI. The CK_SYS may come from the HSI, HSE, LSE, LSI or PLL output clock and it can be switched from one clock source to another by changing the System Clock Switch bits, SW, in the Global Clock Control Register GCCR.
Page 91: Hse Clock Monitor
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 HSE Clock Monitor The HSE clock monitor function is enabled by the HSE Clock Monitor Enable bit CKMEN in the Global Clock Control Register, GCCR. The HSE clock monitor function should be enabled after the HSE oscillator start-up delay and disabled when the HSE oscillator is stopped.
Page 92: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Map The following table shows the CKCU register and reset value. Table 18. CKCU Register Map Register Offset Description Reset Value GCFGR 0x000 Global Clock Configuration Register 0x0000_0102 GCCR 0x004 Global Clock Control Register...
Page 93: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Descriptions Global Clock Configuration Register – GCFGR This register specifies the clock source for PLL/USART/Watchdog Timer/CKOUT. Offset: 0x000 Reset value: 0x0000_0102 LPMOD Reserved Type/Reset 0 RO 0 RO USBPRE Reserved Type/Reset...
Page 94 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [2:0] CKOUTSRC CKOUT Clock Source Selection 000: (CK_REF) is selected where CK_REF = CK_PLL / (CKREFPRE + 1) / 2 001: (HCLKC / 16) is selected 010: (CK_SYS / 16) is selected...
Page 95: Global Clock Control Register - Gccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Global Clock Control Register – GCCR This register specifies the clock enable bits. Offset: 0x004 Reset value: 0x0000_0803 Reserved Type/Reset Reserved PSRCEN CKMEN Type/Reset 0 RW Reserved HSIEN HSEEN PLLEN HSEGAIN Type/Reset...
Page 96 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions HSEGAIN External High Speed Oscillator Gain Selection 0: HSE in low gain mode 1: HSE in high gain mode [2:0] System Clock Switch 00x: CK_PLL clock out as system clock...
Page 97: Global Clock Status Register - Gcsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Global Clock Status Register – GCSR This register indicates the clock ready status. Offset: 0x008 Reset value: 0x0000_0028 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved LSIRDY LSERDY HSIRDY HSERDY PLLRDY Reserved Type/Reset...
Page 98: Global Clock Interrupt Register - Gcir
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Global Clock Interrupt Register – GCIR This register specifies the interrupt enable and flag bits. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved CKSIE Type/Reset Reserved Type/Reset Reserved CKSF Type/Reset Bits Field...
Page 99: Pll Configuration Register - Pllcfgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 PLL Configuration Register – PLLCFGR This register specifies the PLL configurations. Offset: 0x018 Reset value: 0x0000_0000 Reserved PFBD Type/Reset 0 RW 0 RW PFBD POTD Reserved Type/Reset 0 RW 0 RW Reserved...
Page 100: Ahb Configuration Register - Ahbcfgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 AHB Configuration Register – AHBCFGR This register specifies the system clock frequency. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved AHBPRE Type/Reset 0 RW 0 RW Bits Field...
Page 101: Ahb Clock Control Register - Ahbccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 AHB Clock Control Register – AHBCCR This register specifies the AHB clock enable control bits. Offset: 0x024 Reset value: 0x0000_0005 Reserved Type/Reset Reserved PDEN PCEN PBEN PAEN Type/Reset 0 RW 0 RW...
Page 102 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [10] USBEN USB Clock Enable 0: USB clock is disabled 1: USB clock is enabled Set and reset by software APBEN APB bridge Clock Enable 0: APB bridge clock is automatically disabled by hardware during Sleep mode 1: APB bridge clock is always enabled during Sleep mode Set and reset by software.
Page 103: Apb Configuration Register - Apbcfgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 APB Configuration Register – APBCFGR This register specifies the frequency of ADC conversion clock. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved ADCDIV Type/Reset 0 RW 0 RW Reserved Type/Reset Reserved Type/Reset...
Page 104: Apb Clock Control Register 0 - Apbccr0
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 APB Clock Control Register 0 – APBCCR0 This register specifies the APB peripherals clock enable bits. Offset: 0x02C Reset value: 0x0000_0000 Reserved SCI1EN Reserved I2SEN SCI0EN Type/Reset 0 RW Reserved Type/Reset EXTIEN...
Page 105 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions USR1EN USART1 Clock Enable 0: USART1 clock is disabled 1: USART1 clock is enabled Set and reset by software. USR0EN USART0 Clock Enable 0: USART0 clock is disabled 1: USART0 clock is enabled Set and reset by software.
Page 106: Apb Clock Control Register 1 - Apbccr1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 APB Clock Control Register 1 – APBCCR1 This register specifies the APB peripherals clock enable bits. Offset: 0x030 Reset value: 0x0000_0000 Reserved SCTM1EN SCTM0EN Reserved ADCCEN Type/Reset 0 RW Reserved CMPEN Reserved...
Page 107 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions GPTM0EN GPTM0 Clock Enable 0: GPTM0 clock is disabled 1: GPTM0 clock is enabled Set and reset by software. BKPREN Backup Domain Clock Enable for Registers Access 0: RTC clock is disabled 1: RTC clock is enabled Set and reset by software.
Page 108: Clock Source Status Register - Ckst
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Clock Source Status Register – CKST This register specifies the clock source status. Offset: 0x034 Reset value: 0x0100_0003 Reserved HSIST Type/Reset 0 RO 0 RO Reserved HSEST Type/Reset 0 RO Reserved PLLST...
Page 109: Apb Peripheral Clock Selection Register 0 - Apbpcsr0
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 APB Peripheral Clock Selection Register 0 – APBPCSR0 This register specifies the APB peripheral clock prescaler selection. Offset: 0x038 Reset value: 0x0000_0000 UR1PCLK UR0PCLK USR1PCLK USR0PCLK Type/Reset 0 RW 0 RW 0 RW...
Page 110 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [21:20] GPTM0PCLK GPTM0 Peripheral Clock Selection 00: PCLK = CK_AHB 01: PCLK = CK_AHB / 2 10: PCLK = CK_AHB / 4 11: PCLK = CK_AHB / 8 PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock...
Page 111: Apb Peripheral Clock Selection Register 1 - Apbpcsr1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 APB Peripheral Clock Selection Register 1 – APBPCSR1 This register specifies the APB peripheral clock prescaler selection. Offset: 0x03C Reset value: 0x0000_0000 Reserved SCTM1PCLK SCTM0PCLK Type/Reset 0 RW 0 RW 0 RW...
Page 112 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [15:14] BKPRCLK Backup Domain Register Access Clock Selection 00: PCLK = CK_AHB / 4 01: PCLK = CK_AHB / 8 10: PCLK = CK_AHB / 16 11: PCLK = CK_AHB / 32 PCLK = Peripheral Clock;...
Page 113: Hsi Control Register - Hsicr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 HSI Control Register – HSICR This register is used to control the frequency trimming of the HSI RC oscillation. Offset: 0x040 Reset value: 0xXXXX_0000 where X is undefined Reserved HSICOARSE Type/Reset X RO...
Page 114: Hsi Auto Trimming Counter Register - Hsiatcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 HSI Auto Trimming Counter Register – HSIATCR This register contains the counter value of the HSI auto trimming controller. Offset: 0x044 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved ATCNT Type/Reset 0 RO...
Page 115: Low Power Control Register - Lpcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Low Power Control Register – LPCR This register specifies the low power control. Offset: 0x300 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved USBSLEEP Type/Reset Reserved BKISO Type/Reset Bits Field Descriptions USBSLEEP USB Sleep Software Control Enable...
Page 116: Mcu Debug Control Register - Mcudbgcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 MCU Debug Control Register – MCUDBGCR This register specifies the MCU debug control. Offset: 0x304 Reset value: 0x0000_0000 Reserved Type/Reset DBSCTM1 DBSCTM0 DBSCI1 DBTRACE DBUR1 DBUR0 DBBFTM1 DBBFTM0 Type/Reset 0 RW 0 RW...
Page 117 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [16] DBBFTM0 BFTM0 Debug Mode Enable 0: BFTM0 counter continues to count even if the core is halted 1: BFTM0 counter stops counting when the core is halted Set and reset by software.
Page 118 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions DBPD Debug Power-Down Mode 0: LDO = Off, FCLK = Off, and HCLK = Off in Power-Down mode 1: LDO = On, FCLK = On, and HCLK = On in Power-Down mode Set and reset by software.
Page 119: Reset Control Unit (Rstcu)
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Reset Control Unit (RSTCU) Introduction The Reset Control Unit, RSTCU, has three kinds of reset, the power on reset, system reset and APB unit reset. The power on reset, known as a cold reset, resets the full system during a power up.
Page 120: Functional Descriptions
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Functional Descriptions Power On Reset The Power on reset, POR, is generated by either an external reset or the internal reset generator. Both types have an internal filter to prevent glitches from causing erroneous reset operations. By referring to Figure 19, the POR15 active low signal will be de-asserted when the internal LDO voltage regulator is ready to provide 1.5 V power.
Page 121: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Map The following table shows the RSTCU registers and reset values. Table 19. RSTCU Register Map Register Offset Description Reset Value RSTCU Base Address = 0x4008_8000 GRSR 0x100 Global Reset Status Register...
Page 122: Ahb Peripheral Reset Register - Ahbprstr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions NVICRSTF NVIC Reset Flag 0: No NVIC asserting system reset occurred 1: NVIC asserting system reset occurred This bit is set by hardware when a system reset occurs and reset by writing 1 into it or by hardware when a power on reset occurs.
Page 123: Apb Peripheral Reset Register 0 - Apbprstr0
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions CRCRST CRC Reset Control 0: No reset 1: Reset CRC This bit is set by software and cleared to 0 by hardware automatically. EBIRST EBI Reset Control 0: No reset 1: Reset EBI This bit is set by software and cleared to 0 by hardware automatically.
Page 124 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [24] SCI0RST Smart Card Interface 0 Reset Control 0: No reset 1: Reset Smart Card Interface This bit is set by software and cleared to 0 by hardware automatically.
Page 125: Apb Peripheral Reset Register 1 - Apbprstr1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 APB Peripheral Reset Register 1 – APBPRSTR1 This register specifies several APB peripherals software reset control bits. Offset: 0x10C Reset value: 0x0000_0000 Reserved SCTM1RST SCTM0RST Reserved ADCRST Type/Reset 0 RW Reserved CMPRST...
Page 126 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions GPTM0RST GPTM0 Reset Control 0: No reset 1: Reset GPTM0 This bit is set by software and cleared to 0 by hardware automatically. WDTRST Watchdog Timer Reset Control 0: No reset 1: Reset Watchdog Timer This bit is set by software and cleared to 0 by hardware automatically.
Page 127: General Purpose I/O (Gpio)
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 General Purpose I/O (GPIO) Introduction There are up to 51 General Purpose I/O port, GPIO, named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15 and PD0 ~ PD3 for the device to implement the logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirement of specific applications.
Page 128: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Features ▄ Input/output direction control ▄ Schmitt Trigger Input function enable control ▄ Input weak pull-up/pull-down control ▄ Output push-pull/open drain enable control ▄ Output set/reset control ▄ Output drive current selection ▄...
Page 129: Table 20. Afio, Gpio And Io Pad Control Signal True Table
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 PxCFGn Input DMUX Output AFIO OENIP Control IOPAD AFIO ADEN PxDOn PxDIn PxRSTn PxDVn PxINENn PxSETn PxODn PxDIRn PxPLn PxPHn GPIO Figure 21. AFIO/GPIO Control Signal PxDIn/PxDOn (x=A ~ D): Data Input/Data Output...
Page 130: Gpio Locking Mechanism
Cortex ® -M0+ MCU HT32F52342/HT32F52352 GPIO Locking Mechanism The GPIO also offers a lock function to lock the port until a reset event occurs. The PxLOCKR (x = A ~ D) registers are used to lock the port x and lock control options. The value 0x5FA0 is written...
Page 131: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Offset Description Reset Value PCDOUTR 0x020 Port C Data Output Register 0x0000_0000 PCSRR 0x024 Port C Output Set and Reset Control Register 0x0000_0000 PCRR 0x028 Port C Output Reset Control Register...
Page 132: Port A Input Function Enable Control Register - Painer
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port A Input Function Enable Control Register – PAINER This register is used to enable or disable the GPIO Port A input function. Offset: 0x004 Reset value: 0x0000_3300 Reserved Type/Reset Reserved Type/Reset...
Page 133: Port A Pull-Up Selection Register - Papur
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port A Pull-Up Selection Register – PAPUR This register is used to enable or disable the GPIO Port A pull-up function. Offset: 0x008 Reset value: 0x0000_3300 Reserved Type/Reset Reserved Type/Reset PAPU Type/Reset...
Page 134: Port A Pull-Down Selection Register - Papdr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port A Pull-Down Selection Register – PAPDR This register is used to enable or disable the GPIO Port A pull-down function. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PAPD Type/Reset...
Page 135: Port A Open Drain Selection Register - Paodr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port A Open Drain Selection Register – PAODR This register is used to enable or disable the GPIO Port A open drain function. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 136: Port A Output Current Drive Selection Register - Padrvr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port A Output Current Drive Selection Register – PADRVR This register specifies the GPIO Port A output driving current. Offset: 0x014 Reset value: 0x0000_0000 PADV15 PADV14 PADV13 PADV12 Type/Reset 0 RW 0 RW...
Page 137: Port A Lock Register - Palockr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port A Lock Register – PALOCKR This register specifies the GPIO Port A lock configuration. Offset: 0x018 Reset value: 0x0000_0000 PALKEY Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...
Page 138: Port A Data Input Register - Padinr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port A Data Input Register – PADINR This register specifies the GPIO Port A input data. Offset: 0x01C Reset value: 0x0000_3300 Reserved Type/Reset Reserved Type/Reset PADIN Type/Reset 0 RO 0 RO 1 RO...
Page 139: Port A Output Data Register - Padoutr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port A Output Data Register – PADOUTR This register specifies the GPIO Port A output data. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PADOUT Type/Reset 0 RW 0 RW 0 RW...
Page 140: Port A Output Set/Reset Control Register - Pasrr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port A Output Set/Reset Control Register – PASRR This register is used to set or reset the corresponding bit of the GPIO Port A output data. Offset: 0x024 Reset value: 0x0000_0000 PARST...
Page 141: Port A Output Reset Register - Parr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port A Output Reset Register – PARR This register is used to reset the corresponding bit of the GPIO Port A output data. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 142: Port B Data Direction Control Register - Pbdircr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port B Data Direction Control Register – PBDIRCR This register is used to control the direction of GPIO Port B pin as input or output. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset...
Page 143: Port B Input Function Enable Control Register - Pbiner
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port B Input Function Enable Control Register – PBINER This register is used to enable or disable the GPIO Port B input function. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 144: Port B Pull-Up Selection Register - Pbpur
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port B Pull-Up Selection Register – PBPUR This register is used to enable or disable the GPIO Port B pull-up function. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PBPU Reserved...
Page 145: Port B Pull-Down Selection Register - Pbpdr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port B Pull-Down Selection Register – PBPDR This register is used to enable or disable the GPIO Port B pull-down function. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PBPD Reserved...
Page 146: Port B Open Drain Selection Register - Pbodr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port B Open Drain Selection Register – PBODR This register is used to enable or disable the GPIO Port B open drain function. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 147: Port B Output Current Drive Selection Register - Pbdrvr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port B Output Current Drive Selection Register – PBDRVR This register specifies the GPIO Port B output driving current. Offset: 0x014 Reset value: 0x0000_0000 PBDV15 PBDV14 PBDV13 PBDV12 Type/Reset 0 RW 0 RW...
Page 148: Port B Lock Register - Pblockr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port B Lock Register – PBLOCKR This register specifies the GPIO Port B lock configuration. Offset: 0x018 Reset value: 0x0000_0000 PBLKEY Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...
Page 149: Port B Data Input Register - Pbdinr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port B Data Input Register – PBDINR This register specifies the GPIO Port B input data. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PBDIN Reserved PBDIN Type/Reset 0 RO 0 RO...
Page 150: Port B Output Data Register - Pbdoutr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port B Output Data Register – PBDOUTR This register specifies the GPIO Port B output data. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PBDOUT Reserved PBDOUT Type/Reset 0 RW 0 RW...
Page 151: Port B Output Set/Reset Control Register - Pbsrr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port B Output Set/Reset Control Register – PBSRR This register is used to set or reset the corresponding bit of the GPIO Port B output data. Offset: 0x024 Reset value: 0x0000_0000 PBRST...
Page 152: Port B Output Reset Register - Pbrr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port B Output Reset Register – PBRR This register is used to reset the corresponding bit of the GPIO Port B output data. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 153: Port C Data Direction Control Register - Pcdircr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port C Data Direction Control Register – PCDIRCR This register is used to control the direction of GPIO Port C pin as input or output. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset...
Page 154: Port C Input Function Enable Control Register - Pciner
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port C Input Function Enable Control Register – PCINER This register is used to enable or disable the GPIO Port C input function. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 155: Port C Pull-Up Selection Register - Pcpur
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port C Pull-Up Selection Register – PCPUR This register is used to enable or disable the GPIO Port C pull-up function. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PCPU Type/Reset...
Page 156: Port C Pull-Down Selection Register - Pcpdr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port C Pull-Down Selection Register – PCPDR This register is used to enable or disable the GPIO Port C pull-down function. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PCPD Type/Reset...
Page 157: Port C Open Drain Selection Register - Pcodr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port C Open Drain Selection Register – PCODR This register is used to enable or disable the GPIO Port C open drain function. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 158: Port C Output Current Drive Selection Register - Pcdrvr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port C Output Current Drive Selection Register – PCDRVR This register specifies the GPIO Port C output driving current. Offset: 0x014 Reset value: 0x0000_0000 PCDV15 PCDV14 PCDV13 PCDV12 Type/Reset 0 RW 0 RW...
Page 159: Port C Lock Register - Pclockr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port C Lock Register – PCLOCKR This register specifies the GPIO Port C lock configuration. Offset: 0x018 Reset value: 0x0000_0000 PCLKEY Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...
Page 160: Port C Data Input Register - Pcdinr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port C Data Input Register – PCDINR This register specifies the GPIO Port C input data. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PCDIN Type/Reset 0 RO 0 RO 0 RO...
Page 161: Port C Output Data Register - Pcdoutr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port C Output Data Register – PCDOUTR This register specifies the GPIO Port C output data. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PCDOUT Type/Reset 0 RW 0 RW 0 RW...
Page 162: Port C Output Set/Reset Control Register - Pcsrr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port C Output Set/Reset Control Register – PCSRR This register is used to set or reset the corresponding bit of the GPIO Port C output data. Offset: 0x024 Reset value: 0x0000_0000 PCRST...
Page 163: Port C Output Reset Register - Pcrr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port C Output Reset Register – PCRR This register is used to reset the corresponding bit of the GPIO Port C output data. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 164: Port D Data Direction Control Register - Pddircr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port D Data Direction Control Register – PDDIRCR This register is used to control the direction of GPIO Port D pin as input or output. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset...
Page 165: Port D Input Function Enable Control Register - Pdiner
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port D Input Function Enable Control Register – PDINER This register is used to enable or disable the GPIO Port D input function. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 166: Port D Pull-Up Selection Register - Pdpur
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port D Pull-Up Selection Register – PDPUR This register is used to enable or disable the GPIO Port D pull-up function. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset...
Page 167: Port D Pull-Down Selection Register - Pdpdr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port D Pull-Down Selection Register – PDPDR This register is used to enable or disable the GPIO Port D pull-down function. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset...
Page 168: Port D Open Drain Selection Register - Pdodr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port D Open Drain Selection Register – PDODR This register is used to enable or disable the GPIO Port D open drain function. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 169: Port D Output Current Drive Selection Register - Pddrvr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port D Output Current Drive Selection Register – PDDRVR This register specifies the GPIO Port D output driving current. Offset: 0x014 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset PDDV3 PDDV2...
Page 170: Port D Lock Register - Pdlockr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port D Lock Register – PDLOCKR This register specifies the GPIO Port D lock configuration. Offset: 0x018 Reset value: 0x0000_0000 PDLKEY Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...
Page 171: Port D Data Input Register - Pddinr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port D Data Input Register – PDDINR This register specifies the GPIO Port D input data. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved PDDIN Type/Reset 0 RO...
Page 172: Port D Output Data Register - Pddoutr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port D Output Data Register – PDDOUTR This register specifies the GPIO Port D output data. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved PDDOUT Type/Reset 0 RW...
Page 173: Port D Output Set/Reset Control Register - Pdsrr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port D Output Set/Reset Control Register – PDSRR This register is used to set or reset the corresponding bit of the GPIO Port D output data. Offset: 0x024 Reset value: 0x0000_0000 Reserved...
Page 174: Port D Output Reset Register - Pdrr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Port D Output Reset Register – PDRR This register is used to reset the corresponding bit of the GPIO Port D output data. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 175: Alternate Function Input/Output Control Unit (Afio)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Alternate Function Input/Output Control Unit (AFIO) Introduction In order to expand the flexibility of the GPIO or the usage of peripheral functions, each IO pin can be configured to have up to sixteen different functions such as GPIO or IP functions by setting the GPxCFGLR or GPxCFGHR register where x is the different port name.
Page 176: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Features ▄ APB slave interface for register access ▄ EXTI source selection ▄ Configurable pin function for each GPIO, up to sixteen alternative functions on each pin ▄ AFIO lock mechanism Functional Descriptions External Interrupt Pin Selection The GPIO pins are connected to the 16 EXTI lines as shown in the accompanying figure.
Page 177: Alternate Function
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Alternate Function Up to sixteen alternative functions can be chosen for each I/O pad by setting the PxCFGn [3:0] field in the GPxCFGLR or GPxCFGHR (n = 0~15, x = A~ D) registers. If the pin is selected as an unavailable item which is noted as a “N/A”...
Page 178: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Descriptions EXTI Source Selection Register 0 – ESSR0 This register specifies the IO selection of EXTI0 ~ EXTI7. Offset: 0x000 Reset value: 0x0000_0000 EXTI7PIN EXTI6PIN Type/Reset 0 RW 0 RW 0 RW...
Page 179: Exti Source Selection Register 1 - Essr1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 EXTI Source Selection Register 1 – ESSR1 This register specifies the IO selection of EXTI8~EXTI15. Offset: 0x004 Reset value: 0x0000_0000 EXTI15PIN EXTI14PIN Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...
Page 180: Gpio X Configuration Low Register - Gpxcfglr, X = A, B, C, D
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 GPIO x Configuration Low Register – GPxCFGLR, x = A, B, C, D This low register specifies the alternate function of GPIO Port x. x = A, B, C, D Offset: 0x020, 0x028, 0x030, 0x038...
Page 181: Gpio X Configuration High Register - Gpxcfghr, X = A, B, C, D
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 GPIO x Configuration High Register – GPxCFGHR, x = A, B, C, D This high register specifies the alternate function of GPIO Port x. x = A, B, C, D Offset: 0x024, 0x02C, 0x034, 0x03C...
Page 182: Nested Vectored Interrupt Controller (Nvic)
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Nested Vectored Interrupt Controller (NVIC) Introduction In order to reduce the latency and increase the interrupt processing efficiency, a tightly coupled integrated section, which is named as Nested Vectored Interrupt Controller (NVIC) is provided by the Cortex -M0+.
Page 183: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Interrupt Exception Exception Vector Priority Description Number Number type Address Reserved — 0x07C — Reserved — 0x080 — BFTM0 Configurable 0x084 BFTM0 global interrupt BFTM1 Configurable 0x088 BFTM1 global interrupt Configurable 0x08C...
Page 184: Function Descriptions
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Function Descriptions SysTick Calibration The SysTick Calibration Value Register (SCALIB) is provided by the NVIC to give a reference time base of 1ms for the RTOS tick timer or other purpose. The TENMS field in the SCALIB register...
Page 185: External Interrupt/Event Controller (Exti)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 External Interrupt/Event Controller (EXTI) Introduction The External Interrupt/Event Controller, EXTI, comprises 16 edge detectors which can generate a wake-up event or interrupt requests independently. In interrupt mode there are five trigger types...
Page 186: Function Descriptions
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Function Descriptions Wakeup Event Management In order to wakeup the system from the power saving mode, the EXTI controller provides a function which can monitor external events and send them to the CPU core and the Clock Control Unit, CKCU.
Page 187: External Interrupt/Event Line Mapping
Cortex ® -M0+ MCU HT32F52342/HT32F52352 External Interrupt/Event Line Mapping All GPIO pins can be selected as EXTI trigger sources by configuring the EXTInPIN [3:0] field in the AFIO ESSRn (n= 0 ~ 1) register to trigger an interrupt or event. Refer to the AFIO section for more details.
Page 188: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Map The following table shows the EXTI registers and reset values. Table 26. EXTI Register Map Register Offset Description Reset Value EXTICFGR0 0x000 EXTI Interrupt 0 Configuration Register 0x0000_0000 EXTICFGR1 0x004...
Page 189: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Descriptions EXTI Interrupt Configuration Register n – EXTICFGRn, n = 0 ~ 15 This register is used to specify the debounce function and select the trigger type. Offset: 0x000 (0) ~ 0x03C (15)
Page 190: Exti Interrupt Control Register - Exticr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 EXTI Interrupt Control Register – EXTICR This register is used to control the EXTI interrupt. Offset: 0x040 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15EN EXTI14EN EXTI13EN EXTI12EN EXTI11EN EXTI10EN EXTI9EN EXTI8EN...
Page 191: Exti Interrupt Edge Flag Register - Extiedgeflgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR This register is used to indicate if an EXTI edge has been detected. Offset: 0x044 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15EDF EXTI14EDF EXTI13EDF EXTI12EDF EXTI11EDF EXTI10EDF EXTI9EDF...
Page 192: Exti Interrupt Edge Status Register - Extiedgesr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 EXTI Interrupt Edge Status Register – EXTIEDGESR This register indicates the polarity of a detected EXTI edge. Offset: 0x048 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15EDS EXTI14EDS EXTI13EDS EXTI12EDS EXTI11EDS EXTI10EDS EXTI9EDS...
Page 193: Exti Interrupt Software Set Command Register - Extisscr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 EXTI Interrupt Software Set Command Register – EXTISSCR This register is used to activate the EXTI interrupt. Offset: 0x04C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15SC EXTI14SC EXTI13SC EXTI12SC EXTI11SC EXTI10SC...
Page 194: Exti Interrupt Wakeup Control Register - Extiwakupcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR This register is used to control the EXTI interrupt and wakeup function. Offset: 0x050 Reset value: 0x0000_0000 EVWUPIEN Reserved Type/Reset Reserved Type/Reset EXTI15WEN EXTI14WEN EXTI13WEN EXTI12WEN EXTI11WEN EXTI10WEN EXTI9WEN...
Page 195: Exti Interrupt Wakeup Polarity Register - Extiwakuppolr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR This register is used to select the EXTI line interrupt wakeup polarity. Offset: 0x054 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15WPOL EXTI14WPOL EXTI13WPOL EXTI12WPOL EXTI11WPOL EXTI10WPOL EXTI9WPOL EXTI8WPOL...
Page 196: Exti Interrupt Wakeup Flag Register - Extiwakupflg
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG This register is the EXTI interrupt wake flag register. Offset: 0x058 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15WFL EXTI14WFL EXTI13WFL EXTI12WFL EXTI11WFL EXTI10WFL EXTI9WFL...
Page 197: Analog To Digital Converter (Adc)
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Analog to Digital Converter (ADC) Introduction A 12-bit multi-channel Analog to Digital Converter is integrated in the device. There are a total of 14 multiplexed channels including 12 external channels on which the external analog signal can be supplied and 2 internal channels.
Page 198: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Features ▄ 12-bit SAR ADC engine ▄ Up to 1 MSPS conversion rate ▄ 12 external analog input channels ▄ 2 internal analog input channels for reference voltage detection ▄ Programmable sampling time for conversion channel ▄...
Page 199: Function Descriptions
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Function Descriptions ADC Clock Setup The ADC clock, CK_ADC is provided by the Clock Controller which is synchronous and divided by with the AHB clock known as HCLK. Refer to the Clock Control Unit chapter for more details.
Page 200: Figure 28. One Shot Conversion Mode
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Conversion (ex: Sequence Length=8) Cycle Cycle Start of Conversion Single sample End of Conversion Cycle End of Conversion Figure 28. One Shot Conversion Mode Continuous Conversion Mode In the Continuous Conversion Mode, repeated conversion cycle will restart automatically without requiring additional A/D start trigger signals after a channel group conversion has completed.
Page 201 ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Discontinuous Conversion Mode The A/D converter will operate in the Discontinuous Conversion Mode for channels group when the A/D conversion mode bit field ADMODE [1:0] in the ADCCONV register is set to 0x3. The group to be converted can have up to 8 channels and can be arranged in a specific sequence by configuring the ADCLSTn registers where n ranges from 0 to 1.
Page 202: Start Conversion On External Event
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Discontinuous Conversion Mode (ex: Sequence Length=8, Subgroup Length=3 ) Cycle Cycle Subgroup 0 Subgroup 1 Subgroup 2 Subgroup 0 Start of Conversion Single sample End of Conversion Subgroup End of Conversion Cycle End of Conversion Figure 30.
Page 203: Sampling Time Setting
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Sampling Time Setting The conversion channel sampling time can be programmed according to the input resistance of the input voltage source. This sampling time must be enough for the input voltage source to charge the internal sample and hold capacitor in A/D the converter to the input voltage level.
Page 204: Interrupts
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Interrupts When an A/D conversion is completed, an End of Conversion EOC event will occur. There are three kinds of EOC events which are known as single sample EOC, subgroup EOC and cycle EOC for A/D conversion.
Page 205: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Map The following table shows the A/D Converter registers and reset values. Table 28. A/D Converter Register Map Register Offset Description Reset Value ADCCR 0x000 ADC Conversion Control Register 0x0000_0000 ADCLST0...
Page 206: Register Descriptions
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Descriptions ADC Conversion Control Register – ADCCR This register specifies the mode setting, sequence length, and subgroup length of the ADC conversion mode. Note that once the content of ADCCR is changed, the conversion in progress will be aborted and the A/D converter will return to an idle state.
Page 207 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [1:0] ADMODE ADC Conversion Mode ADMODE [1:0] Mode Descriptions After a start trigger, the conversion will be One shot mode executed on the specific channels for the whole conversion sequence once.
Page 208: Adc Conversion List Register 0 - Adclst0
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 ADC Conversion List Register 0 – ADCLST0 This register specifies the conversion sequence order No.0 ~ No.3 of the ADC. Offset: 0x004 Reset value: 0x0000_0000 Reserved ADSEQ3 Type/Reset 0 RW 0 RW...
Page 209: Adc Conversion List Register 1 - Adclst1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 ADC Conversion List Register 1 – ADCLST1 This register specifies the conversion sequence order No.4 ~ No.7 of the ADC. Offset: 0x008 Reset value: 0x0000_0000 Reserved ADSEQ7 Type/Reset 0 RW 0 RW...
Page 210: Adc Input Sampling Time Register - Adcstr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 ADC Input Sampling Time Register – ADCSTR This register specifies the A/D converter input channel sampling time. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset ADST Type/Reset 0 RW...
Page 211: Adc Conversion Data Register Y - Adcdry, Y = 0 ~ 7
Cortex ® -M0+ MCU HT32F52342/HT32F52352 ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7 This register is used to store the conversion data of the conversion sequence order No.y which is specified by the ADSEQy field in the ADCLSTn (n= 0 ~ 1) registers.
Page 212: Adc Trigger Control Register - Adctcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 ADC Trigger Control Register – ADCTCR This register contains the ADC start conversion trigger enable bits. Offset: 0x070 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved BFTM ADEXTI ADSW Type/Reset...
Page 213: Adc Trigger Source Register - Adctsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 ADC Trigger Source Register – ADCTSR This register contains the trigger source selection and the software trigger bit of the conversion. Offset: 0x074 Reset value: 0x0000_0000 Reserved Type/Reset 0 RW 0 RW...
Page 214: Adc Watchdog Control Register - Adcwcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 ADC Watchdog Control Register – ADCWCR This register provides the control bits and status of the ADC watchdog function. Offset: 0x078 Reset value: 0x0000_0000 Reserved ADUCH Type/Reset 0 RO 0 RO 0 RO...
Page 215: Adc Watchdog Threshold Register - Adctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions ADWUE ADC Watchdog Upper Threshold Enable Bit 0: Disable upper threshold monitor function 1: Enable upper threshold monitor function ADWLE ADC Watchdog Lower Threshold Enable Bit 0: Disable lower threshold monitor function 1: Enable lower threshold monitor function ADC Watchdog Threshold Register –...
Page 216: Adc Interrupt Enable Register - Adcier
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 ADC Interrupt Enable Register – ADCIER This register contains the ADC interrupt enable bits. Offset: 0x080 Reset value: 0x0000_0000 Reserved ADIEO Type/Reset Reserved ADIEU ADIEL Type/Reset 0 RW Reserved Type/Reset Reserved ADIEC...
Page 217: Adc Interrupt Raw Status Register - Adciraw
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 ADC Interrupt Raw Status Register – ADCIRAW This register contains the ADC interrupt raw status bits. Offset: 0x084 Reset value: 0x0000_0000 Reserved ADIRAWO Type/Reset Reserved ADIRAWU ADIRAWL Type/Reset 0 RO Reserved Type/Reset...
Page 218: Adc Interrupt Status Register - Adcisr
Cortex ® -M0+ MCU HT32F52342/HT32F52352 ADC Interrupt Status Register – ADCISR This register contains the ADC interrupt masked status bits. The corresponding interrupt status will be set to 1 if the associated interrupt event occurs and the related enable bit is set to 1.
Page 219: Adc Interrupt Clear Register - Adciclr
Cortex ® -M0+ MCU HT32F52342/HT32F52352 ADC Interrupt Clear Register – ADCICLR This register provides the clear bits used to clear the interrupt raw and masked status of the ADC. These bits are set to 1 by software to clear the interrupt status and automatically cleared to 0 by hardware after being set to 1.
Page 220: Adc Dma Request Register - Adcdmar
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 ADC DMA Request Register – ADCDMAR This register contains the ADC DMA request enable bits. Offset: 0x090 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved ADDMAC ADDMAG ADDMAS Type/Reset 0 RW...
Page 221: Comparator (Cmp)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Comparator (CMP) Introduction The two general purpose comparators (CMP) are implemented within the device. They can be configured either as standalone comparators or combined with the different kinds of peripheral IP. Each comparator is capable of asserting interrupts to the NVIC or wakeup the CPU Deep Sleep mode through EXTI wakeup event management unit.
Page 222: Function Descriptions
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Function Descriptions Comparator Inputs and Output The I/O pins used as comparator inputs or output must be configured in the AFIO controller registers. The detail comparator I/Os information will be referred in the pin assignment table in the datasheet.
Page 223: Interrupts And Wakeup
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Interrupts and Wakeup The comparator can generate an interrupt when its output waveform generates a rising or falling edge and its corresponding interrupt enables control bit is also set. For example, when a comparator output rising edge occurs, the comparator rising edge flag bit CMPRF in the Comparator Transition Flag Register CMPTFR will be set.
Page 224: Power Mode And Hysteresis
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Power Mode and Hysteresis The comparator response time can be programmed to meet the trade-off between the power consumption and application requirement. The bit CMPSM in CMPCR register can be programmed as “1” to get the comparator in the low speed mode with low power consumption.
Page 225: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Descriptions Comparator Control Register n – CMPCRn, n = 0 or 1 This register contains the comparator function and comparator voltage reference control bits. Offset: 0x000 (n = 0), 0x100 (n = 1)
Page 226 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [13:11] CMPOSEL Comparator 0 Output Selection 000: No selection 001: GPTM0 capture channel 3 010: MCTM capture channel 3 011: MCTM break input 1 100: ADC trigger input Other: Reserved...
Page 227: Comparator Voltage Reference Value Register N - Cvrvalrn, N = 0 Or 1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Comparator Voltage Reference Value Register n – CVRVALRn, n = 0 or 1 The register is used to set the comparator voltage reference level. Offset: 0x004 (n = 0), 0x104 (n = 1)
Page 228: Comparator Interrupt Enable Register N - Cmpiern, N = 0 Or 1
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Comparator Interrupt Enable Register n – CMPIERn, n = 0 or 1 The register is used to enable the comparator n interrupt when the comparator output transition event occurs. Offset: 0x008 (n = 0), 0x108 (n = 1)
Page 229: Comparator Transition Flag Register N - Cmptfrn, N = 0 Or 1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Comparator Transition Flag Register n – CMPTFRn, n = 0 or 1 This register contains the comparator n transition detection enable bits and flags. Offset: 0x00C (n = 0), 0x10C (n = 1)
Page 230: General-Purpose Timer (Gptm)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 General-Purpose Timer (GPTM) Introduction The General-Purpose Timer consists of one 16-bit up/down-counter, four 16-bit Capture/ Compare Registers (CCRs), one 16-bit Counter-Reload Register (CRR) and several control/status registers. It can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as single pulse generation or PWM output.
Page 231: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Features ▄ 16-bit up/down auto-reload counter ▄ 16-bit programmable prescaler that allows division of the counter clock frequency by any factor between 1 and 65536 ▄ Up to 4 independent channels for: ●...
Page 232: Functional Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Functional Descriptions Counter Mode Up-Counting In this mode the counter counts continuously from 0 to the counter-reload value, which is defined in the CRR register, in a count-up direction. Once the counter reaches the counter-reload value, the Timer Module generates an overflow event and the counter restarts to count once again from 0.
Page 233: Figure 37. Down-Counting Example
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Down-Counting In this mode the counter counts continuously from the counter-reload value, which is defined in the CRR register, to 0 in a count-down direction. Once the counter reaches 0, the Timer module generates an underflow event and the counter restarts to count once again from the counter-reload value.
Page 234: Figure 38. Center-Aligned Counting Example
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Center-Align Counting In the center-aligned counting mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The Timer module generates an overflow event when the counter counts to the counter-reload value in the up-counting mode and generates an underflow event when the counter counts to 0 in the down-counting mode.
Page 235: Clock Controller
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Clock Controller The following describes the Timer Module clock controller which determines the clock source of the internal prescaler counter. ▄ Internal APB clock f CLKIN The default internal clock source is the APB clock f...
Page 236: Trigger Controller
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Trigger Controller The trigger controller is used to select the trigger source and setup the trigger level or edge trigger condition. For the internal trigger input, it can be selected by the Trigger Selection bits TRSEL in the TRCFR register.
Page 237: Slave Controller
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Slave Controller The GPTM can be synchronized with an external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which is selected by the SMSEL field in the MDCFR register.
Page 238: Figure 43. Gptm In Pause Mode
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Pause Mode In the Pause Mode, the selected STI input signal level is used to control the counter start/stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level, here the counter will maintain its present value and will not be reset.
Page 239: Figure 44. Gptm In Trigger Mode
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Trigger Mode After the counter is disabled to count, the counter can resume counting when a STI rising edge signal occurs. When an STI rising edge occurs, the counter will start to count from the current value in the counter.
Page 240: Master Controller
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Master Controller The GPTMs and MCTMs can be linked together internally for timer synchronization or chaining. When one GPTM is configured to be in the Master Mode, the GPTM Master Controller will generate a Master Trigger Output (MTO) signal which includes a reset, a start, a stop signal or a clock source which is selected by the MMSEL field in the MDCFR register to trigger or drive another GPTM or MCTM, if exists, which is configured in the Slave Mode.
Page 241: Channel Controller
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel Controller The GPTM has four independent channels which can be used as capture inputs or compare match outputs. Each capture input or compare match output channel is composed of a preload register and a shadow register.
Page 242: Figure 48. Input Capture Mode
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Capture Counter Value Transferred to CHxCCR When the channel is used as a capture input, the counter value is captured into the Channel Capture/Compare Register (CHxCCR) when an effective input signal transition occurs. Once the capture event occurs, the CHxCCIF flag in the INTSR register is set accordingly.
Page 243: Figure 49. Pwm Pulse Width Measurement Example
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Pulse Width Measurement The input capture mode can be also used for pulse width measurement from signals on the GT_ CHx pins, TIx. The following example shows how to configure the GPTM operated in the input capture mode to measure the high pulse width and the input period on the GT_CH0 pin using channel 0 and channel 1.
Page 244: Input Stage
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Input Stage The input stage consists of a digital filter, a channel polarity selection, edge detection and a channel prescaler. The channel 0 input signal (TI0) can be chosen to come from the GT_CH0 signal or the Excusive-OR function of the GT_CH0, GT_CH1 and GT_CH2 signals.
Page 245: Figure 51. Channel 2 And Channel 3 Input Stages
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 TRCED CH2CCS CLKIN GT_CH2 TI2FP Filter Edge TI2S2 TI2S2ED sampling TI2FN Detection CH2PSC TI2F CH2PRESCALER CH2P CH2CAP Event TI3S2 Edge TI3S2ED CH2PSC Detection TI2S3 Edge TI2S3ED Detection CH3P CH3PSC TI3FP GT_CH3 CH3PRESCALER...
Page 246: Quadrature Decoder
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Quadrature Decoder The Quadrature Decoder function uses two quadrantal inputs TI0 and TI1 derived from the GT_ CH0 and GT_CH1 pins respectively to interact to generate the counter value. The DIR bit is modified by hardware automatically during each input source transition. The input source can be either TI0 only, TI1 only or both TI0 and TI1, the selection made by setting the SMSEL field to 0x01, 0x02 or 0x03.
Page 247: Table 30. Counting Direction And Encoding Signals
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Table 30. Counting Direction and Encoding Signals TI0S0 TI1S1 Counting mode Level Rising Falling Rising Falling TI1S1 = High Down — — Counting on TI0 only (SMSEL = 0x01) TI1S1 = Low Down —...
Page 248: Output Stage
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Output Stage The GPTM has four channels for compare match, single pulse or PWM output function. The channel output GT_CHxO is controlled by the CHxOM, CHxP and CHxE bits in the corresponding CHxOCFR, CHPOLR and CHCTR registers.
Page 249: Figure 56. Toggle Mode Channel Output Reference Signal (Chxpre = 0)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Counter Value CHxOM=0x03, CHxPRE=0 (Output toggle, preload disable) CHxCCR (New value 2) CHxCCR (New value 3) CHxCCR (New value 1) CHxCCR Time Update CHxCCR value CHxOREF (Update Event) Figure 56. Toggle Mode Channel Output Reference Signal (CHxPRE = 0)
Page 250: Figure 58. Pwm Mode Channel Output Reference Signal And Counter In Up-Counting Mode
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Counter Value Counter Value Counter Value CHxCCR CHxCCR CHxCCR = 0x00 CHxOM = 0x06 100% CHxOREF CHxOREF CHxOREF CHxCCIF CHxCCIF CHxCCIF CHxOM = 0x07 CHxOREF Figure 58. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode...
Page 251: Figure 60. Pwm Mode Channel Output Reference Signal And Counter In Centre-Align Mode
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 CRR = 5 CMSEL= 0x01 Up-counting Down-counting CHxCCR = 3 CHxCCIF CHxCCR = 4 CHxCCIF CHxCCR >= 5 100% CHxCCIF CHxCCR = 0 CHxCCIF Figure 60. PWM Mode Channel Output Reference Signal and Counter in Centre-align Mode Rev.
Page 252: Update Management
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Update Management The Update event is used to update the CRR, the PSCR, the CHxACR and the CHxCCR values from the actual registers to the corresponding shadow registers. An update event occurs when the counter overflows or underflows, the software update control bit is triggered or an update event from the slave controller is generated.
Page 253: Single Pulse Mode
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Single Pulse Mode Once the timer is set to operate in the single pulse mode, it is not necessary to set the timer enable bit TME in the CTR register to 1 to enable the counter. The trigger to generate a pulse can be sourced from the STI signal rising edge or by setting the TME bit to 1 using software.
Page 254: Figure 63. Immediate Active Mode Minimum Delay
Cortex ® -M0+ MCU HT32F52342/HT32F52352 In the Single Pulse mode, the STI active edge which sets the TME bit to 1 will enable the counter. However, there exist several clock delays to perform the comparison result between the counter value and the CHxCCR value. In order to reduce the delay to a minimum value, the user can set the CHxIMAE bit in each CHxOCFR register.
Page 255: Asymmetric Pwm Mode
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Asymmetric PWM Mode Asymmetric PWM mode allows two center-aligned PWM signals to be generated with a programmable phase shift. While the PWM frequency is determined by the value of the CRR register, the duty cycle and the phase-shift are determined by the CHxCCR and CHxACR register.
Page 256: Timer Interconnection
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Interconnection The timers can be internally connected together for timer chaining or synchronization. This can be implemented by configuring one timer to operate in the Master mode while configuring another timer to be in the Slave mode. The following figures present several examples of trigger selection for the master and slave modes.
Page 257: Figure 66. Triggering Gptm1 With Gptm0 Update Event
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Using one timer to trigger another timer start counting ▄ Configure GPTM0 to operate in the master mode to send its Update Event UEV as the trigger output (MMSEL = 0x02). ▄...
Page 258: Figure 67. Trigger Gptm0 And Gptm1 With The Gptm0 Ch0 Input
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Starting two timers synchronously in response to an external trigger ▄ Configure GPTM0 to operate in the master mode to send its enable signal as a trigger output (MMSEL = 0x01). ▄...
Page 259: Trigger Adc Start
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Trigger ADC Start To interconnect to the Analog-to-Digital Converter, the GPTM can output the MTO signal or the channel compare match output signal CHxOREF (x = 0 ~ 3) to be used as an Analog-to-Digital Converter input trigger signal.
Page 260: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Map The following table shows the GPTM registers and reset values. Table 32. GPTM Register Map Register Offset Description Reset Value CNTCFR 0x000 Timer Counter Configuration Register 0x0000_0000 MDCFR 0x004 Timer Mode Configuration Register...
Page 261: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Descriptions Timer Counter Configuration Register – CNTCFR This register specifies the GPTM counter configuration. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CMSEL Type/Reset 0 RW Reserved CKDIV Type/Reset 0 RW...
Page 262 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions UGDIS Update event interrupt generation disable control 0: Any of the following events will generate an update PDMA request or interrupt - Counter overflow/underflow - Setting the UEVG bit...
Page 263: Timer Mode Configuration Register - Mdcfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Mode Configuration Register – MDCFR This register specifies the GPTM master and slave mode selection and single pulse mode. Offset: 0x004 Reset value: 0x0000_0000 Reserved SPMSET Type/Reset Reserved MMSEL Type/Reset 0 RW...
Page 264 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [18:16] MMSEL Master Mode Selection Master mode selection is used to select the MTO signal source which is used to synchronize the other slave timer. MMSEL [2:0] Mode Descriptions...
Page 265 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [10:8] SMSEL Slave Mode Selection SMSEL [2:0] Mode Descriptions The prescaler is clocked directly by the internal Disable mode clock. The counter uses the clock pulse generated from the interaction between the TI0 and Quadrature Decoder TI1 signals to drive the counter prescaler.
Page 266: Timer Trigger Configuration Register - Trcfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Trigger Configuration Register – TRCFR This register specifies the trigger source selection of GPTM. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved TRSEL Type/Reset 0 RW 0 RW...
Page 267: Timer Counter Register - Ctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Counter Register – CTR This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE) and Channel PDMA selection bit (CHCCDS). Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved...
Page 268: Channel 0 Input Configuration Register - Ch0Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 0 Input Configuration Register – CH0ICFR This register specifies the channel 0 input mode configuration. Offset: 0x020 Reset value: 0x0000_0000 TI0SRC Reserved Type/Reset Reserved CH0PSC CH0CCS Type/Reset 0 RW 0 RW...
Page 269 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [3:0] TI0F Channel 0 Input Source TI0 Filter Setting These bits define the frequency divided ratio used to sample the TI0 signal. The Digital filter in the GPTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
Page 270: Channel 1 Input Configuration Register - Ch1Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 1 Input Configuration Register – CH1ICFR This register specifies the channel 1 input mode configuration. Offset: 0x024 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CH1PSC CH1CCS Type/Reset 0 RW 0 RW 0 RW...
Page 271 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [3:0] TI1F Channel 1 Input Source TI1 Filter Setting These bits define the frequency divided ratio used to sample the TI1 signal. The Digital filter in the GPTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
Page 272: Channel 2 Input Configuration Register - Ch2Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 2 Input Configuration Register – CH2ICFR This register specifies the channel 2 input mode configuration. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CH2PSC CH2CCS Type/Reset 0 RW 0 RW 0 RW...
Page 273 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [3:0] TI2F Channel 2 Input Source TI2 Filter Setting These bits define the frequency divided ratio used to sample the TI2 signal. The Digital filter in the GPTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
Page 274: Channel 3 Input Configuration Register - Ch3Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 3 Input Configuration Register – CH3ICFR This register specifies the channel 3 input mode configuration. Offset: 0x02C Reset value: 0x0000_0000 Reserved Type/Reset Reserved CH3PSC CH3CCS Type/Reset 0 RW 0 RW 0 RW...
Page 275 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [3:0] TI3F Channel 3 Input Source TI3 Filter Setting These bits define the frequency divided ratio used to sample the TI3 signal. The Digital filter in the GPTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
Page 276: Channel 0 Output Configuration Register - Ch0Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 0 Output Configuration Register – CH0OCFR This register specifies the channel 0 output mode configuration. Offset: 0x040 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH0OM[3] Type/Reset Reserved CH0IMAE CH0PRE Reserved...
Page 277 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [8][2:0] CH0OM[3:0] Channel 0 Output Mode Setting These bits define the functional types of the output reference signal CH0OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
Page 278: Channel 1 Output Configuration Register - Ch1Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 1 Output Configuration Register – CH1OCFR This register specifies the channel 1 output mode configuration. Offset: 0x044 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH1OM[3] Type/Reset Reserved CH1IMAE CH1PRE Reserved...
Page 279 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [8][2:0] CH1OM[3:0] Channel 1 Output Mode Setting These bits define the functional types of the output reference signal CH1OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
Page 280: Channel 2 Output Configuration Register - Ch2Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 2 Output Configuration Register – CH2OCFR This register specifies the channel 2 output mode configuration. Offset: 0x048 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH2OM[3] Type/Reset Reserved CH2IMAE CH2PRE Reserved...
Page 281 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [8][2:0] CH2OM[3:0] Channel 2 Output Mode Setting These bits define the functional types of the output reference signal CH2OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
Page 282: Channel 3 Output Configuration Register - Ch3Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 3 Output Configuration Register – CH3OCFR This register specifies the channel 3 output mode configuration. Offset: 0x04C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH3OM[3] Type/Reset Reserved CH3IMAE CH3PRE Reserved...
Page 283 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [8][2:0] CH3OM[3:0] Channel 3 Output Mode Setting These bits define the functional types of the output reference signal CH3OREF 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
Page 284: Channel Control Register - Chctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel Control Register – CHCTR This register contains the channel capture input or compare output function enable control bits. Offset: 0x050 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3E...
Page 285: Channel Polarity Configuration Register - Chpolr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel Polarity Configuration Register – CHPOLR This register contains the channel capture input or compare output polarity control. Offset: 0x054 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3P Reserved...
Page 286: Timer Pdma/Interrupt Control Register - Dictr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer PDMA/Interrupt Control Register – DICTR This register contains the timer PDMA and interrupt enable control bits. Offset: 0x074 Reset value: 0x0000_0000 Reserved TEVDE Reserved UEVDE Type/Reset Reserved CH3CCDE CH2CCDE CH1CCDE CH0CCDE...
Page 287 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions CH1CCIE Channel 1 Capture/Compare Interrupt Enable 0: Channel 1 interrupt is disabled 1: Channel 1 interrupt is enabled CH0CCIE Channel 0 Capture/Compare Interrupt Enable 0: Channel 0 interrupt is disabled 1: Channel 0 interrupt is enabled Rev.
Page 288: Timer Event Generator Register - Evgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Event Generator Register – EVGR This register contains the software event generation bits. Offset: 0x078 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVG Reserved UEVG Type/Reset Reserved CH3CCG CH2CCG CH1CCG...
Page 289 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions CH1CCG Channel 1 Capture/Compare Generation A Channel 1 capture/compare event can be generated by setting this bit. It is cleared by hardware automatically. 0: No action 1: Capture/compare event is generated on channel 1 If Channel 1 is configured as an input, the counter value is captured into the CH1CCR register and then the CH1CCIF bit is set.
Page 290: Timer Interrupt Status Register - Intsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Interrupt Status Register – INTSR This register stores the timer interrupt status. Offset: 0x07C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVIF Reserved UEVIF Type/Reset CH3OCF CH2OCF CH1OCF CH0OCF CH3CCIF...
Page 291 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions CH0OCF Channel 0 Over-Capture Flag This flag is set by hardware and cleared by software. 0: No over-capture event is detected 1: Capture event occurs again when the CH0CCIFbit is already set and it is not yet cleared by software.
Page 292 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions CH0CCIF Channel 0 Capture/Compare Interrupt Flag - Channel 0 is configured as an output: 0: No match event occurs 1: The contents of the counter CNTR have matched the content of the CH0CCR...
Page 293: Timer Counter Register - Cntr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Counter Register – CNTR This register stores the timer counter value. Offset: 0x080 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CNTV Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...
Page 294: Timer Prescaler Register - Pscr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Prescaler Register – PSCR This register specifies the timer prescaler value to generate the counter clock. Offset: 0x084 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PSCV Type/Reset 0 RW 0 RW...
Page 295: Timer Counter Reload Register - Crr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Counter Reload Register – CRR This register specifies the timer counter reload value. Offset: 0x088 Reset value: 0x0000_FFFF Reserved Type/Reset Reserved Type/Reset Type/Reset 1 RW 1 RW 1 RW 1 RW...
Page 296: Channel 0 Capture/Compare Register - Ch0Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 0 Capture/Compare Register – CH0CCR This register specifies the timer channel 0 capture/compare value. Offset: 0x090 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH0CCV Type/Reset 0 RW 0 RW 0 RW...
Page 297: Channel 1 Capture/Compare Register - Ch1Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 1 Capture/Compare Register – CH1CCR This register specifies the timer channel 1 capture/compare value. Offset: 0x094 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH1CCV Type/Reset 0 RW 0 RW 0 RW...
Page 298: Channel 2 Capture/Compare Register - Ch2Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 2 Capture/Compare Register – CH2CCR This register specifies the timer channel 2 capture/compare value. Offset: 0x098 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2CCV Type/Reset 0 RW 0 RW 0 RW...
Page 299: Channel 3 Capture/Compare Register - Ch3Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 3 Capture/Compare Register – CH3CCR This register specifies the timer channel 3 capture/compare value. Offset: 0x09C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH3CCV Type/Reset 0 RW 0 RW 0 RW...
Page 300: Channel 0 Asymmetric Compare Register - Ch0Acr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 0 Asymmetric Compare Register – CH0ACR This register specifies the timer channel 0 asymmetric compare value. Offset: 0x0A0 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH0ACV Type/Reset 0 RW 0 RW...
Page 301: Channel 1 Asymmetric Compare Register - Ch1Acr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 1 Asymmetric Compare Register – CH1ACR This register specifies the timer channel 1 asymmetric compare value. Offset: 0x0A4 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH1ACV Type/Reset 0 RW 0 RW...
Page 302: Channel 2 Asymmetric Compare Register - Ch2Acr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 2 Asymmetric Compare Register – CH2ACR This register specifies the timer channel 2 asymmetric compare value. Offset: 0x0A8 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2ACV Type/Reset 0 RW 0 RW...
Page 303: Channel 3 Asymmetric Compare Register - Ch3Acr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 3 Asymmetric Compare Register – CH3ACR This register specifies the timer channel 3 asymmetric compare value. Offset: 0x0AC Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH3ACV Type/Reset 0 RW 0 RW...
Page 304: Basic Function Timer (Bftm)
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Basic Function Timer (BFTM) Introduction The Basic Function Timer Module, BFTM, is a 32-bit up-counting counter designed to measure time intervals, generate one shot or generate repetitive interrupts. The BFTM can operate in two modes which are repetitive and one shot modes.
Page 305: Functional Description
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Functional Description The BFTM is a 32-bit up-counting counter which is driven by the BFTM APB clock, PCLK. The counter value can be changed or read at any time even when the timer is counting. The BFTM supports two operating modes known as the repetitive mode and one shot mode allowing the measurement of time intervals or the generation of periodic time durations.
Page 306: One Shot Mode
Cortex ® -M0+ MCU HT32F52342/HT32F52352 One Shot Mode By setting the OSM bit in BFTMCR register to 1, the BFTM will operate in the one shot mode. The BFTM starts to count when the CEN bit is set to 1 by the application program. The counter value will remain unchanged if the CEN bit is cleared to 0 by the application program.
Page 307: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Map The following table shows the BFTM registers and their reset values. Table 34. BFTM Register Map Register Offset Description Reset Value BFTMCR 0x000 BFTM Control Register 0x0000_0000 BFTMSR 0x004 BFTM Status Register...
Page 308: Bftm Status Register - Bftmsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 BFTM Status Register – BFTMSR This register specifies the BFTM status. Offset: 0x004 Reset value: 0x0000_0004 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Bits Field Descriptions BFTM Compare Match Interrupt Flag...
Page 309: Bftm Counter Register - Bftmcntr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 BFTM Counter Register – BFTMCNTR This register specifies the BFTM counter value. Offset: 0x008 Reset value: 0x0000_0000 Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW...
Page 310: Bftm Compare Value Register - Bftmcmpr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 BFTM Compare Value Register – BFTMCMPR The register specifies the BFTM compare value. Offset: 0x00C Reset value: 0xFFFF_FFFF Type/Reset 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW...
Page 311: Motor Control Timer (Mctm)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Motor Control Timer (MCTM) Introduction The Motor Control Timer consists of one 16-bit up/down-counter, four 16-bit Capture/Compare Registers (CCRs), one 16-bit Counter-Reload Register (CRR), one 8-bit Repetition Counter (REPR) and several control/status registers. It can be used for a variety of purposes which include general time measurement, input signal pulse width measurement, output waveform generation for signals such as single pulse generation or PWM generation, including dead time insertion.
Page 312: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Features ▄ 16-bit up/down auto-reload counter. ▄ 16-bit programmable prescaler that allows division the counter clock frequency by any factor between 1 and 65536. ▄ Up to 4 independent channels for: ●...
Page 313: Functional Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Functional Descriptions Counter Mode Up-Counting In this mode the counter counts continuously from 0 to the counter-reload value, which is defined in the CRR register, in a count-up direction. Once the counter reaches the counter-reload value, the Timer Module generates an overflow event and the counter restarts to count once again from 0.
Page 314: Figure 75. Down-Counting Example
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Down-Counting In this mode the counter counts continuously from the counter-reload value, which is defined in the CRR register, to 0 in a count-down direction. Once the counter reaches 0, the Timer module generates an underflow event and the counter restarts to count once again from the counter-reload value.
Page 315: Figure 76. Center-Aligned Counting Example
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Center-aligned Counting In the center-aligned counting mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The Timer Module generates an overflow event when the counter counts to the counter-reload value in the up-counting mode and generates an underflow event when the counter counts to 0 in the down-counting mode.
Page 316: Figure 77. Update Event 1 Dependent Repetition Mechanism Example
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Repetition Down-counter Operation The update event 1 is usually generated at each overflow or underflow event occurrence. However, when the repetition operation is active by assigning a non-zero value into the REPR register, the update event is only generated if the REPR counter has reached zero.
Page 317: Clock Controller
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Clock Controller The following describes the Timer Module clock controller which determines the internal prescaler counter clock source. ▄ Internal APB clock f CLKIN The default internal clock source is the APB clock f...
Page 318: Trigger Controller
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Trigger Controller The trigger controller is used to select the trigger source and setup the trigger level and edge trigger conditions. For the internal trigger input (ITIx), it can be selected by the Trigger Selection bits, TRSEL, in the TRCFR register.
Page 319: Slave Controller
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Slave Controller The MCTM can be synchronised with an internal/external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which are selected by the SMSEL field in the MDCFR register.
Page 320: Figure 82. Mctm In Pause Mode
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Pause Mode In the Pause Mode, the selected STI input signal level is used to control the counter start/stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level.
Page 321: Master Controller
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Master Controller The MCTMs and GPTMs can be linked together internally for timer synchronisation or chaining. When one MCTM is configured to be in the Master Mode, the MCTM Master Controller will generate a Master Trigger Output (MTO) signal which can reset, restart, stop the Slave counter or be a clock source of the Slave Counter.
Page 322: Channel Controller
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel Controller The MCTM has four independent channels which can be used as capture inputs or compare match outputs. Each capture input or compare match output channel is composed of a preload register and a shadow register. Data access of the APB bus is always implemented through the read/write preload register.
Page 323: Figure 87. Input Capture Mode
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Capture Counter Value Transferred to CHxCCR When the channel is used as a capture input, the counter value is captured into the Channel Capture/Compare Register (CHxCCR) when an effective input signal transition occurs. Once the capture event occurs, the CHxCCIF flag in the INTSR register is set accordingly.
Page 324: Figure 88. Pwm Pulse Width Measurement Example
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Pulse Width Measurement The input capture mode can be also used for pulse width measurement from signals on the MT_ CHx pins, TIx. The following example shows how to configure the MCTM when operated in the input capture mode to measure the high pulse width and the input period on the MT_CH0 pin using channel 0 and channel 1.
Page 325: Input Stage
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Input Stage The input stage consists of a digital filter, a channel polarity selection, edge detection and a channel prescaler. The channel 0 input signal TI0 can be chosen to come from the MT_CH0 signal or the Excusive-OR function of the MT_CH0, MT_CH1 and MT_CH2 signals.
Page 326: Figure 91. Ti0 Digital Filter Diagram With N = 2
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Digital Filter The digital filters are embedded in the input stage and clock controller block for the MT_CH0 ~ MT_CH3 pins. The digital filter in the MCTM is an N-event counter where N refers to how many valid transitions are necessary to output a filtered signal.
Page 327: Output Stage
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Output Stage The MCTM supports complementary outputs for channels 0, 1 and 2 with dead time insertion. The MCTM channel 3 output function is almost the same as that of GPTM channel 3 except for the break function.
Page 328: Table 35. Compare Match Output Setup
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel Output Reference Signal When the MCTM is used in the compare match output mode, the CHxOREF signal (Channel x Output Reference signal) is defined by the CHxOM bit setup. The CHxOREF signal has several types of output function which defines what happens to the output when the counter value matches the contents of the CHxCCR register.
Page 329: Figure 94. Toggle Mode Channel Output Reference Signal - Chxpre = 1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Counter Value CHxOM=0x03, CHxPRE=1 (Output toggle, preload enable) CHxCCR (New value 2) CHxCCR (New value 3) CHxCCR (New value 1) CHxCCR Time Update CHxCCR value CHxOREF UEV1 (Update Event 1) Figure 94. Toggle Mode Channel Output Reference Signal – CHxPRE = 1...
Page 330: Figure 96. Pwm Mode Channel Output Reference Signal And Counter In Down-Counting Mode
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Counter Value Counter Value CHxCCR CHxCCR CHxOM = 0x06 100% CHxOREF CHxOREF CHxCCIF CHxCCIF CHxOM = 0x07 CHxOREF CHxOREF Figure 96. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode...
Page 331: Figure 98. Dead-Time Insertion Performed For Complementary Outputs
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Dead Time Generator An 8-bit dead time generator function is included for channels 0~2. The dead time insertion is enabled by setting both the CHxE and CHxNE bits. The relationship between the CHxO and CHxNO signals with respect to the CHxOREF signal is as follows: ▄...
Page 332: Figure 99. Mctm Break Signal Bolck Diagram
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Break Function The MCTM includes break function and one input signals for MCTM break. The MT_BRK is default function and from external MT_BRK pin. The detail block diagram is shown as below figure. Output...
Page 333: Figure 101. Channel 3 Output With A Break Event Occurrence
Cortex ® -M0+ MCU HT32F52342/HT32F52352 When using the break function, the channel output enable signals and output levels are changed depending on several control bits which include the CHMOE, CHOSSI, CHOSSR, CHxOIS and CHxOISN bits. Once a break event occurs, the output enable bit CHMOE will be cleared asynchronously.
Page 334: Figure 102. Channel 0 ~ 2 Complementary Outputs With A Break Event Occurrence
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 The accompanying diagram shows that the complementary output states when a break event occurs where the complementary outputs are enabled by setting both the CHxE and CHxNE bits to 1. Break event CHMOE...
Page 335: Figure 104. Hardware Protection When Both Chxo And Chxno Are In Active Condition
Cortex ® -M0+ MCU HT32F52342/HT32F52352 The CHxO and CHxNO complementary outputs should not be set to an active level at the same time. The hardware will protect the MCTM circuitry to force only one channel output to be in the active state.
Page 336: Table 36. Output Control Bits For Complementary Output With A Break Event Occurrence
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Table 36. Output Control Bits for Complementary Output with a Break Event Occurrence Control bit Output status MT_CHxN Pin output CHMOE CHOSSI CHOSSR CHxE CHxNE MT_CHx Pin output state state Output disabled - floating...
Page 337: Update Management
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Update Management The update events are categorised into two different types which are the update event 1, UEV1, and update event 2, UEV2. The update event 1 is used to update the CRR, the PSCR, the CHxACR and the CHxCCR values from the actual registers to the corresponding shadow registers.
Page 338: Figure 106. Chxe, Chxne And Chxom Updated By Update Event 2
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Update Event 2 The CHxE, CHxNE, CHxOM control bits for the complementary outputs can be preloaded by setting the COMPRE bit in the CTR register. Here the shadow bits of the CHxE, CHxNE, and CHxOM bits will be updated when an update event 2 occurs.
Page 339: Single Pulse Mode
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Single Pulse Mode Once the timer is set to operate in the single pulse mode, it is not necessary to set the timer enable bit TME in the CTR register to 1 to enable the counter. The trigger to generate a pulse can be sourced from the STI signal rising edge or by setting the TME bit to 1 using software.
Page 340: Figure 109. Immediate Active Mode Minimum Delay
Cortex ® -M0+ MCU HT32F52342/HT32F52352 In the Single Pulse mode, the STI active edge which sets the TME bit to 1 will enable the counter. However, there exist several clock delays to perform the comparison result between the counter value and the CHxCCR value. In order to reduce the delay to a minimum value, users can set the CHxIMAE bit in each CHxOCFR register.
Page 341: Asymmetric Pwm Mode
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Asymmetric PWM Mode Asymmetric PWM mode allows two center-aligned PWM signals to be genetated with a programmable phase shift. While the PWM frequency is determined by the value of the MCTMx_ CRR register, the duty cycle and the phase-shift are determined by the CHxCCR and CHxACR register.
Page 342: Timer Interconnection
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Interconnection The timers can be internally connected together for timer chaining or synchronization. This can be implemented by configuring one timer to operate in the master mode while configuring another timer to be in the slave mode. The following figures present several examples of trigger selection for the master and slave modes.
Page 343: Figure 112. Triggering Gptm With Mctm Update Event 1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Using one timer to trigger another timer to start counting ▄ Configure MCTM to operate in the master mode and to send its Update Event UEV as the trigger output (MMSEL = 0x02).
Page 344: Figure 113. Trigger Mctm And Gptm With The Mctm Ch0 Input
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Starting two timers synchronously in response to an external trigger ▄ Configure MCTM to operate in the master mode to send its enable signal as a trigger output (MMSEL = 0x01). ▄...
Page 345: Figure 114. Ch1Xor Input As Hall Sensor Interface
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Using one timer as a hall sensor interface to trigger another timer with update event 2 GPTM: ▄ Configure channel 0 to choose an input XOR function (TI0SRC = 1) ▄ Configure channel 0 to be in the input capture mode and TRCED as capture source (CH0CCS= 0x03) and Enable channel 0 (CH0E=1) ▄...
Page 346: Trigger Adc Start
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Trigger ADC Start To interconnect to the Analog-to-Digital Converter, the MCTM can output the MTO signal or the channel compare match output signal CHxOREF (x = 0 ~ 3) to be used as an Analog-to-Digital Converter input trigger signal.
Page 347: Pdma Request
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 PDMA Request The MCTM has a PDMA data transfer interface. There are certain events which can generate PDMA requests if the corresponding enable control bits are set to 1 to enable the PDMA access.
Page 348: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Map The following table shows the MCTM registers and reset values. Table 38. MCTM Register Map Register Offset Description Reset Value CNTCFR 0x000 Timer Counter Configuration Register 0x0000_0000 MDCFR 0x004 Timer Mode Configuration Register...
Page 349: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Descriptions Timer Counter Configuration Register – CNTCFR This register specifies the MCTM counter configuration. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CMSEL Type/Reset 0 RW Reserved CKDIV Type/Reset 0 RW...
Page 350 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions UGDIS Update event 1 interrupt generation disable control 0: Any of the following events will generate an update PDMA request or interrupt - Counter overflow / underflow - Setting the UEV1G bit...
Page 351: Timer Mode Configuration Register - Mdcfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Mode Configuration Register – MDCFR This register specifies the MCTM master and slave mode selection and single pulse mode. Offset: 0x004 Reset value: 0x0000_0000 Reserved SPMSET Type/Reset Reserved MMSEL Type/Reset 0 RW...
Page 352 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [18:16] MMSEL Master Mode Selection Master mode selection is used to select the MTO signal source which is used to synchronise the other slave timer. MMSEL [2:0] Mode Descriptions...
Page 353 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [10:8] SMSEL Slave Mode Selection SMSEL [2:0] Mode Descriptions Disable mode The prescaler is clocked directly by the internal clock. Reserved Reserved Reserved The counter value restarts from 0 or the CRR shadow...
Page 354: Timer Trigger Configuration Register - Trcfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Trigger Configuration Register – TRCFR This register specifies the trigger source selection of MCTM. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved TRSEL Type/Reset 0 RW 0 RW...
Page 355: Timer Counter Register - Ctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Counter Register – CTR This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE), Capture/compare control bit and Channel PDMA selection bit (CHCCDS). Offset: 0x010 Reset value: 0x0000_0000...
Page 356: Channel 0 Input Configuration Register - Ch0Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 0 Input Configuration Register – CH0ICFR This register specifies the channel 0 input mode configuration. Offset: 0x020 Reset value: 0x0000_0000 TI0SRC Reserved Type/Reset Reserved CH0PSC CH0CCS Type/Reset 0 RW 0 RW...
Page 357 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [3:0] TI0F Channel 0 Input Source TI0 Filter Setting These bits define the frequency divided ratio used to sample the TI0 signal. The Digital filter in the MCTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
Page 358: Channel 1 Input Configuration Register - Ch1Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 1 Input Configuration Register – CH1ICFR This register specifies the channel 1 input mode configuration. Offset: 0x024 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CH1PSC CH1CCS Type/Reset 0 RW 0 RW 0 RW...
Page 359 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [3:0] TI1F Channel 1 Input Source TI1 Filter Setting These bits define the frequency divide ratio used to sample the TI1 signal. The Digital filter in the MCTM is an N-event counter where N is defined as how many...
Page 360: Channel 2 Input Configuration Register - Ch2Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 2 Input Configuration Register – CH2ICFR This register specifies the channel 2 input mode configuration. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CH2PSC CH2CCS Type/Reset 0 RW 0 RW 0 RW...
Page 361 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [3:0] TI2F Channel 2 Input Source TI2 Filter Setting These bits define the frequency divide ratio used to sample the TI2 signal. The Digital filter in the MCTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
Page 362: Channel 3 Input Configuration Register - Ch3Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 3 Input Configuration Register – CH3ICFR This register specifies the channel 3 input mode configuration. Offset: 0x02C Reset value: 0x0000_0000 Reserved Type/Reset Reserved CH3PSC CH3CCS Type/Reset 0 RW 0 RW 0 RW...
Page 363 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [3:0] TI3F Channel 3 Input Source TI3 Filter Setting These bits define the frequency divide ratio used to sample the TI3 signal. The digital filter in the GPTM is an N-event counter where N is defined as how many...
Page 364: Channel 0 Output Configuration Register - Ch0Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 0 Output Configuration Register – CH0OCFR This register specifies the channel 0 output mode configuration. Offset: 0x040 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH0OM[3] Type/Reset Reserved CH0IMAE CH0PRE Reserved...
Page 365 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [8][2:0] CH0OM[3:0] Channel 0 Output Mode Setting These bits define the functional types of the output reference signal CH0OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
Page 366: Channel 1 Output Configuration Register - Ch1Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 1 Output Configuration Register – CH1OCFR This register specifies the channel 1 output mode configuration. Offset: 0x044 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH1OM[3] Type/Reset Reserved CH1IMAE CH1PRE Reserved...
Page 367 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [8][2:0] CH1OM[3:0] Channel 1 Output Mode Setting These bits define the functional types of the output reference signal CH1OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
Page 368: Channel 2 Output Configuration Register - Ch2Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 2 Output Configuration Register – CH2OCFR This register specifies the channel 2 output mode configuration. Offset: 0x048 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH2OM[3] Type/Reset Reserved CH2IMAE CH2PRE Reserved...
Page 369 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [8][2:0] CH2OM[3:0] Channel 2 Output Mode Setting These bits define the functional types of the output reference signal CH2OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
Page 370: Channel 3 Output Configuration Register - Ch3Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 3 Output Configuration Register – CH3OCFR This register specifies the channel 3 output mode configuration. Offset: 0x04C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH3OM[3] Type/Reset Reserved CH3IMAE CH3PRE Reserved...
Page 371 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [8][2:0] CH3OM[3:0] Channel 3 Output Mode Setting These bits define the functional types of the output reference signal CH3OREF 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
Page 372: Channel Control Register - Chctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel Control Register – CHCTR This register contains the channel capture input or compare output function enable control bits. Offset: 0x050 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3E...
Page 373 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions CH1NE Channel 1 Capture/Compare Complementary Enable 0: Off – Channel 1 complementary output CH1NO is not active. The CH1NO level is then determined by the condition of the CHMOE, CHOSSI, CHOSSR, CH1OIS, CH1OISN and CH1E bits.
Page 374: Channel Polarity Configuration Register - Chpolr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel Polarity Configuration Register – CHPOLR This register contains the channel capture input or compare output polarity control. Offset: 0x054 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3P CH2NP...
Page 375 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions CH0P Channel 0 Capture/Compare Polarity - When Channel 0 is configured as an input 0: capture event occurs on a Channel 0 rising edge 1: capture event occurs on a Channel 0 falling edge...
Page 376: Channel Break Configuration Register - Chbrkcfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel Break Configuration Register – CHBRKCFR This register specifies the channel output idle state when using the break function. Offset: 0x06C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3OIS...
Page 377: Channel Break Control Register - Chbrkctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel Break Control Register – CHBRKCTR This register specifies the channel break control bits. Offset: 0x070 Reset value: 0x0000_0000 CHDTG Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW...
Page 378 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [11:8] Break Input Filter Setting These bits define the frequency ratio used to sample the MT_BRK signal. The digital filter in the MCTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
Page 379: Timer Pdma/Interrupt Control Register - Dictr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer PDMA/Interrupt Control Register – DICTR This register contains the timer PDAM and interrupt enable control bits. Offset: 0x074 Reset value: 0x0000_0000 Reserved TEVDE UEV2DE UEV1DE Type/Reset 0 RW 0 RW Reserved...
Page 380 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions UEV1IE Update event 1 Interrupt Enable 0: Update event 1 interrupt is disabled 1: Update event 1 interrupt is enabled CH3CCIE Channel 3 Capture/Compare Interrupt Enable 0: Channel 3 interrupt is disabled...
Page 381: Timer Event Generator Register - Evgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Event Generator Register – EVGR This register contains the software event generation bits. Offset: 0x078 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved BRKG TEVG UEV2G UEV1G Type/Reset 0 WO 0 WO...
Page 382 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions CH3CCG Channel 3 Capture/Compare Generation A Channel 3 capture/compare event can be generated by setting this bit. It is cleared by hardware automatically. 0: No action 1: Capture/compare event is generated on channel 3 If Channel 3 is configured as an input, the counter value is captured into the CH3CCR register and then the CH3CCIF bit is set.
Page 383: Timer Interrupt Status Register - Intsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Interrupt Status Register – INTSR This register stores the timer interrupt status. Offset: 0x07C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved BRKIF TEVIF UEV2IF UEV1IF Type/Reset 0 W0C 0 W0C...
Page 384 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions CH2OCF Channel 2 Over-capture Flag This flag is set by hardware and cleared by software. 0: No over-capture event is detected 1: Capture event occurs again when the CH2CCIF bit is already set and it is not cleared yet by software.
Page 385 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions CH0CCIF Channel 0 Capture/Compare Interrupt Flag - Channel 0 is configured as an output 0: No match event occurs 1: The contents of the counter CNTR have matched the content of the CH0CCR...
Page 386: Timer Counter Register - Cntr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Counter Register – CNTR This register stores the timer counter value. Offset: 0x080 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CNTV Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...
Page 387: Timer Prescaler Register - Pscr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Prescaler Register – PSCR This register specifies the timer prescaler value to generate the counter clock. Offset: 0x084 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PSCV Type/Reset 0 RW 0 RW...
Page 388: Timer Counter Reload Register - Crr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Counter Reload Register – CRR This register specifies the timer counter reload value. Offset: 0x088 Reset value: 0x0000_FFFF Reserved Type/Reset Reserved Type/Reset Type/Reset 1 RW 1 RW 1 RW 1 RW...
Page 389: Timer Repetition Register - Repr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Repetition Register – REPR This register specifies the timer repetition counter value. Offset: 0x08C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset REPV Type/Reset 0 RW 0 RW 0 RW...
Page 390: Channel 0 Capture/Compare Register - Ch0Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 0 Capture/Compare Register – CH0CCR This register specifies the timer channel 0 capture/compare value. Offset: 0x090 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH0CCV Type/Reset 0 RW 0 RW 0 RW...
Page 391: Channel 1 Capture/Compare Register - Ch1Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 1 Capture/Compare Register – CH1CCR This register specifies the timer channel 1 capture/compare value. Offset: 0x094 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH1CCV Type/Reset 0 RW 0 RW 0 RW...
Page 392: Channel 2 Capture/Compare Register - Ch2Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 2 Capture/Compare Register – CH2CCR This register specifies the timer channel 2 capture/compare value. Offset: 0x098 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2CCV Type/Reset 0 RW 0 RW 0 RW...
Page 393: Channel 3 Capture/Compare Register - Ch3Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 3 Capture/Compare Register – CH3CCR This register specifies the timer channel 3 capture/compare value. Offset: 0x09C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH3CCV Type/Reset 0 RW 0 RW 0 RW...
Page 394: Channel 0 Asymmetric Compare Register - Ch0Acr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 0 Asymmetric Compare Register – CH0ACR This register specifies the timer channel 0 asymmetric compare value. Offset: 0x0A0 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH0ACV Type/Reset 0 RW 0 RW...
Page 395: Channel 1 Asymmetric Compare Register - Ch1Acr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 1 Asymmetric Compare Register – CH1ACR This register specifies the timer channel 1 asymmetric compare value. Offset: 0x0A4 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH1ACV Type/Reset 0 RW 0 RW...
Page 396: Channel 2 Asymmetric Compare Register - Ch2Acr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 2 Asymmetric Compare Register – CH2ACR This register specifies the timer channel 2 asymmetric compare value. Offset: 0x0A8 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2ACV Type/Reset 0 RW 0 RW...
Page 397: Channel 3 Asymmetric Compare Register - Ch3Acr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel 3 Asymmetric Compare Register – CH3ACR This register specifies the timer channel 3 asymmetric compare value. Offset: 0x0AC Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH3ACV Type/Reset 0 RW 0 RW...
Page 398: Single-Channel Timer (Sctm)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Single-Channel Timer (SCTM) Introduction The Single-Channel Timer consists of one 16-bit up-counter, one 16-bit Capture/Compare Register (CCR), one 16-bit Counter-Reload Register (CRR) and several control/status registers. It can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as single pulse generation or PWM output.
Page 399: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Features ▄ 16-bit auto-reload up counter ▄ 16-bit programmable prescaler that allows division of the counter clock frequency by any factor between 1 and 65536 ▄ Single channel for: ● Input Capture function ●...
Page 400: Clock Controller
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Clock Controller The following describes the Timer Module clock controller which determines the clock source of the internal prescaler counter. ▄ Internal APB clock f CLKIN The default internal clock source is the APB clock f...
Page 401: Trigger Controller
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Trigger Controller The trigger controller is used to select the trigger source and setup the trigger level or edge trigger condition. For the internal trigger input, it can be selected by the Trigger Selection bits TRSEL in the TRCFR register.
Page 402: Slave Controller
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Slave Controller The SCTM can be synchronized with an external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which is selected by the SMSEL field in the MDCFR register.
Page 403: Figure 122. Sctm In Pause Mode
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Pause Mode In the Pause Mode, the selected STI input signal level is used to control the counter start/stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level, here the counter will maintain its present value and will not be reset.
Page 404: Channel Controller
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel Controller The SCTM channel can be used as the capture input or compare match output. The capture input or compare match output channel is composed of a preload register and a shadow register. Data access of the APB bus is always through the read/write preload register.
Page 405: Figure 125. Input Capture Mode
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Capture Counter Value Transferred to CHCCR When the channel is used as a capture input, the counter value is captured into the Channel Capture/Compare Register (CHCCR) when an effective input signal transition occurs. Once the capture event occurs, the CHCCIF flag in the INTSR register is set accordingly.
Page 406: Input Stage
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Input Stage The input stage consists of a digital filter, a channel polarity selection, edge detection and a channel prescaler. The channel input signal (TI) is sampled by a digital filter to generate a filtered input signal TIFP.
Page 407: Output Stage
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Output Stage The SCTM output has function for compare match, single pulse or PWM output. The channel output SCTM_CHO is controlled by the CHOM, CHP and CHE bits in the corresponding CHOCFR, CHPOLR and CHCTR registers.
Page 408: Figure 129. Toggle Mode Channel Output Reference Signal (Chpre = 0)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Counter Value CHOM=0x03, CHPRE=0 (Output toggle, preload disable) CHCCR (New value 2) CHCCR (New value 3) CHCCR (New value 1) CHCCR Time Update CHCCR value CHOREF (Update Event) Figure 129. Toggle Mode Channel Output Reference Signal (CHPRE = 0)
Page 409: Update Management
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Counter Value Counter Value Counter Value CHCCR CHCCR CHCCR = 0x00 CHOM = 0x06 100% CHOREF CHOREF CHOREF CHCCIF CHCCIF CHCCIF CHOM = 0x07 CHOREF Figure 131. PWM Mode Channel Output Reference Signal...
Page 410: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Update Event Management Counter Overflow / Underflow UEVG UEV (Update PSCR, CRR, CHCCR Shadow Registers) Slave Restart mode UEVDIS Update Event Interrupt Management Counter Overflow / Underflow UEV interrupt UEVG UEVDIS Slave Restart mode UGDIS Figure 132.
Page 411: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Descriptions Timer Counter Configuration Register – CNTCFR This register specifies the SCTM counter configuration. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CKDIV Type/Reset 0 RW Reserved UGDIS UEVDIS...
Page 412: Timer Mode Configuration Register - Mdcfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Mode Configuration Register – MDCFR This register specifies the SCTM slave mode selection. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved SMSEL Type/Reset 0 RW 0 RW Reserved Type/Reset...
Page 413: Timer Trigger Configuration Register - Trcfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Trigger Configuration Register – TRCFR This register specifies the trigger source selection of SCTM. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved TRSEL Type/Reset 0 RW 0 RW...
Page 414: Timer Counter Register - Ctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Counter Register – CTR This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE). Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CRBE Type/Reset...
Page 415: Channel Input Configuration Register - Chicfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel Input Configuration Register – CHICFR This register specifies the channel input mode configuration. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CHPSC CHCCS Type/Reset 0 RW 0 RW 0 RW Reserved...
Page 416 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [3:0] Channel Input Source TI Filter Setting These bits define the frequency divided ratio used to sample the TI signal. The Digital filter in the SCTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
Page 417: Channel Output Configuration Register - Chocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel Output Configuration Register – CHOCFR This register specifies the channel output mode configuration. Offset: 0x040 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CHPRE Reserved CHOM[2:0] Type/Reset 0 RW...
Page 418: Channel Control Register - Chctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel Control Register – CHCTR This register contains the channel capture input or compare output function enable control bits. Offset: 0x050 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset...
Page 419: Channel Polarity Configuration Register - Chpolr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel Polarity Configuration Register – CHPOLR This register contains the channel capture input or compare output polarity control. Offset: 0x054 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Bits...
Page 420: Timer Interrupt Control Register - Dictr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Interrupt Control Register – DICTR This register contains the timer interrupt enable control bits. Offset: 0x074 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVIE Reserved UEVIE Type/Reset Reserved CHCCIE Type/Reset...
Page 421: Timer Event Generator Register - Evgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Event Generator Register – EVGR This register contains the software event generation bits. Offset: 0x078 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVG Reserved UEVG Type/Reset Reserved CHCCG Type/Reset Bits...
Page 422: Timer Interrupt Status Register - Intsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Interrupt Status Register – INTSR This register stores the timer interrupt status. Offset: 0x07C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVIF Reserved UEVIF Type/Reset Reserved CHOCF Reserved CHCCIF Type/Reset...
Page 423: Timer Counter Register - Cntr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Counter Register – CNTR This register stores the timer counter value. Offset: 0x080 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CNTV Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...
Page 424: Timer Prescaler Register - Pscr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Prescaler Register – PSCR This register specifies the timer prescaler value to generate the counter clock. Offset: 0x084 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PSCV Type/Reset 0 RW 0 RW...
Page 425: Timer Counter Reload Register - Crr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Timer Counter Reload Register – CRR This register specifies the timer counter reload value. Offset: 0x088 Reset value: 0x0000_FFFF Reserved Type/Reset Reserved Type/Reset Type/Reset 1 RW 1 RW 1 RW 1 RW...
Page 426: Channel Capture/Compare Register - Chccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel Capture/Compare Register – CHCCR This register specifies the timer channel capture/compare value. Offset: 0x090 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CHCCV Type/Reset 0 RW 0 RW 0 RW 0 RW...
Page 427: Real Time Clock (Rtc)
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Real Time Clock (RTC) Introduction The Real Time Clock, RTC, circuitry includes the APB interface, a 32-bit up-counter, a control register, a prescalmer, a compare register and a status register. Most of the RTC circuits are located in the Backup Domain, as shown shaded in the accompanying figure, except for the APB interface.
Page 428: Functional Descriptions
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Functional Descriptions RTC Related Register Reset The RTC registers can only be reset by either a Backup Domain power on reset, PORB, or by a Backup Domain software reset by setting the BAKRST bit in the BAKCR register. Other reset events have no effect to clear the RTC registers.
Page 429: Rtc Counter Operation
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 RTC Counter Operation The RTC provides a 32-bit up-counter which increments at the falling edge of the CK_SECOND clock and whose value can be read from the RTCCNT register asynchronously via the APB bus.
Page 430: Rtcout Output Pin Configuration
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 RTCOUT Output Pin Configuration The following table shows RTCOUT output format according to the mode, polarity, and event selection setting. Table 43. RTCOUT Output Mode and Active Level Setting ROWM ROES RTCOUT Output Waveform...
Page 431: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Map The following table shows the RTC registers and reset values. Note all the registers in this unit are located at the V backup power domain. Table 44. RTC Register Map...
Page 432: Rtc Compare Register - Rtccmp
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 RTC Compare Register – RTCCMP This register defines a specific value to be compared with the RTC counter value. Offset: 0x004 Reset value: 0x0000_0000 (Reset by Backup Domain reset only) RTCCMPV Type/Reset...
Page 433: Rtc Control Register - Rtccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 RTC Control Register – RTCCR This register specifies a range of RTC circuitry control bits. Offset: 0x008 Reset value: 0x0000_0F04 (Reset by Backup Domain reset only) Reserved Type/Reset Reserved ROLF ROAP ROWM...
Page 434 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [11:8] RPRE RTC Clock Prescaler Select CK_SECOND = CK_RTC / 2 RPRE 0000: CK_SECOND = CK_RTC / 2 0001: CK_SECOND = CK_RTC / 2 0010: CK_SECOND = CK_RTC / 2 …...
Page 435: Rtc Status Register - Rtcsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 RTC Status Register – RTCSR This register stores the counter flags. Offset: 0x00C Reset value: 0x0000_0000 (Reset by Backup Domain reset and RTCEN bit change from 1 to 0) Reserved Type/Reset Reserved...
Page 436: Rtc Interrupt And Wakeup Enable Register - Rtciwen
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 RTC Interrupt and Wakeup Enable Register – RTCIWEN This register contains the interrupt and wakeup enable bits. Offset: 0x010 Reset value: 0x0000_0000 (Reset by Backup Domain reset only) Reserved Type/Reset Reserved Type/Reset...
Page 437: Watchdog Timer (Wdt)
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Watchdog Timer (WDT) Introduction The Watchdog timer is a hardware timing circuitry that can be used to detect a system lock-up due to software trapped in a deadlock. The Watchdog timer can be operated in a reset mode. The Watchdog timer will generate a reset when the counter counts down to a zero value.
Page 438: Functional Description
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Functional Description The Watchdog timer is formed from a 12-bit count-down counter and a fixed 3-bit prescaler. The largest time-out period is 16 seconds, using the LSE or LSI clock and a 1/128 maximum prescaler value.
Page 439: Figure 135. Watchdog Timer Behavior
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 The Watchdog timer should be used in the following manners: ▄ Set the Watchdog timer reload value (WDTV) and reset in the WDTMR0 register. ▄ Set the Watchdog timer delta value (WDTD) and prescaler in the WDTMR1 register.
Page 440: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Map The following table shows the Watchdog Timer registers and reset values. Table 45. Watchdog Timer Register Map Register Offset Description Reset Value WDTCR 0x000 Watchdog Timer Control Register 0x0000_0000 WDTMR0...
Page 441: Watchdog Timer Mode Register 0 - Wdtmr0
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Watchdog Timer Mode Register 0 – WDTMR0 This register specifies the Watchdog timer counter reload value and reset enable control. Offset: 0x004 Reset value: 0x0000_0FFF Reserved Type/Reset Reserved WDTEN Type/Reset WDTSHLT WDTRSTEN Reserved...
Page 442: Watchdog Timer Mode Register 1 - Wdtmr1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Watchdog Timer Mode Register 1 – WDTMR1 This register specifies the Watchdog delta value and the prescaler selection. Offset: 0x008 Reset value: 0x0000_7FFF Reserved Type/Reset Reserved Type/Reset Reserved WPSC WDTD Type/Reset 1 RW...
Page 443: Watchdog Timer Status Register - Wdtsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Watchdog Timer Status Register – WDTSR This register specifies the Watchdog timer status. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved WDTERR WDTUF Type/Reset 0 WC Bits Field...
Page 444: Watchdog Timer Protection Register - Wdtpr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Watchdog Timer Protection Register – WDTPR This register specifies the Watchdog timer protect key configuration. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PROTECT Type/Reset 0 RW 0 RW 0 RW...
Page 445: Watchdog Timer Clock Selection Register - Wdtcsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Watchdog Timer Clock Selection Register – WDTCSR This register specifies the Watchdog timer clock source selection and lock configuration. Offset: 0x018 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved WDTLOCK...
Page 446: Inter-Integrated Circuit (I C)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Inter-Integrated Circuit (I Introduction The I C Module is an internal circuit allowing communication with an external I C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line, SDA, and a serial clock line, SCL.
Page 447: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Features ▄ Two–wire I C serial interface ● Serial data line (SDA) and serial clock (SCL) ▄ Multiple speed modes ● Standard mode – 100 kHz ● Fast mode – 400 kHz ●...
Page 448: Data Validity
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 STOP Condition START Condition Figure 137. START and STOP Condition Data Validity The data on the SDA line must be stable during the high period of the SCL clock. The SDA data state can only be changed when the clock signal on the SCL line is in a low state.
Page 449: Addressing Format
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Addressing Format The I C interface starts to transfer data after the master device has sent the address to confirm the targeted slave device. The address frame is sent just after the START signal by master device. The addressing mode selection bit named ADRM in the I2CCR register should be defined to choose either the 7-bit or 10-bit addressing mode.
Page 450: Figure 140. 10-Bit Addressing Write Transmit Mode
Cortex ® -M0+ MCU HT32F52342/HT32F52352 10-bit Address Format In order to prevent address clashes, due to the limited range of the 7-bit addresses, a new 10-bit address scheme has been introduced. This enhancement can be mixed with the 7-bit addressing mode which increases the available address range about ten times.
Page 451: Data Transfer And Acknowledge
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Data Transfer and Acknowledge Once the slave device address has been matched, the data can be transmitted to or received from the slave device according to the transfer direction specified by the R/W bit. Each byte is followed...
Page 452: Clock Synchronization
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Clock Synchronization Only one master device can generate the SCL clock under normal operation. However when there is more than one master trying to generate the SCL clock, the clock should be synchronized so that the data output can be compared.
Page 453: General Call Addressing
Cortex ® -M0+ MCU HT32F52342/HT32F52352 General Call Addressing The general call addressing function can be used to address all the devices connected to the I bus. The master device can activate the general call function by writing a value “00” into the TAR and setting the RWD bit to 0 in the I2CTAR register on the addressing frame.
Page 454: Figure 145. Master Transmitter Timing Diagram
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Master Transmitter Mode Start condition Users write the target slave device address and communication direction into the I2CTAR register after setting the I2CEN bit in the I2CCR register. The STA flag in the I2CSR register is set by hardware after a start condition occurs.
Page 455 ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Master Receiver Mode Start condition The target slave device address and communication direction must be written into the I2CTAR register. The STA flag in the I2CSR register is set by hardware after a start condition occurs. In order to send the following address frame, the STA flag must be cleared to 0 if it has been set to 1.The...
Page 456: Figure 146. Master Receiver Timing Diagram
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Close / Continue Transmission The master device needs to reset the AA bit in the I2CCR register to send a NACK signal to the slave device before the last data byte transfer has been completed. After the last data byte has been received from the slave device, the master device will hold the SCL line at a logic low state following after a NACK signal sent by the master device to the slave device.
Page 457: Figure 147. Slave Transmitter Timing Diagram
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Slave Transmitter Mode Address Frame In the 7-bit addressing mode, the ADRS bit in the I2CSR register is set after the slave device receives the calling address which matches with the slave device address. In the 10-bit addressing mode, the ADRS bit is set when the first header byte is matched and the second address byte is matched respectively.
Page 458: Figure 148. Slave Receiver Timing Diagram
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Slave Receiver Mode Address Frame The ADRS bit in the I2CSR register is set after the slave device receives the calling address which matches with the slave device address. After the ADRS bit has been set to 1, it must be cleared to 0 to continue the data transfer process.
Page 459: Conditions Of Holding Scl Line
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Conditions of Holding SCL Line The following conditions will cause the SCL line to be held at a logic low state by hardware resulting in all the I C transfers being stopped. Data transfer will be continued after the creating conditions are eliminated.
Page 460: I 2 C Timeout Function
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 C Timeout Function In order to reduce the occurrence of I C lockup problem due to the reception of erroneous clock source, a timeout function is provided. If the I C bus clock source is not received for a certain timeout period, then a corresponding I C timeout flag will be asserted.
Page 461: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Map The following table shows the I C registers and reset values. Table 47. I C Register Map Register Offset Description Reset Value I2CCR 0x000 C Control Register 0x0000_2000 I2CIER 0x004...
Page 462: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Descriptions C Control Register – I2CCR This register specifies the corresponding I C function enable control. Offset: 0x000 (0) Reset value: 0x0000_2000 Reserved Type/Reset Reserved Type/Reset SEQFILTER COMBFILTEREn ENTOUT Reserved DMANACK RXDMAE TXDMAE...
Page 463 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions RXDMAE DMA Mode RX Request Enable Control 0: RX DMA request disabled 1: RX DMA request enabled If the data register is not empty in the receiver mode and the RXDMAE bit is...
Page 464: I 2 C Interrupt Enable Register - I2Cier
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 C Interrupt Enable Register – I2CIER This register specifies the corresponding I C interrupt enable bits. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved RXBFIE TXDEIE RXDNEIE Type/Reset 0 RW 0 RW...
Page 465 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions ARBLOSIE Arbitration Loss Interrupt Enable Bit in the I C multi-master mode 0: Interrupt disabled 1: Interrupt enabled When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by hardware.
Page 466: I 2 C Address Register - I2Caddr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 C Address Register – I2CADDR This register specifies the I C device address. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved ADDR Type/Reset 0 RW ADDR Type/Reset 0 RW 0 RW...
Page 467: I 2 C Status Register - I2Csr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 C Status Register – I2CSR This register contains the I C operation status. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved TXNRX MASTER BUSBUSY RXBF TXDE RXDNE Type/Reset 0 RO 0 RO...
Page 468 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [17] TXDE Data Register Empty Using in Transmitter Mode 0: Data register I2CDR not empty 1: Data register I2CDR empty This bit is set when the I2CDR register is empty in the Transmitter mode. Note that the TXDE bit will be set after the address frame is being transmitted to inform that the data to be transmitted should be loaded into the I2CDR register.
Page 469 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions ADRS Address Transmit (master mode) / Address Receive (slave mode) Flag Address Sent in Master Mode 0: Address frame has not been transmitted 1: Address frame has been transmitted For the 7-bit addressing mode, this bit is set after the master device receives the address frame acknowledge bit sent from the slave device.
Page 470: C Scl High Period Generation Register - I2Cshpgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 C SCL High Period Generation Register – I2CSHPGR This register specifies the I C SCL clock high period interval. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset SHPG Type/Reset 0 RW...
Page 471: I 2 C Scl Low Period Generation Register - I2Cslpgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 C SCL Low Period Generation Register – I2CSLPGR This register specifies the I C SCL clock low period interval. Offset: 0x014 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset SLPG Type/Reset 0 RW...
Page 472: C Data Register - I2Cdr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 C Data Register – I2CDR This register specifies the data to be transmitted or received by the I C module. Offset: 0x018 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset DATA...
Page 473: I 2 C Target Register - I2Ctar
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 C Target Register – I2CTAR This register specifies the target device address to be communicated. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset 0 RW 0 RW Type/Reset 0 RW...
Page 474: I 2 C Address Mask Register - I2Caddmr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 C Address Mask Register – I2CADDMR This register specifies which bit of the I C address is masked and not compared with corresponding bit of the received address frame. Offset: 0x020 Reset value: 0x0000_0000...
Page 475: I 2 C Address Snoop Register - I2Caddsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 C Address Snoop Register – I2CADDSR This register is used to indicate the address frame value appeared on the I C bus. Offset: 0x024 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved...
Page 476: I 2 C Timeout Register - I2Ctout
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 C Timeout Register – I2CTOUT This register specifies the I C Timeout counter preload value and clock prescaler ratio. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset 0 RW 0 RW...
Page 477: Serial Peripheral Interface (Spi)
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Serial Peripheral Interface (SPI) Introduction The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive functions in both master or slave mode. The SPI interface uses 4 pins, among which are serial data input and output lines MISO and MOSI, the clock line SCK, and the slave select line SEL.
Page 478: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Features ▄ Master or slave mode ▄ Master mode speed up to f PCLK ▄ Slave mode speed up to f PCLK ▄ Programmable data frame length up to 16 bits ▄...
Page 479: Spi Serial Frame Format
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 SPI Serial Frame Format The SPI interface format is base on the Clock Polarity, CPOL, and the Clock Phase, CPHA, configurations. ▄ Clock Polarity Bit – CPOL When the Clock Polarity bit is cleared to 0, the SCK line idle state is LOW. When the Clock Polarity bit is set to 1, the SCK line idle state is HIGH.
Page 480: Figure 152. Spi Continuous Data Transfer Timing Diagram - Cpol = 0, Cpha = 0
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Figure 152 shows the continuous data transfer timing diagram of this format. Note that the SEL signal must change to an inactive level between each data frame. SEL (SELAP=0) SEL (SELAP=1) MOSI/MISO...
Page 481: Figure 154. Spi Continuous Transfer Timing Diagram - Cpol = 0, Cpha = 1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Figure 154 shows the continuous data transfer diagram timing. Note that the SEL signal must remain active until the last data transfer has completed. SEL (SELAP=0) SEL (SELAP=1) MOSI/MISO Data1 Data2 Figure 154. SPI Continuous Transfer Timing Diagram – CPOL = 0, CPHA = 1...
Page 482: Figure 156. Spi Continuous Transfer Timing Diagram - Cpol = 1, Cpha = 0
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Figure 156 shows the continuous data transfer timing of this format. Note that the SEL signal must change to an inactive level between each data frame. SEL (SELAP=0) SEL (SELAP=1) ½ SCK ½...
Page 483: Status Flags
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Status Flags TX Buffer Empty – TXBE This TXBE flag is set when the TX buffer is empty in the non-FIFO mode or when the TX FIFO data length is equal to or less than the TX FIFO threshold level as defined by the TXFTLS field in the SPIFCR register in the FIFO mode.
Page 484: Table 50. Spi Mode Fault Trigger Conditions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 MOSI MOSI Master Master MISO MISO I/O 0 I/O 0 I/O 1 I/O 1 I/O 2 I/O 2 MOSI Slave MISO MOSI Slave MISO Figure 159. SPI Multi-Master Slave Environment Table 50. SPI Mode Fault Trigger Conditions...
Page 485 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Write Collision – WC The following conditions will assert the Write Collision Flag. ▄ The FIFOEN bit in the SPIFCR register is cleared The write collision flag is asserted when new data is written into the SPIDR register while both the TX buffer and the shift register are already full.
Page 486: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Map The following table shows the SPI registers and their reset values. Table 52. SPI Register Map Register Offset Description Reset Value SPICR0 0x000 SPI Control Register 0 0x0000_0000 SPICR1 0x004...
Page 487 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [11:8] GUADT Guard Time GUADTEN=1 0x0:1 SCK 0x1:2 SCK 0x2: 3 SCK Note that GUADT is for master mode only. GUADTEN Guard Time Enable 0: Guard Time is 1/2 SCK 1: When set this bit, Guard time can be controlled by GUADT Note that GUADTEN is for master mode only.
Page 488: Spi Control Register 1 - Spicr1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 SPI Control Register 1 – SPICR1 This register specifies the SPI parameters including the data length, the transfer format, the SEL active polarity/ mode, the LSB/MSB control, and the master/slave mode. Offset:...
Page 489 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [10:8] FORMAT SPI Data Transfer Format These three bits are used to determine the data transfer format of the SPI interface FORMAT [2:0] CPOL CPHA Others Reserved CPOL: Clock Polarity...
Page 490: Spi Interrupt Enable Register - Spiier
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 SPI Interrupt Enable Register – SPIIER This register contains the corresponding SPI interrupt enable control bit. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset TOIEN SAIEN MFIEN ROIEN WCIEN...
Page 491: Spi Clock Prescaler Register - Spicpr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions TXBEIEN TX Buffer Empty Interrupt Enable 0: Disable 1: Enable The TX buffer empty interrupt request will be generated when the TXBE flag and the TXBEIEN bit are set. In the FIFO mode, the interrupt request being generated depends upon the TX FIFO trigger level setting.
Page 492: Spi Data Register - Spidr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 SPI Data Register – SPIDR This register stores the SPI received or transmitted Data. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Type/Reset 0 RW 0 RW 0 RW 0 RW...
Page 493: Spi Status Register - Spisr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 SPI Status Register – SPISR This register contains the relevant SPI status. Offset: 0x014 Reset value: 0x0000_0003 Reserved Type/Reset Reserved Type/Reset Reserved BUSY Type/Reset RXBNE TXBE Type/Reset 0 WC 0 WC 0 WC...
Page 494 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions Write Collision flag 0: No write collision 1: Write collision has occurred. This bit is set by hardware and cleared by writing 1. RXBNE Receive Buffer Not Empty flag...
Page 495: Spi Fifo Control Register - Spifcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 SPI FIFO Control Register – SPIFCR This register contains the related SPI FIFO control including the FIFO enable control and the FIFO trigger level selections. Offset: 0x018 Reset value: 0x0000_0000 Reserved Type/Reset...
Page 496: Spi Fifo Status Register - Spifsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 SPI FIFO Status Register – SPIFSR This register contains the relevant SPI FIFO status. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset RXFS TXFS Type/Reset 0 RO 0 RO...
Page 497: Spi Fifo Time Out Counter Register - Spiftocr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 SPI FIFO Time Out Counter Register – SPIFTOCR This register stores the SPI RX FIFO time out counter value. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset 0 RW 0 RW 0 RW...
Page 498: Universal Synchronous Asynchronous Receiver Transmitter (Usart)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Universal Synchronous Asynchronous Receiver Transmitter (USART) Introduction The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. The USART is used to translate data between parallel and serial interfaces, and is also commonly used for RS232 standard communication.
Page 499: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Features ▄ Supports both asynchronous and clocked synchronous serial communication modes ▄ Full Duplex Communication Capability ▄ Programming baud rate up to 3 Mbit/s for asynchronous mode and 6 Mbit/s for synchronous mode ▄...
Page 500: Function Descriptions
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Function Descriptions Serial Data Format The USART module performs a parallel-to-serial conversion on data that is written to the transmit FIFO registers and then sends the data with the following format: Start bit, 7 ~ 9 LSB first data bits, optional Parity bit and finally 1 ~ 2 Stop bits.
Page 501: Baud Rate Generation
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Baud Rate Generation The baud rate for the USART receiver and transmitter are both set with the same values. The baud- rate divisor, BRD, has the following relationship with the USART clock which is known as CK_ USART.
Page 502: Hardware Flow Control
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Table 54. Baud Rate Deviation Error Calculation – CK_USART = 48 MHz Baud rate CK_USART = 48 MHz Kbps Actual Deviation Error rate 20000 0.00% 5000 0.00% 19.2 19.2 2500 0.00% 57.6 57.6...
Page 503: Figure 164. Usart Rts Flow Control
Cortex ® -M0+ MCU HT32F52342/HT32F52352 RTS Flow Control In the RTS flow control, the USART RTS pin is active with a logic low state when the receive data register is empty. It means that the receiver is ready to receive a new data. When the RX FIFO reaches the trigger level which is specified by configuring the RXTL field in the USRFCR register, the USART RTS pin is inactive with a logic high state.
Page 504: Irda
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 IrDA The USART IrDA mode is provided half-duplex point-to-point wireless communication. The USART module includes an integrated modulator and demodulator which allow a wireless communication using infrared transceivers. The transmitter specifies a logic data ‘0’ as a ‘high’...
Page 505 Cortex ® -M0+ MCU HT32F52342/HT32F52352 IrDA Normal Mode For the IrDA normal mode, the width of each transmitted pulse generated by the transmitter modulator is specified as 3/16 of the baud rate clock period. The receiver pulse width for the IrDA receiver demodulator is based on the IrDA receive debounce filter which is implement using an 8-bit down-counting counter.
Page 506: Rs485 Mode
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 TX_Data Transmitter Modulation TXSEL RX_Data Receiver Demodulation IrDAEN Figure 167. USART I/O and IrDA Block Diagram RS485 Mode The RS485 mode of the USART provides the data transmission on the interface transmitted over a 2-wire twisted pair bus.
Page 507: Figure 168. Rs485 Interface And Waveform
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 RS-485 Transceiver Differential USART TG = 4 Reference Divisor Clock Stop D6 D7 Parity Start D1 D2 D3 D4 D5 TXENP =0 TXENP =1 Figure 168. RS485 Interface and Waveform Rev. 1.30...
Page 508 Cortex ® -M0+ MCU HT32F52342/HT32F52352 RS485 Normal Multi-drop Operation Mode – NMM When the RS485 mode is configured as an addressable slave, it will operate in the Normal Multi- drop Operation Mode, NMM. This mode is enabled when the RSNMM field is set in the RS485CR register.
Page 509: Synchronous Master Mode
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Synchronous Master Mode The data is transmitted in a full-duplex style in the USART Synchronous Master Mode, i.e., data transmission and reception both occur at the same time and only support master mode. The USART CTS pin is the synchronous USART transmitter clock output.
Page 510: Figure 170. 8-Bit Format Usart Synchronous Waveform
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 (CPS=1,WLS[1:0]=0x01,PBE=0) Clock (CPO=0) Clock (CPO=1) USART TX (From Start Stop Master to Slave) USART RX (From Slave to Master) (CPS=1,WLS[1:0]=0x00,PBE=1) Clock (CPO=0) Clock (CPO=1) USART TX (From Start Parity Stop Master to Slave)
Page 511: Interrupts And Status
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Interrupts and Status The USART can generate interrupts when the following event occurs and corresponding interrupt enable bits are set: ▄ Receive FIFO time-out interrupt: An interrupt will be generated when the USART receive FIFO does not receive a new data package during the specified time-out interval.
Page 512: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Descriptions USART Data Register – USRDR The register is used to access the USART transmitted and received FIFO data. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Type/Reset...
Page 513: Usart Control Register - Usrcr
Cortex ® -M0+ MCU HT32F52342/HT32F52352 USART Control Register – USRCR The register specifies the serial parameters such as data length, parity, and stop bit for the USART. It also contains the USART enable control bits together with the USART mode and data transfer mode selections.
Page 514 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [11] Parity Bit Enable 0: Parity bit is not generated (transmitted data) or checked (receive data) during transfer. 1: Parity bit is generated or checked during transfer. Note: When the WLS field is set to “10” to select the 9-bit data format, writing to the PBE bit has no effect.
Page 515: Usart Fifo Control Register - Usrfcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 USART FIFO Control Register – USRFCR This register specifies the USART FIFO control and configurations including threshold level and reset function together with the USART FIFO status. Offset: 0x008 Reset value: 0x0000_0000...
Page 516: Usart Interrupt Enable Register - Usrier
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions TX FIFO Reset Setting this bit will generate a reset pulse to reset TX FIFO which will empty the TX FIFO, i.e., the TX pointer will be reset to 0 after a reset signal. This bit returns to 0 automatically after the reset pulse is generated.
Page 517 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions FEIE Framing Error Interrupt Enable 0: Disable interrupt 1: Enable interrupt An interrupt will be generated when the FEI bit is set in the URSIFR register. PEIE Parity Error Interrupt Enable...
Page 518: Usart Status & Interrupt Flag Register - Usrsifr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 USART Status & Interrupt Flag Register – USRSIFR This register contains the corresponding USART status. Offset: 0x010 Reset value: 0x0000_0180 Reserved Type/Reset Reserved Type/Reset Reserved CTSS CTSC RSADDE Type/Reset 0 WC 0 WC...
Page 519 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions RXTOF Receive FIFO Time-Out Flag 0: RX FIFO Time-Out does not occur. 1: RX FIFO Time-Out occurs. This bit is clear when RX FIFO is empty. RXDR Receive FIFO Ready Flag...
Page 520: Usart Timing Parameter Register - Usrtpr
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 USART Timing Parameter Register – USRTPR This register contains the USART timing parameters including the transmitter time guard parameters and the receive FIFO time-out value together with the RX FIFO time-out function enable control.
Page 521: Usart Irda Control Register - Irdacr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 USART IrDA Control Register – IrDACR This register is used to control the IrDA mode of USART. Offset: 0x018 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset IrDAPSC Type/Reset 0 RW 0 RW...
Page 522: Usart Rs485 Control Register - Rs485Cr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions IrDAEN IrDA Enable control 0: Disable IrDA mode 1: Enable IrDA mode USART RS485 Control Register – RS485CR This register is used to control the RS485 mode of USART.
Page 523: Usart Synchronous Control Register - Syncr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 USART Synchronous Control Register – SYNCR This register is used to control the USART synchronous mode. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Reserved CLKEN Type/Reset 0 RW...
Page 524: Usart Divider Latch Register - Usrdlr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 USART Divider Latch Register – USRDLR The register is used to determine the USART clock divided ratio to generate the appropriate baud rate. Offset: 0x024 Reset value: 0x0000_0010 Reserved Type/Reset Reserved Type/Reset...
Page 525: Usart Test Register - Usrtstr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 USART Test Register – USRTSTR This register controls the USART debug mode. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset 0 RW Bits Field Descriptions [1:0] Loopback Test Mode Select...
Page 526: Universal Asynchronous Receiver Transmitter (Uart)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Universal Asynchronous Receiver Transmitter (UART) Introduction The Universal Asynchronous Receiver Transceiver, UART, provides a flexible full duplex data exchange using asynchronous transfer. The UART is used to translate data between parallel and serial interfaces, and is also commonly used for RS232 standard communication.
Page 527: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Features ▄ Supports asynchronous serial communication modes ▄ Full Duplex Communication Capability ▄ Programming baud rate up to 3 Mbit/s. ▄ Fully programmable serial communication functions including: ● Word length: 7, 8, or 9-bit character ●...
Page 528: Baud Rate Generation
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Baud Rate Generation The baud rate for the UART receiver and transmitter are both set with the same values. The baud- rate divisor, BRD, has the following relationship with the UART clock which is known as CK_ UART.
Page 529: Interrupts And Status
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Table 57. Baud Rate Deviation Error Calculation – CK_UART = 48 MHz Baud rate CK_UART = 48 MHz Kbps Actual Deviation Error rate 20000 0.00% 5000 0.00% 19.2 19.2 2500 0.00% 57.6 57.6...
Page 530: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Map The following table shows the UART registers and reset values. Table 58. UART Register Map Register Offset Description Reset Value URDR 0x000 UART Data Register 0x0000_0000 URCR 0x004 UART Control Register...
Page 531: Uart Control Register - Urcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 UART Control Register – URCR The register specifies the serial parameters such as data length, parity, and stop bit for the UART. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved...
Page 532 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [9:8] Word Length Select 00: 7 bits 01: 8 bits 10: 9 bits 11: Reserved RXDMAEN UART RX DMA Enable 0: Disabled 1: Enabled TXDMAEN UART TX DMA Enable...
Page 533: Uart Interrupt Enable Register - Urier
Cortex ® -M0+ MCU HT32F52342/HT32F52352 UART Interrupt Enable Register – URIER This register is used to enable the related UART interrupt function. The UART module generates interrupts to the controller when the corresponding events occur and the corresponding interrupt enable bits are set.
Page 534: Uart Status & Interrupt Flag Register - Ursifr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions TXDEIE Transmit Data Register Empty Interrupt Enable 0: Disable interrupt 1: Enable interrupt An interrupt is generated when the transmit data register empty interrupt is enabled and the TXDE bit is set in the URSIFR register.
Page 535 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions RXDR RX Data Ready 0: Receive data register is empty 1: Received data in the receive data register is ready to read. This bit is set by hardware when the content of the receive shift register RDR has been transferred to the URDR register.
Page 536: Uart Divider Latch Register - Urdlr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 UART Divider Latch Register – URDLR The register is used to determine the UART clock divided ratio to generate the appropriate baud rate. Offset: 0x024 Reset value: 0x0000_0010 Reserved Type/Reset Reserved Type/Reset...
Page 537: Uart Test Register - Urtstr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 UART Test Register – URTSTR This register controls the UART debug mode. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset 0 RW Bits Field Descriptions [1:0] Loopback Test Mode Select...
Page 538: Smart Card Interface (Sci)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Smart Card Interface (SCI) Introduction The Smart Card Interface, SCI, is compatible with the ISO 7816-3 standard. This interface includes functions for card Insertion/Removal detection, SCI data transfer control logic and data buffers, internal Timer Counters and corresponding control logic circuits to perform the required Smart Card operations.
Page 539: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Features ▄ Supports ISO 7816-3 standard ▄ Character Transfer Mode ▄ 1 transmit buffer and 1 receive buffer ▄ 11-bit ETU (elementary time unit) counter ▄ 9-bit guard time counter ▄ 24-bit general purpose waiting time counter ▄...
Page 540: Table 59. Di Field Based Di Encoded Decimal Values
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 where: ▄ etu is the nominal duration of the data bit on the signal SCI_DIO provided to the card by the interface ▄ Di is the bit-rate adjustment factor ▄ Fi is the clock rate conversion factor ▄...
Page 541: Guard Time Counter
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Compensation mode As the value of the ETUR register is obtained by the above procedure, the calculation results of the value may not be an integer. If the calculation result is not an integer and is less than the integer n but greater than the integer (n-1), either the integer n or (n-1) should be written into the ETUR register depending upon whether the result is closer to integer n or (n-1).
Page 542: Waiting Time Counter
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Start Start Start Start Char 0 Char 1 Char n SCI_DIO Start Start Start SCI_DIO Smart CardàSCI Char 0 Char 1 SCIàSmart Card Figure 176. Guard Time Duration Waiting Time Counter The Waiting Time counter, WT, is a 24-bit down counting counter which generates a maximum time duration, denoted as t , for data transfer.
Page 543: Card Clock And Data Selection
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Start bit Program the CWT Program the BWT SCI_DIO Char 0 Char 1 Char n Start bit SCI_DIO SCIàSmart Card Char 0 Char 1 BWT is reloaded on Start bit Smart CardàSCI Figure 177.
Page 544: Sci Data Transfer Mode
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 CPREF Edge Detection SCI_DET Card Insertion / Removal Interrupt request CARDIRE DETCNF Figure 178. SCI Card Detection Diagram SCI Data Transfer Mode The SCI data transfer with the external Smart Card is implemented with two operating modes. One is the SCI mode while the other is the Manual Mode.
Page 545 ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Repetition Function There is a Character Repetition function supported by the SCI transfer circuitry when a parity error occurs. The Character Repetition function is enabled by setting the CREP bit in the CR register to 1.
Page 546: Interrupt Generator
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Interrupt Generator There are several conditions for the SCI to generate an SCI interrupt. When these conditions are met, an interrupt signal will be generated to obtain the attention of the microcontroller. These conditions are a Smart Card Insertion/Removal, a Waiting Time Counter Underflow, a Parity error, an end of a Character Transmission or Reception and an empty Transmit buffer.
Page 547: Pdma Interface
Cortex ® -M0+ MCU HT32F52342/HT32F52352 PDMA Interface The PDMA interface is integrated in the SCI module. The PDMA function can be enabled by setting the TXDMA or RXDMA bit to 1 in the transmitter or receiver mode respectively. When the...
Page 548: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Descriptions SCI Control Register – CR This register contains the SCI control bits. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved RXDMA TXDMA Type/Reset 0 RW Reserved DETCNF ENSCI...
Page 549 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions SCIM SCI Mode Selection 0: SCI data transfer in manual mode 1: SCI data transfer in SCI mode This bit is set and cleared by the application program to select the SCI data Transfer Mode.
Page 550: Sci Status Register - Sr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 SCI Status Register – SR This register contains the SCI status bits. Offset: 0x004 Reset value: 0x0000_0080 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset TXBEF CPREF reserved TXCF RXCF PARF Type/Reset 1 RO...
Page 551 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions PARF Parity Error Request Flag. 0: No parity error occurs 1: Parity error has occurred This bit is set by hardware and cleared by writing a “0” into it. When a character is received, the parity check circuitry will check that the parity is correct or not.
Page 552: Sci Contact Control Register - Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 SCI Contact Control Register – CCR This register specifies the SCI pin setting and clock selection. Offset: 0x008 Reset value: 0x0000_0008 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset CLKSEL Reserved CDIO CCLK Reserved...
Page 553: Sci Elementary Time Unit Register - Etur
Cortex ® -M0+ MCU HT32F52342/HT32F52352 SCI Elementary Time Unit Register – ETUR The register specifies the value determined by the formula described in the ETU section. It also includes the Compensation function enable control bit for the ETU time granularity.
Page 554: Sci Guard Time Register - Gtr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 SCI Guard Time Register – GTR This register specifies the guard time value obtained from the Answer-to-Reset packet described in the Guard Time Counter section. Offset: 0x010 Reset value: 0x0000_000C Reserved Type/Reset...
Page 555: Sci Waiting Time Register - Wtr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 SCI Waiting Time Register – WTR This register specifies the waiting time value obtained from the Answer-to-Reset packet described in the Waiting Time Counter section. Offset: 0x014 Reset value: 0x0000_2580 Reserved Type/Reset...
Page 556: Sci Interrupt Enable Register - Ier
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 SCI Interrupt Enable Register – IER This register specifies the interrupt enable control bits for all of the interrupt events in the SCI. Offset: 0x018 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 557 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions RXCE Character Reception Completion interrupt enable control 0: Disabled 1: Enabled This bit is set and cleared by the application program and is used to control the Character Reception Completion interrupt. If this bit is set to 1, the Character Reception Completion interrupt will be generated at the end of the character reception.
Page 558: Sci Interrupt Pending Register - Ipr
Cortex ® -M0+ MCU HT32F52342/HT32F52352 SCI Interrupt Pending Register – IPR This register contains the interrupt pending flags for all of the interrupt events in the SCI. These pending flags can be masked by the corresponding interrupt enable control bits.
Page 559 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions TXCP Character Transmission Completion interrupt pending flag 0: No interrupt pending 1: Interrupt pending This bit is set by hardware and cleared by a read access to this register using the application program.
Page 560: Sci Transmit Buffer - Txb
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 SCI Transmit Buffer – TXB This register is used to store the SCI data to be transmitted. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Type/Reset 0 RW 0 RW...
Page 561: Sci Prescaler Register - Pscr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 SCI Prescaler Register – PSCR This register specifies the prescaler division ratio which is used the SCI internal clock. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset...
Page 562: Usb Device Controller (Usb)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 USB Device Controller (USB) Introduction The USB device controller is compliant with the USB 2.0 full-speed specification. There is one control endpoint know as Endpoint 0 and seven configurable endpoints (EP1~EP7). A 1024- byte EP-SRAM is used for the endpoint buffers.
Page 563: Functional Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Functional Descriptions Endpoints The USB Endpoint 0 is the only bidirectional endpoint dedicated to USB control transfer. The device also contains seven unidirectional endpoints for other USB transfer types. There are three endpoints (EP1~EP3) which supports a single buffering function which is used for Bulk and Interrupt IN or OUT data transfer.
Page 564: Serial Interface Engine - Sie
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 CK_USART BRD =18 Reference Divisor Clock Parity Bit Next Start Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bitn Stop Bit n=6~8 Figure 181. Endpoint Buffer Allocation Example Serial Interface Engine – SIE The Serial Interface Engine, SIE, which is connected to the USB full-speed transceiver and internal USB control circuitry provides a temporal buffer for the transmitted and received data.
Page 565: Figure 182. Double-Buffering Operation Example
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 IN Transaction Buffer toggled by SIE hardware Endpoint 4 Buffer Accessed Endpoint 4 Endpoint 4 by USB SIE Buf 0 Buf 1 Buf 0 1st Data packet 2nd Data packet 3rd Data packet...
Page 566: Suspend Mode And Wake-Up
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Suspend Mode and Wake-up According to USB specifications, the device must enter the suspend mode after a 3 ms bus idle time. When the USB device enters the suspend mode, the current from the USB bus must not be greater than 500 μA to meet the specification suspend mode current requirements.
Page 567 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Offset Description Reset Value USBEP3IER 0x054 USB Endpoint 3 Interrupt Enable Register 0x0000_0000 USBEP3ISR 0x058 USB Endpoint 3 Interrupt Status Register 0x0000_0000 USBEP3TCR 0x05C USB Endpoint 3 Transfer Count Register 0x0000_0000...
Page 568: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Descriptions USB Control and Status Register – USBCSR This register specifies the USB control bits and USB data line status. Offset: 0x000 Reset value: 0x0000_00X6 Reserved Type/Reset Reserved Type/Reset Reserved DPWKEN...
Page 569: Table 66. Resume Event Detection
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions LPMODE Low-power Mode Control This bit is used to determine the USB operating mode. Setting this bit will force the USB to enter the low-power mode. When USB bus traffic, known as a wakeup event, is detected by the hardware, this bit should be cleared by software.
Page 570: Usb Interrupt Enable Register - Usbier
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 USB Interrupt Enable Register – USBIER This register specifies the USB interrupt enable control. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EP7IE EP6IE EP5IE EP4IE EP3IE EP2IE EP1IE EP0IE Type/Reset...
Page 571: Usb Interrupt Status Register - Usbisr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 USB Interrupt Status Register – USBISR This register specifies the USB interrupt status. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EP7IF EP6IF EP5IF EP4IF EP3IF EP2IF EP1IF EP0IF Type/Reset 0 WC...
Page 572 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions URSTIF USB Reset Interrupt Flag This bit is set by the hardware when the USB reset has been detected. When a USB reset occurs, the internal protocol state machine will be reset and an USB reset interrupt will be generated if the URSTIE bit in the USBIER register is set to 1.
Page 573: Usb Frame Count Register - Usbfcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 USB Frame Count Register – USBFCR This register specifies the lost Start-of-Frame number and the USB frame count. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved LSOF SOFLCK Type/Reset 0 RO 0 RO...
Page 574: Usb Device Address Register - Usbdeva
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 USB Device Address Register – USBDEVA This register specifies the USB device address. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved DEVA Type/Reset 0 RW 0 RW 0 RW...
Page 575: Usb Endpoint 0 Control And Status Register - Usbep0Csr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 USB Endpoint 0 Control and Status Register – USBEP0CSR This register specifies the Endpoint 0 control and status. Offset: 0x014 Reset value: 0x0000_0002 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved STLRX NAKRX...
Page 576: Usb Endpoint 0 Interrupt Enable Register - Usbep0Ier
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions NAKTX NAK Status for transmission (IN) transfer This bit is toggled from 0 to 1 by the hardware circuitry, which will result in a NAK signal in the handshake phase of an IN transaction after an ACK signal has been received.
Page 577 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions STRXIE SETUP Token Received Interrupt Enable Control 0: Disable interrupt 1: Enable interrupt UERIE USB Error Interrupt Enable Control 0: Disable interrupt 1: Enable interrupt STLIE STALL Transmitted Interrupt Enable Control...
Page 578: Usb Endpoint 0 Interrupt Status Register - Usbep0Isr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 USB Endpoint 0 Interrupt Status Register – USBEP0ISR This register specifies the Endpoint 0 interrupt status. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved ZLRXIF SDERIF SDRXIF STRXIF Type/Reset 0 WC...
Page 579: Usb Endpoint 0 Transfer Count Register - Usbep0Tcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions IDTXIF IN Data Transmitted Interrupt Flag This bit is set by the hardware when a data packet is transmitted to and then an ACK signal is received from the USB host.
Page 580: Usb Endpoint 0 Configuration Register - Usbep0Cfgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 USB Endpoint 0 Configuration Register – USBEP0CFGR This register specifies the Endpoint 0 configurations. Offset: 0x024 Reset value: 0x8000_0002 EPEN Reserved EPADR Type/Reset 0 RO 0 RO 0 RO Reserved EPLEN Type/Reset...
Page 581: Usb Endpoint 1 ~ 3 Control And Status Register - Usbepncsr, N = 1 ~ 3
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 USB Endpoint 1 ~ 3 Control and Status Register – USBEPnCSR, n = 1 ~ 3 This register specifies the Endpoint 1 ~ 3 control and status bit. Offset: 0x028 (n = 1), 0x03C (n = 2), 0x050 (n = 3)
Page 582: Usb Endpoint 1 ~ 3 Interrupt Enable Register - Usbepnier, N = 1 ~ 3
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions DTGTX Data Toggle bit for transmission transfers. This bit contains the required value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be transmitted. When the current data packet is transmitted...
Page 583: Usb Endpoint 1 ~ 3 Interrupt Status Register - Usbepnisr, N = 1 ~ 3
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions ODRXIE OUT Data Received Interrupt Enable Control. 1: Enable interrupt 0: Disable interrupt OTRXIE OUT Token Received Interrupt Enable Control. 1: Enable interrupt 0: Disable interrupt USB Endpoint 1 ~ 3 Interrupt Status Register – USBEPnISR, n = 1 ~ 3 This register specifies the Endpoint 1 ~ 3 interrupt status.
Page 584: Usb Endpoint 1 ~ 3 Transfer Count Register - Usbepntcr, N = 1 ~ 3
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions ODOVIF OUT Data Buffer Overrun Interrupt Flag. This bit is set by the hardware circuitry when the received data byte count is larger than the corresponding endpoint OUT data buffersize.
Page 585: Usb Endpoint 1 ~ 3 Configuration Register - Usbepncfgr, N = 1 ~ 3
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 USB Endpoint 1 ~ 3 Configuration Register – USBEPnCFGR, n = 1 ~ 3 This register specifies the Endpoint 1 ~ 3 configurations. Offset: 0x038 (n = 1), 0x04C (n = 2), 0x060 (n = 3)
Page 586: Usb Endpoint 4 ~ 7 Control And Status Register - Usbepncsr, N = 4 ~ 7
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 USB Endpoint 4 ~ 7 Control and Status Register – USBEPnCSR, n = 4 ~ 7 This register specifies the Endpoint 4 ~ 7 control and status bits. Offset: 0x064 (n = 4), 0x078 (n = 5), 0x08C (n = 6), 0x0A0 (n = 7)
Page 587 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions MDBTG CPU Double Buffer Toggle bit The MDBTG bit is used to indicate which data buffer is accessed by the CPU if the double buffering function is enabled. It can be toggled to switch to the other buffer by the CPU application software after the data in the current buffer accessed by the CPU has been properly setup.
Page 588 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions DTGTX Data Toggle bit for transmission transfers. If the endpoint is not used for Isochronous transfer, this bit is available for usage. This bit contains the required value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted.
Page 589: Usb Endpoint 4 ~ 7 Interrupt Enable Register - Usbepnier, N = 4 ~ 7
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 USB Endpoint 4 ~ 7 Interrupt Enable Register – USBEPnIER, n = 4 ~ 7 This register specifies the Endpoint 4 ~ 7 interrupt enable control bits. Offset: 0x068 (n = 4), 0x07C (n = 5), 0x090 (n = 6), 0x0A4 (n = 7)
Page 590: Usb Endpoint 4 ~ 7 Interrupt Status Register - Usbepnisr, N = 4 ~ 7
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 USB Endpoint 4 ~ 7 Interrupt Status Register – USBEPnISR, n = 4 ~ 7 This register specifies the Endpoint 4 ~ 7 interrupt status. Offset: 0x06C (n = 4), 0x080 (n = 5), 0x094 (n = 6), 0x0A8 (n = 7)
Page 591: Usb Endpoint 4 ~ 7 Transfer Count Register - Usbepntcr, N = 4 ~ 7
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 USB Endpoint 4 ~ 7 Transfer Count Register – USBEPnTCR, n = 4 ~ 7 This register specifies the Endpoint 4 ~ 7 transfer byte count. Offset: 0x070 (n = 4), 0x084 (n = 5), 0x098 (n = 6), 0x0AC (n = 7)
Page 592: Usb Endpoint 4 ~ 7 Configuration Register - Usbepncfgr, N = 4 ~ 7
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 USB Endpoint 4 ~ 7 Configuration Register – USBEPnCFGR, n = 4 ~ 7 This register specifies the Endpoint 4 ~ 7 configurations. Offset: 0x074 (n = 4), 0x088 (n = 5), 0x09C (n = 6), 0x0B0 (n = 7)
Page 593: Peripheral Direct Memory Access (Pdma)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Peripheral Direct Memory Access (PDMA) Introduction The Peripheral Direct Memory Access circuitry, PDMA, provides 6 unidirectional channels for dedicated peripherals to implement the peripheral-to-memory and memory-to-peripheral data transfer. The memory-to-memory data transfer such as the FLASH-to-SRAM or SRAM-to- SRAM type is also supported and requested by the application program.
Page 594: Functional Description
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Functional Description AHB Master The PDMA is an AHB master connected to other AHB peripherals such as the FLASH memory, the SRAM memory and the AHB-to-APB bridges through the bus-matrix. The CPU and PDMA can access different AHB slaves at the same time via the bus-matrix.
Page 595: Table 67. Pdma Channel Assignments
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Peripheral request signals CH0 HW REQ High priority Channel 0 CH0 SW REQ SWTRIG Enable Channel 1 Channel 2 PDMA Request CHn HW REQ Channel n CHn SW REQ Low priority SWTRIG Enable Figure 184.
Page 596: Channel Transfer
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Channel transfer A PDMA channel transfer is split into multiple block transactions with PDMA arbitration occurring at the end of each block transaction. Although these channel transfers can all be activated, there is only one block transaction being transferred through the bus at a time. The channel transfer sequence depends upon the channel priority setting of each PDMA channel.
Page 597: Transfer Request
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Transfer Request For a peripheral-to-memory or memory-to-peripheral transfer, one peripheral hardware request will trigger one block transaction of the dedicated PDMA channel. However, a complete data transfer of the relevant dedicated PDMA channel will be triggered when a software request occurs. It is recommended that the PDMA channel is configured to have a lower priority level and a smaller block length which is requested by the software for memory-to-memory data copy applications.
Page 598: Transfer Interrupt
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Transfer Interrupt There are five transfer events during which the interrupts can be asserted for each PDMA channel. These are the block transaction end (BE), half-transfer (HT), transfer complete (TC), transfer error (TE) and global transfer event (GE). Setting the corresponding control bits in the PDMA interrupt enable register PDMAIER will enable the relevant interrupt events.
Page 599 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Offset Description Reset Value PDMA Base Address = 0x4009_0000 PDMACH4CTSR 0x074 PDMA Channel 4 Current Transfer Size Register 0x0000_0000 PDMA Channel 5 Registers PDMACH5CR 0x078 PDMA Channel 5 Control Register 0x0000_0000...
Page 600: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Descriptions PDMA Channel n Control Register – PDMACHnCR, n = 0 ~ 5 This register is used to specify the PDMA channel n data transfer configuration. Offset: 0x000 (0), 0x018 (1), 0x030 (2), 0x048 (3), 0x060 (4), 0x078 (5)
Page 601 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions SRCAMODn Channel n Source Address Mode selection 0: Linear address mode 1: Circular address mode In the linear address mode, the current source address value can be incremented or decremented, determined by the SRCAINCn bit value during a complete transfer.
Page 602: Pdma Channel N Source Address Register - Pdmachnsadr, N = 0 ~ 5
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 PDMA Channel n Source Address Register – PDMACHnSADR, n = 0 ~ 5 This register specifies the source address of the PDMA channel n. Offset: 0x004 (0), 0x01C (1), 0x034 (2), 0x04C (3), 0x064 (4), 0x07C (5)
Page 603: Pdma Channel N Destination Address Register - Pdmachndadr, N=0~5
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 PDMA Channel n Destination Address Register – PDMACHnDADR, n=0~5 This register specifies the destination address of the PDMA channel n. Offset: 0x008 (0), 0x020 (1), 0x038 (2), 0x050 (3), 0x068 (4), 0x080 (5)
Page 604: Pdma Channel N Transfer Size Register - Pdmachntsr, N = 0 ~ 5
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 PDMA Channel n Transfer Size Register – PDMACHnTSR, n = 0 ~ 5 This register is used to specify the block transaction count and block transaction length. Offset: 0x010 (0), 0x028 (1), 0x040 (2), 0x058 (3), 0x070 (4), 0x088 (5)
Page 605: Pdma Channel N Current Transfer Size Register - Pdmachnctsr, N=0~5
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 PDMA Channel n Current Transfer Size Register – PDMACHnCTSR, n=0~5 This register is used to indicate the current block transaction count. Offset: 0x014 (0), 0x02C (1), 0x044 (2), 0x05C (3), 0x074 (4), 0x08C (5)
Page 606: Pdma Interrupt Status Register - Pdmaisr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 PDMA Interrupt Status Register – PDMAISR This register is used to indicate the corresponding interrupt status of the PDMA channel 0 ~ 5. Offset: 0x120 Reset value: 0x0000_0000 Reserved TEISTA5 TCISTA5 HTISTA5...
Page 607: Pdma Interrupt Status Clear Register - Pdmaiscr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [ 2 5 ] , [ 2 0 ] , GEISTAn Channel n Global Transfer Interrupt Status (n= 0 ~ 5) [15], [10], [5], 0: No TE, TC, HT or BE event occurs 1: TE, TC, HT, or BE event occurs This bit is set by hardware and is cleared by writing a “1”...
Page 608 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [ 2 6 ] , [ 2 1 ] , BEICLRn Channel n Block Transaction End Interrupt Status Clear (n = 0 ~ 5) [16], [11], [6], 0: No Operation 1: Clear the corresponding BEISTAn bit in the PDMAISR register Writing a “1”...
Page 609: Pdma Interrupt Enable Register - Pdmaier
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 PDMA Interrupt Enable Register – PDMAIER This register is used to enable or disable the related interrupts of the PDMA channel 0 ~ 5. Offset: 0x130 Reset value: 0x0000_0000 Reserved TEIE5 TCIE5...
Page 610: Extend Bus Interface (Ebi)
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Extend Bus Interface (EBI) Introduction The external bus interface is able to access external parallel interface devices such as SRAM, Flash and LCD modules. The interface is memory mapped into the internal address bus of the CPU. The data and address lines can be multiplexed in order to reduce the number of pins required to connect to external devices.
Page 611: Function Descriptions
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Function Descriptions An overview of the EBI module is shown in Figure 186. The EBI enables internal CPU and other bus matrix master peripherals to access external memories or devices. The EBI automatically translates the internal AHB transactions into the external device protocol. In particular, if the selected external memory is 16 or 8 bits width, then 32-bit wide transactions on the AHB are auto split into consecutive 16 or 8-bit accesses.
Page 612: Non-Multiplexed 8-Bit Data 8-Bit Address Mode
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Non-multiplexed 8-bit Data 8-bit Address Mode In this mode, 8-bit address and 8-bit data is supported. The address is located on the higher 8 bits of the EBI_AD lines and the data uses the lower 8 bits. This mode is set by programming the MODE field in the EBICR register to D8A8.
Page 613: Non-Multiplexed 16-Bit Data N-Bit Address Mode
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Non-multiplexed 16-bit Data N-bit Address Mode In this non-multiplexed mode 16-bit data is provided on the 16 EBI_AD lines. The addresses are provided on the EBI_A lines. This mode is set by programming the MODE field in the EBICR register to D16.
Page 614: Multiplexed 16-Bit Data, 16-Bit Address Mode
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Multiplexed 16-bit Data, 16-bit Address Mode In this mode, 16-bit address and 16-bit data is supported, but the utilization of an external latch and an extra signal EBI_ALE is required. The 16-bit address and 16-bit data bits are multiplexed on the EBI_AD pins.
Page 615: Multiplexed 8-Bit Data, 20-Bit Address Mode
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 ADDRSETUP ADDRHOLD WESETUP WESTRB WEHOLD (1, 2, 3, …) (0, 1, 2, …) (0, 1, 2, …) (1, 2, 3, …) (0, 1, 2, …) EBI_AD[15:0] DATA[15:0] ADDR[16:1] EBI_ALE EBI_CSn EBI_WE Figure 193. EBI Multiplexed 16-bit Data, 16-bit Address Write Operation...
Page 616: Write Buffer And Ebi Status
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 ADDRSETUP ADDRHOLD WESETUP WESTRB WEHOLD (1, 2, 3, …) (0, 1, 2, …) (0, 1, 2, …) (1, 2, 3, …) (0, 1, 2, …) EBI_AD[15:8] ADDR[7:0] ADDR[19:16] EBI_AD[7:0] DATA[7:0] ADDR[15:8] EBI_ALE...
Page 617: Ahb Transaction Width Conversion
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 RDSETUP RDSTRB RDHOLD IDLE RDSETUP RDSTRB RDHOLD IDLE (0, 1, 2, …) (1, 2, 3, …) (0, 1, 2, …) (0, 1, 2, …) (1, 2, 3, …) (0, 1, 2, …)
Page 618: Table 70. Ebi Maps Ahb Transactions Width To External Device Transactions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Table 70. EBI Maps AHB Transactions Width to External Device Transactions. 8-bit External Device 16-bit External Device AHB Transaction Transaction Transaction 1 x 16-bit read 8-bit read 1 x 8-bit read (EBI ignore the superfluous data)
Page 619: Ebi Bank Access
Cortex ® -M0+ MCU HT32F52342/HT32F52352 EBI Bank Access The EBI is split into 4 different address regions and each owns an individual EBI_CSn line. When accessing one of the memory regions, the corresponding EBI_CSn line is asserted. This way up to 4 separate devices can share the EBI lines and be identified by the EBI_CSn line.
Page 620: Pdma Request
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 PDMA Request The EBI only supports a software trigger for activating a PDMA service. Register Map The following table shows the EBI register and reset value. Table 72. EBI Register Map Register...
Page 621 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [14] NOIDLE2 No IDLE 2 0: Enable IDLE state insertion 1: Disable IDLE state insertion Enable or disable the insertion of an idle state between transactions for bank 2.
Page 622: Ebi Status Register - Ebisr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 EBI Status Register – EBISR This register indicates the EBI status. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved EBISMRST Type/Reset Reserved EBIBUSY Type/Reset Bits Field Descriptions EBISMRST EBI State Machine Reset...
Page 623: Ebi Address Timing Register - Ebiatr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 EBI Address Timing Register – EBIATR This register specifies the address timing setting for each bank. Offset: 0x010 Reset value: 0x0000_0707 Reserved Type/Reset Reserved Type/Reset Reserved ADDRHOLD Type/Reset 1 RW Reserved ADDRSETUP...
Page 624: Ebi Read Timing Register - Ebirtr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 EBI Read Timing Register – EBIRTR This register specifies the read timing setting for each bank Offset: 0x014 Reset value: 0x0007_1F07 Reserved Type/Reset Reserved RDHOLD Type/Reset 1 RW 1 RW Reserved RDSTRB...
Page 625: Ebi Write Timing Register - Ebiwtr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 EBI Write Timing Register – EBIWTR This register specifies the write timing setting for each bank. Offset: 0x018 Reset value: 0x0007_1F07 Reserved Type/Reset Reserved WRHOLD Type/Reset 1 RW 1 RW Reserved WRSTRB...
Page 626: Ebi Parity Register - Ebipr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 EBI Parity Register – EBIPR This register specifies the polarity of the EBI control signal for each bank. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset 0 RW 0 RW Reserved...
Page 627: Inter-Ic Sound
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Inter-IC Sound (I Introduction The I S is a synchronous communication interface that can be used as a master or slave to exchange data with other audio peripherals, such as ADCs or DACs. The I S supports a variety of data formats.
Page 628: Functional Description
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Functional Description S Master and Slave Mode The I S can operate in slave or master mode. Within the I S module the difference between these modes lies in the word select (WS) signal which determines the timing of data transmissions.
Page 629: I 2 S Clock Rate Generator
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 S Clock Rate Generator The main (I S_MCLK) and bit clock (I S_BCLK) rates for the I S are determined by the values in the I2SCDR register. The required I S bit clock rate setting depends on the desired audio sample rate desired, the format (stereo/mono) used, and the data size.
Page 630: Table 73. Recommend Fs List @ 8 Mhz Pclk
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Table 73. Recommend FS List @ 8 MHz PCLK 512 F 384 F 256 F 192 F 128 F 64 F Fs (Hz) 8,000 — — 11,025 — — — — 12,000 —...
Page 631: I 2 S Interface Format
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 S Interface Format S-justified Stereo Mode The standard I S-justified mode is where the Most Significant Bit (MSB) of the stereo audio sample data is available on the second rising edge of the BCLK clock following a WS signal transition. In the stereo mode, a low WS state indicates left channel data and a high state indicates right channel data.
Page 632: Figure 204. Left-Justified Stereo Mode Waveforms
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Left-justified Stereo Mode Left-Justified mode is where the Most Significant Bit (MSB) of the stereo audio sample data is available on the first rising edge of BCLK following a WS transition. Figure 204 and Figure 205 are shown with a left I S-justified stereo mode format.
Page 633: Figure 206. Right-Justified Stereo Mode Waveforms
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Right-justified Stereo Mode Right-Justified mode is where the Least Significant Bit (LSB) of the stereo audio sample data is available on the rising edge of BCLK preceding a WS transition and where the MSB is transmitted first.
Page 634: Figure 208. I S-Justified Mono Mode Waveforms
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 S-justified Mono Mode In the I S-justified mono mode, the Most Significant Bit (MSB) of the mono audio sample data is available on the second rising edge of the BCLK clock following a falling edge on the WS signal.
Page 635: Figure 210. Left-Justified Mono Mode Waveforms
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Left-justified Mono Mode In the left-justified mono mode, the Most Significant Bit (MSB) of the mono audio sample data is available on the first rising edge of the BCLK clock following a falling edge on the WS signal.
Page 636: Figure 212. Right-Justified Mono Mode Waveforms
Cortex ® -M0+ MCU HT32F52342/HT32F52352 Right-justified Mono Mode In the right-justified mono mode, the Least Significant Bit (LSB) of the mono audio sample data is available on the last rising edge of the BCLK clock preceding a rising edge on the WS signal.
Page 637: Figure 214. I S-Justified Repeat Mode Waveforms
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 S-justified Repeat Mode In the I S-justified repeat mode, the Most Significant Bit (MSB) of the mono audio sample data is available on the second rising edge of the BCLK clock following a WS signal transition. In this mode the same data is transmitted twice, once when WS is low and again when WS is high.
Page 638: Fifo Control And Arrangement
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 FIFO Control and Arrangement The I S handles audio data for transmission and reception and is performed via the FIFO controller. Each transmitted or received FIFO has a depth of 8 words (8 × 32-bit) and can buffer the data. The format is dependent upon the stereo/mono mode and sample size setting.
Page 639: Pdma And Interrupt
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 PDMA and Interrupt When the level of received data in the RX FIFO is equal to or greater than the level defined by the RXFTLS field in the I S FIFO control register (I2SFCR), the relative RXFTL flag will be set and then an I S RX PDMA request will be generated.
Page 640: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Descriptions S Control Register – I2SCR This register specifies the corresponding I S function enable control. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved MCKINV BCKINV RCSEL RCEN Type/Reset 0 RW...
Page 641 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [11] CHANNEL Stereo or Mono 0: Stereo 1: Mono Note: This bit should be configured when I S is disabled. [10] REPEAT Repeat Mode 0: Disable 1: Enable This mode is for I S-justified stereo configuration only, transmitting the mono data on both channels and receiving just the left channel data and ignoring the right.
Page 642: I 2 S Interrupt Enable Register - I2Sier
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 S Interrupt Enable Register – I2SIER This register contains the corresponding I S interrupt enable bits. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved RXOVIEN RXUDIEN RXFTLIEN Reserved...
Page 643: I 2 S Clock Divider Register - I2Scdr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 S Clock Divider Register – I2SCDR This register specifics the I S clock divider ratio. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset N_DIV Type/Reset 0 RW 0 RW 0 RW 0 RW...
Page 644: I 2 S Tx Data Register - I2Stxdr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 S TX Data Register – I2STXDR This register is used to specify the I S transmitted data. Offset: 0x00C Reset value: 0x0000_0000 TXDR Type/Reset 0 WO 0 WO 0 WO 0 WO...
Page 645: I 2 S Fifo Control Register - I2Sfcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 S FIFO Control Register – I2SFCR This register contains the related I S FIFO control bits. Offset: 0x014 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved RXFRST TXFRST Type/Reset 0 RW RXFTLS...
Page 646: I 2 S Status Register - I2Ssr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 S Status Register – I2SSR This register contains the relevant I S status. Offset: 0x018 Reset value: 0x0000_0809 RXFS TXFS Type/Reset 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO...
Page 647 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Bits Field Descriptions [10] RXFOV RX FIFO Overflow Flag 0: RX FIFO not overflow 1: RX FIFO overflow This bit is set by hardware and cleared by writing 1. RXFUD RX FIFO Underflow Flag...
Page 648: I 2 S Rate Counter Value Register - I2Srcntr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 S Rate Counter Value Register – I2SRCNTR This register specifics the I S rate control counter value. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset 0 RW 0 RW 0 RW 0 RW...
Page 649: Cyclic Redundancy Check (Crc)
® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Cyclic Redundancy Check (CRC) Introduction The CRC (Cyclic Redundancy Check) calculation unit is an error detection technique test algorithm and uses to verify data transmission or storage data correctness. A CRC calculation takes a data stream or a block of data as input and generates a 16- or 32-bit output remainder.
Page 650: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Features ▄ Support CRC16 polynomial: 0x8005, X ▄ Support CCITT CRC16 polynomial: 0x1021, X ▄ Support IEEE-802.3 CRC32 polynomial: 0x04C11DB7, X +X+1 ▄ Support 1’s complement, byte reverse & bit reverse operation on data and checksum ▄...
Page 651: Crc With Pdma
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Byte 3 Byte 2 Byte 1 Byte 0 Input data is big-endian Byte Reversal Enable Byte 0 Byte 1 Byte 2 Byte 3 Bit Reversal Enable Byte 0 Byte 1 Byte 2 Byte 3 Figure 218.
Page 652: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 Register Descriptions CRC Control Register – CRCCR This register specifies the corresponding CRC function enable control. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset SUMCMPL SUMBYRV SUMBIRV DATCMPL DATBYRV...
Page 653: Crc Seed Register - Crcsdr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 CRC Seed Register – CRCSDR This register is used to specify the CRC seed. Offset: 0x004 Reset value: 0x0000_0000 SEED Type/Reset 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO...
Page 654 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 CRC Checksum Register – CRCCSR This register contains the CRC checksum output. Offset: 0x008 Reset value: 0x0000_0000 CHKSUM Type/Reset 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO...
Page 655 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52342/HT32F52352 CRC Data Register – CRCDR This register is used to specify the CRC input data. Offset: 0x00C Reset value: 0x0000_0000 CRCDATA Type/Reset 0 WO 0 WO 0 WO 0 WO 0 WO...
Page 656 Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.

This manual is also suitable for:

Ht32f52352

Holtek HT32F52342 User Manual

1 Introduction

2 Document Conventions

3 System Architecture

4 Flash Memory Controller (FMC)

5 Power Control Unit (PWRCU)

6 Clock Control Unit (CKCU)

7 Reset Control Unit (RSTCU)

8 General Purpose I/O (GPIO)

9 Alternate Function Input/Output Control Unit (AFIO)

10 Nested Vectored Interrupt Controller (NVIC)

11 External Interrupt/Event Controller (EXTI)

12 Analog to Digital Converter (ADC)

13 Comparator (CMP)

Quick Links

Need help?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Holtek HT32F52342

Summary of Contents for Holtek HT32F52342