Figure 94. Up-Counting Example; Figure 95. Down-Counting Example - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
CK_PSC
CNT_EN
CK_CNT
CNTR F2
CRR F5
CRR Shadow
Register
PSCR
PSCR Shadow
Register
PSC_CNT
Counter Overflow
Update Event 1
Flag
Write a new value

Figure 94. Up-counting Example

Down-Counting
In this mode the counter counts continuously from the counter-reload value, which is defined in
the CRR register, to 0 in a count-down direction. Once the counter reaches 0, the Timer module
generates an underflow event and the counter restarts to count once again from the counter-reload
value. This action will continue repeatedly. The counting direction bit DIR in the CNTCFR register
should be set to 1 for the down-counting mode.
When an update event 1 is generated by setting the UEV1G bit in the EVGR register to 1, the
counter value will also be initialised to the counter-reload value.
CK_PSC
CNT_EN
CK_CNT
CNTR 3
CRR F5
CRR Shadow
Register
PSCR 0
PSCR Shadow
Register
PSC_CNT
Counter Underflow
Update Event 1
Flag
Write a new value

Figure 95. Down-counting Example

Rev. 1.00
F3 F4 F5
F5
0
0
0
Update the new value
2 1 0
F5
0
0
Update a new value
300 of 486
0 1
36
36
1
1
0 1 0 1
Software clearing
36 35
36
36
1
1
0 1 0 1
Software clearing
2 3
0 1 0 1
34 33
0 1 0 1
July 31, 2018