Timer Interrupt Status Register - Intsr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Bits Field
[0] CH0CG
Timer Interrupt Status Register – INTSR
This register stores the timer interrupt status.
Offset: 0x07C
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[10] TEVIF
[8] UEVIF
[3] CH3CIF
Rev. 1.00
Descriptions
Channel 0 Compare Generation
A Channel 0 compare event can be generated by software setting this bit. It is
cleared by hardware automatically.
0: No action
1: Compare event is generated on channel 0
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
Reserved
Descriptions
Trigger Event Interrupt Flag
This flag is set by hardware on a trigger event and is cleared by software.
0: No trigger event occurs
1: Trigger event occurs
Update Event Interrupt Flag
This bit is set by hardware on an update event and is cleared by software.
0: No update event occurs
1: Update event occurs
Note: The update event is derived from the following conditions:
- The counter overflows or underflows
- The UEVG bit is asserted
- A restart trigger event occurs from the slave trigger input
Channel 3 Compare Interrupt Flag
0: No match event occurs
1: The content of the counter CNTR has matched the contents of the CH3CR register
This flag is set by hardware when the counter value matches the CH3CR value
except in the center-aligned mode. It is cleared by software.
285 of 486
27 26
Reserved
19 18
Reserved
11 10
TEVIF Reserved
RW 0
3 2
CH3CIF CH2CIF CH1CIF
RW 0 RW 0 RW
25 24
17 16
9 8
UEVIF
RW 0
1 0
CH0CIF
0 RW 0
July 31, 2018