Usart Interrupt Enable Register - Usrier - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Bits Field
[0] TXR
USART Interrupt Enable Register – USRIER
This register is used to enable the related USART interrupt function. The USART module generates interrupts to
the controller when the corresponding events occur and the corresponding interrupt enable bits are set.
Offset: 0x00C
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
RSADDIE
Type/Reset RW 0 RW
Bits Field
[9] CTSIE
[8] RXTOIE
[7] RSADDIE
[6] BIE
Rev. 1.00
Descriptions
TX FIFO Reset
Setting this bit will generate a reset pulse to reset the TX FIFO which will empty the
TX FIFO, i.e., the TX pointer will be reset to 0 after a reset signal. This bit returns to
0 automatically after the reset pulse is generated.
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
BIE FEIE PEIE
0 RW 0 RW
Descriptions
CTS Clear-To-Send Interrupt Enable
0: Disable interrupt
1: Enable interrupt
If this bit is set, an interrupt will be generated when the CTSC bit is set in the
USRSIFR register.
Receive FIFO Time-Out Interrupt Enable
0: Disable interrupt
1: Enable interrupt
If this bit is set, an interrupt will be generated when the RXTOF bit is set in the
USRSIFR register.
RS485 Address Detection Interrupt Enable
0: Disable interrupt
1: Enable interrupt
If this bit is set, an interrupt will be generated when the RSADD bit is set in the
USRSIFR register.
Break Interrupt Enable
0: Disable interrupt
1: Enable interrupt
If this bit is set, an interrupt will be generated when the BII bit is set in the
USRSIFR register.
455 of 486
27 26
Reserved
19 18
Reserved
11 10
RW
3 2
OEIE TXCIE
0 RW 0 RW 0 RW
25 24
17 16
9 8
CTSIE RXTOIE
0 RW 0
1 0
TXDEIE RXDRIE
0 RW 0
July 31, 2018