Timer Event Generator Register - Evgr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Timer Event Generator Register – EVGR
This register contains the software event generation bits.
Offset: 0x078
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[10] TEVG
[8] UEVG
[3] CH3CG
[2] CH2CG
[1] CH1CG
Rev. 1.00
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
Reserved
Descriptions
Trigger Event Generation
The trigger event TEV can be generated by setting this bit. It is cleared by hardware
automatically.
0: No action
1: TEVIF flag is set
Update Event Generation
The update event UEV can be generated by setting this bit. It is cleared by hardware
automatically.
0: No action
1: Reinitialize the counter
The counter value returns to 0 or the CRR preload value, depending on the
counter mode in which the current timer is being used. An update operation of
any related registers will also be performed. For more detailed descriptions,
refer to the corresponding section.
Channel 3 Compare Generation
A Channel 3 compare event can be generated by software setting this bit. It is
cleared by hardware automatically.
0: No action
1: Compare event is generated on channel 3
Channel 2 Compare Generation
A Channel 2 compare event can be generated by software setting this bit. It is
cleared by hardware automatically.
0: No action
1: Compare event is generated on channel 2
Channel 1 Compare Generation
A Channel 1 compare event can be generated by software setting this bit. It is
cleared by hardware automatically.
0: No action
1: Compare event is generated on channel 1
284 of 486
27 26
Reserved
19 18
Reserved
11 10
TEVG Reserved
WO 0
3 2
CH3CG CH2CG CH1CG
WO 0 WO 0 WO
25 24
17 16
9 8
UEVG
WO 0
1 0
CH0CG
0 WO 0
July 31, 2018