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Summary of Contents for Holtek HT32F52243
- Page 1 Holtek 32-Bit Microcontroller with Arm ® Cortex ® -M0+ Core HT32F52243/HT32F52253 User Manual Revision: V1.20 Date: September 19, 2018...
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Page 2: Table Of Contents
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Table of Contents 1 Introduction ......................22 Overview ..........................22 Features ..........................23 Device Information ....................... 27 Block Diagram ........................28 2 Document Conventions ..................29 3 System Architecture ..................... 30 ®... - Page 3 ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Flash Vector Mapping Control Register – VMCR ................55 Flash Manufacturer and Device ID Register – MDID ..............56 Flash Page Number Status Register – PNSR ................57 Flash Page Size Status Register – PSSR ..................58 Device ID Register –...
- Page 4 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 AHB Configuration Register – AHBCFGR ..................87 AHB Clock Control Register – AHBCCR ..................88 APB Configuration Register – APBCFGR ..................90 APB Clock Control Register 0 – APBCCR0 ..................91 APB Clock Control Register 1 – APBCCR1 ..................92 Clock Source Status Register –...
- Page 5 ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port A Output Reset Register – PARR ..................125 Port B Data Direction Control Register – PBDIRCR ..............125 Port B Input Function Enable Control Register – PBINER ............126 Port B Pull-Up Selection Register – PBPUR ................127 Port B Pull-Down Selection Register –...
- Page 6 Cortex ® -M0+ MCU HT32F52243/HT32F52253 EXTI Source Selection Register 1 – ESSR1 ................157 GPIO Port x Configuration Low Register – GPxCFGLR, x = A, B, C, D ........158 GPIO Port x Configuration High Register – GPxCFGHR, x = A, B, C, D ........159 10 Nested Vectored Interrupt Controller (NVIC) ..........
- Page 7 ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 ADC Conversion List Register 0 – ADCLST0 ................183 ADC Conversion List Register 1 – ADCLST1 ................184 ADC Input Sampling Time Register – ADCSTR ................185 ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7 ............... 186 ADC Trigger Control Register –...
- Page 8 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 2 Output Configuration Register – CH2OCFR ............... 239 Channel 3 Output Configuration Register – CH3OCFR ............... 241 Channel Control Register – CHCTR ..................... 243 Channel Polarity Configuration Register – CHPOLR ..............244 Timer PDMA/Interrupt Control Register –...
- Page 9 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Output Stage ..........................277 Update Management ........................287 Single Pulse Mode ........................289 Asymmetric PWM Mode ....................... 291 Timer Interconnection ........................292 Trigger ADC Start.......................... 296 Lock Level Table ........................... 296 PDMA Request ..........................297 Register Map ........................
- Page 10 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 16 Single-Channel Timer (SCTM) ................. 342 Introduction ........................342 Features ..........................342 Functional Descriptions ..................... 343 Counter Mode ..........................343 Clock Controller ..........................343 Trigger Controller .......................... 344 Slave Controller ..........................346 Channel Controller ........................
- Page 11 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 RTC Control Register – RTCCR ....................376 RTC Status Register – RTCSR..................... 378 RTC Interrupt and Wakeup Enable Register – RTCIWEN ............379 18 Watchdog Timer (WDT) ..................380 Introduction ........................380 Features ..........................
- Page 12 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 C Address Register – I2CADDR ....................407 C Status Register – I2CSR ......................408 C SCL High Period Generation Register – I2CSHPGR ...............411 C SCL Low Period Generation Register – I2CSLPGR ............... 412 C Data Register –...
- Page 13 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Descriptions ......................453 USART Data Register – USRDR ....................453 USART Control Register – USRCR ....................454 USART FIFO Control Register – USRFCR................... 456 USART Interrupt Enable Register – USRIER ................457 USART Status &...
- Page 14 ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Descriptions ......................483 PDMA Channel n Control Register – PDMACHnCR, n = 0 ~ 5 ............ 483 PDMA Channel n Source Address Register – PDMACHnSADR, n = 0 ~ 5 ........485 PDMA Channel n Destination Address Register – PDMACHnDADR, n = 0 ~ 5 ......485 PDMA Channel n Transfer Size Register –...
- Page 15 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 List of Tables Table 1. Features and Peripheral List ..................... 27 Table 2. Document Conventions ......................29 Table 3. Register Map ..........................34 Table 4. Flash Memory and Option Byte ....................38 Table 5.
- Page 16 ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Table 40. SCTM Register Map ......................354 Table 41. LSE Startup Mode Operating Current and Startup Time ............371 Table 42. RTCOUT Output Mode and Active Level Setting ..............373 Table 43. RTC Register Map......................... 374 Table 44.
- Page 17 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 List of Figures Figure 1. Block Diagram ......................... 28 Figure 2. Cortex -M0+ Block Diagram ....................31 ® Figure 3. Bus Architecture ........................32 Figure 4. Memory Map ..........................33 Figure 5. Flash Memory Controller Block Diagram ................. 36 Figure 6.
- Page 18 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Figure 40. GPTM in Trigger Mode ......................202 Figure 41. Master GPTMn and Slave GPTMm/MCTMm Connection ........... 203 Figure 42. MTO Selection ........................203 Figure 43. Capture/Compare Block Diagram ..................204 Figure 44. Input Capture Mode ......................204 Figure 45.
- Page 19 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Figure 81. MTO Selection ........................273 Figure 82. Capture/Compare Block Diagram ..................274 Figure 83. Input Capture Mode ......................274 Figure 84. PWM Pulse Width Measurement Example ................275 Figure 85. Channel 0 and Channel 1 Input Stages ................276 Figure 86.
- Page 20 ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Figure 121. Input Capture Mode ......................349 Figure 122. Channel Input Stages ......................349 Figure 123. TI Digital Filter Diagram with N = 2 ..................350 Figure 124. Output Stage Block Diagram ..................... 350 Figure 125.
- Page 21 ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Figure 162. IrDA Modulation and Demodulation ................... 445 Figure 163. USART I/O and IrDA Block Diagram ................. 447 Figure 164. RS485 Interface and Waveform ..................448 Figure 165. USART Synchronous Transmission Example ..............449 Figure 166.
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Page 22: Introduction
Nested Vectored Interrupt Controller (NVIC), SysTick timer, and including advanced debug support. The devices operate at a frequency of up to 40 MHz for HT32F52243/52253 with a Flash accelerator to obtain maximum efficiency. It provides up to 128 KB of embedded Flash memory for code/ data storage and 16 KB of embedded SRAM memory for system operation and application program usage. -
Page 23: Features
Features ▄ Core ● 32-bit Arm ® Cortex ® -M0+ processor core ● Up to 40 MHz operating frequency for HT32F52243/52253 ● Single-cycle multiplication ● Integrated Nested Vectored Interrupt Controller (NVIC) ● 24-bit SysTick timer ▄ On-chip Memory ● Up to 128 KB on-chip Flash memory for instruction/data and options storage ●... - Page 24 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 ▄ IO ports – GPIO ● Up to 51 GPIOs ● Port A, B, C, D are mapped as 16 external interrupts – EXTI ● Almost I/O pins are configurable output driving current ▄...
- Page 25 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 ▄ Real Time Clock – RTC ● 24-bit up-counter with a programmable prescaler ● Alarm function ● Interrupt and Wake-up event ▄ Inter-integrated Circuit – I ● Supports both master and slave modes with a frequency of up to 1 MHz ●...
- Page 26 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 ▄ Peripheral Direct Memory Access – PDMA ● 6 channels with trigger source grouping ● 8-bit /16-bit /32-bit width data transfer ● Supports Address increment, decrement or fixed mode ● 4-level programmable channel priority ●...
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Page 27: Device Information
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Device Information Table 1. Features and Peripheral List Peripherals HT32F52243 HT32F52253 Main Flash (KB) Option Bytes Flash (KB) SRAM (KB) MCTM GPTM SCTM Timers BFTM USART Communication UART PDMA 6 channels Hardware Divider... -
Page 28: Block Diagram
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Block Diagram PA ~ PC[15:0], PD[3:0] SWCLK SWDIO BOOT Powered by V DD15 /PDR Flash Memory Flash SW-DP XTALIN Interface Memory GPIO XTALOUT 4 ~ 16 MHz ® Cortex -M0+ PDMA CKCU/RSTCU... -
Page 29: Document Conventions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Document Conventions The conventions used in this document are shown in the following table. Table 2. Document Conventions Notation Example Description The number string with a 0x prefix indicates a 0x5a05 hexadecimal number. -
Page 30: System Architecture
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 System Architecture The system architecture of devices that includes the Arm ® Cortex ® -M0+ processor, bus architecture and memory organization will be described in the following sections. The Cortex ® -M0+ is a next generation processor core which offers many new features. -
Page 31: Bus Architecture
Figure 2. Cortex ® -M0+ Block Diagram Bus Architecture The HT32F52243/HT32F52253 series consist of one master and four slaves in the bus architecture. The Cortex -M0+ AHB-Lite bus is the master while the internal SRAM access bus, the internal ®... -
Page 32: Memory Organization
-M0+ system peripherals. Refer to the Arm ® Cortex ® -M0+ Technical Reference Manual for more information. The following figure shows the memory map of HT32F52243/HT32F52253 series of devices, including Code, SRAM, peripheral, and other pre- defined regions. Rev. 1.20 32 of 501 September 19, 2018... -
Page 33: Memory Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Memory Map 0xFFFF_FFFF 0x400F_FFFF Reserved Reserved 0x400C_C000 0x400C_A000 0xE010_0000 Reserved 0x400B_8000 Private peripheral bus 0x400B_0000 GPIO A ～ D 0xE000_0000 Reserved 0x4009_2000 0x4009_0000 PDMA_REG 0x4008_C000 Reserved 0x4008_A000 0x4008_8000 CKCU/RSTCU 0x4008_2000 Reserved Reserved... -
Page 34: Table 3. Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Table 3. Register Map Start Address End Address Peripheral 0x4000_0000 0x4000_0FFF USART0 0x4000_1000 0x4000_1FFF UART0 0x4000_2000 0x4000_2FFF UART2 0x4000_3000 0x4000_3FFF Reserved 0x4000_4000 0x4000_4FFF SPI0 0x4000_5000 0x4000_7FFF Reserved 0x4000_8000 0x4000_8FFF I2C2 0x4000_9000 0x4000_FFFF... -
Page 35: Embedded Flash Memory
Programming (IAP) or In Circuit Programming (ICP). For more information, refer to the Flash Memory Controller section. Embedded SRAM Memory The HT32F52243/HT32F52253 series contain up to 16 KB on-chip SRAM which is located at address 0x2000_0000. It support byte, half-word and word access operations. AHB Peripherals The address of the AHB peripherals ranges from 0x4008_0000 to 0x400F_FFFF. -
Page 36: Flash Memory Controller (Fmc)
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Flash Memory Controller (FMC) Introduction The Flash Memory Controller (FMC) provides functions of flash operation and pre-fetch buffer for the embedded on-chip Flash memory. The figure below shows the block diagram of FMC which includes programming interface, control registers, pre-fetch buffer, and access interface. -
Page 37: Functional Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Functional Descriptions Flash Memory Map The following figure is the Flash memory map of the system. The address ranges from 0x0000_0000 to 0x1FFF_FFFF (0.5 GB). The address from 0x1F00_0000 to 0x1F00_07FF is mapped to Boot Loader Block (2 KB). -
Page 38: Flash Memory Architecture
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Flash Memory Architecture The Flash memory consists of up to 128 KB main Flash with 1 KB per page and 2 KB Information Block for Boot Loader. The main Flash memory contains totally 128 pages (or 64 pages for 64 KB device) which can be erased individually. -
Page 39: Booting Configuration
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Booting Configuration The system provides two kinds of boot modes which can be selected using the BOOT pin. The BOOT pin is sampled during a power-on reset or system reset. Once the logic value is decided, the first 4 words of vector will be remapped to the corresponding source according to the boot modes. -
Page 40: Page Erase
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Page Erase The FMC provides a page erase function which is used to reset partial content of Flash memory. Each page can be erased independently without affecting the contents of other pages. The following steps show the access sequence of the register for a page erase operation. -
Page 41: Mass Erase
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Mass Erase The FMC provides a complete erase function which is used to initialize all the main Flash memory contents to a high state. The following steps show the mass erase operation register access sequence. -
Page 42: Word Programming
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Word Programming The FMC provides a 32-bit word programming function which is used to modify the Flash memory content. The following steps show the word programming operation register access sequence. ▄ Check the OPCR register to confirm that no Flash memory operation is in progress (OPM [3:0] equals to 0xE, or 0x6). -
Page 43: Option Byte Description
Description Reset Value Option Byte Base Address = 0x1FF0_0000 Flash Page Erase/Program Protection (n = 0 ~ 127) For HT32F52243 OB_PP [n] (n = 0 ~ 63) 0: Flash Page n Erase / Program Protection is enabled 1: Flash Page n Erase / Program Protection is... -
Page 44: Page Erase/Program Protection
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Page Erase/Program Protection The FMC provides page erase/program protection function to prevent unexpected operation of Flash memory. The page erase (CMD [3:0] = 0x8 in the OCMR register) or word program (CMD [3:0] = 0x4) command will not be accepted by FMC on the protected pages. When the page erase... -
Page 45: Security Protection
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Security Protection The FMC provides a Security protection function to prevent illegal code/data access of the Flash memory. This function is useful for protecting the software / firmware from the illegal users. The function is activated by configuring the Option Byte OB_CP [0] bit. Once the function has been enabled, all the main Flash data access through ICP/Debug mode, programming, and page erase operation will not be allowed except the user’s application. -
Page 46: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Map The following table shows the FMC registers and reset values. Table 10. FMC Register Map Register Offset Description Reset Value FMC Base Address = 0x4008_0000 TADR 0x000 Flash Target Address Register... -
Page 47: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Descriptions Flash Target Address Register – TADR This register specifies the target address of the page erase and word programming operations. Offset: 0x000 Reset value: 0x0000_0000 TADB Type/Reset 0 RW 0 RW... -
Page 48: Flash Write Data Register - Wrdr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Flash Write Data Register – WRDR This register specifies the data to be written for programming operation. Offset: 0x004 Reset value: 0x0000_0000 WRDB Type/Reset 0 RW 0 RW 0 RW 0 RW... -
Page 49: Flash Operation Command Register - Ocmr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Flash Operation Command Register – OCMR This register is used to specify the Flash operation commands that include the word programming, page erase and mass erase. Offset: 0x00C Reset value: 0x0000_0000 Reserved... -
Page 50: Flash Operation Control Register - Opcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Flash Operation Control Register – OPCR This register is used for controlling the command commitment and checking the status of the FMC operations. Offset: 0x010 Reset value: 0x0000_000C Reserved Type/Reset Reserved Type/Reset... -
Page 51: Flash Operation Interrupt Enable Register - Oier
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Flash Operation Interrupt Enable Register – OIER This register is used to enable or disable the FMC interrupt function. The FMC generates interrupts to the controller when corresponding interrupt enable bits are set. Offset:... -
Page 52: Flash Operation Interrupt And Status Register - Oisr
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Flash Operation Interrupt and Status Register – OISR This register indicates the FMC interrupt status which is used to check if a Flash operation has been finished or an error occurs. The status bits, bit [4:0], are available when the corresponding bits in the OIER register are set. -
Page 53: Flash Page Erase/Program Protection Status Register - Ppsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions ITADF Invalid Target Address Flag 0: The target address is valid 1: The target address is invalid The data in the TADR field must be within the range from 0x0000_0000 to 0x1FFF_FFFF. -
Page 54: Flash Security Protection Status Register - Cpsr
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Flash Security Protection Status Register – CPSR This register indicates the Flash Memory Security protection status. The content of this register is not dynamically updated and will only be reloaded by the Option Byte loader which is active when any kind of reset occurs. -
Page 55: Flash Vector Mapping Control Register - Vmcr
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Flash Vector Mapping Control Register – VMCR This register is used to control the vector mapping. The reset value of the VMCR register is determined by the external booting pin, BOOT, during the power-on reset period. -
Page 56: Flash Manufacturer And Device Id Register - Mdid
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Flash Manufacturer and Device ID Register – MDID This register is used to store the manufacture ID and device part number information which can be used as the product identity. Offset: 0x180... -
Page 57: Flash Page Number Status Register - Pnsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Flash Page Number Status Register – PNSR This register is used to indicate the Flash memory page number. Offset: 0x184 Reset value: 0x0000_00XX PNSB Type/Reset 0 RO 0 RO 0 RO 0 RO... -
Page 58: Flash Page Size Status Register - Pssr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Flash Page Size Status Register – PSSR This register is used to indicate the page size in bytes. Offset: 0x188 Reset value: 0x0000_0400 PSSB Type/Reset 0 RO 0 RO 0 RO 0 RO... -
Page 59: Flash Pre-Fetch Control Register - Cfcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Flash Pre-fetch Control Register – CFCR This register is used for controlling the FMC pre-fetch module. Offset: 0x200 Reset value: 0x0000_0011 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved PFBE Reserved WAIT Type/Reset... -
Page 60: Custom Id Register N - Cidrn (N = 0 ~ 3)
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Custom ID Register n – CIDRn (n = 0 ~ 3) This register is used to store the custom ID information which can be used as the custom identity. Offset: 0x310 (0) ~ 0x31C (3) Reset value: Various depending on Flash Manufacture Privilege Information Block. -
Page 61: Power Control Unit (Pwrcu)
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Power Control Unit (PWRCU) Introduction The power consumption can be regarded as one of the most important issues for many embedded system applications. Accordingly the Power Control Unit, PWRCU, provides many types of power saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2, and Power-Down modes. -
Page 62: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Features ▄ Two power domains: V 3.3 V and V 1.5 V power domains. DD15 ▄ Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down modes. ▄ Internal Voltage regulator supplies 1.5 V voltage source. -
Page 63: Figure 12. Power On Reset / Power Down Reset Waveform
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Power On Reset (POR) / Power Down Reset (PDR) The device has an integrated POR/PDR circuitry that allows proper operation starting from/down to 2.0 V. The device remains in Power-Down mode when V is below a specified threshold V without the need for an external reset circuit. -
Page 64: 1.5 V Power Domain
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 High Speed External Oscillator The High Speed External Oscillator, HSE, is located in the V power domain. The HSE crystal oscillator can be switched on or off using the HSEEN bit in the Global Clock Control Register (GCCR). -
Page 65: Table 12. Enter/Exit Power Saving Modes
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Sleep Mode By default, only the CPU clock will be stopped in the Sleep mode. Clearing the FMCEN or SRAMEN bit in the CKCU AHBCCR register to 0 will have the effect of stopping the Flash clock or SRAM clock after the system enters the Sleep mode. -
Page 66: Register Map
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Power-Down Mode The Power-Down mode is derived from the Deep-Sleep mode of the CPU together with the additional control bits LDOOFF and DMOSON. To enter the Power-Down mode, users can configure the registers shown in the preceding Mode-Entering table and execute the WFI or WFE instruction. -
Page 67: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Descriptions Power Control Status Register – PWRSR This register indicates power control status. Offset: 0x100 Reset value: 0x0000_0001 (Reset only by V domain power on reset) Reserved Type/Reset Reserved Type/Reset Reserved... -
Page 68: Power Control Register - Pwrcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Power Control Register – PWRCR This register provides power control bits for the different kinds of power saving modes. Offset: 0x104 Reset value: 0x0000_0000 (Reset only by V domain power on reset) - Page 69 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions WUPEN External WAKEUP Pin Enable 0: Disable WAKEUP pin function 1: Enable WAKEUP pin function The Software can set the WUPEN bit as 1 to enable the WAKEUP pin function before entering the power saving mode.
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Page 70: Vdd Power Domain Test Register - Pwrtest
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Power Domain Test Register – PWRTEST This register specifies a read-only value for the software to recognize whether V Power Domain is ready for access. Offset: 0x108 Reset value: 0x0000_0027 Reserved Type/Reset... - Page 71 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [21] LVDEWEN LVD Event Wakeup Enable 0: LVD event wakeup is disabled 1: LVD event wakeup is enabled Setting this bit to 1 will enable the LVD event wakeup function to wake up the system when a LVD condition occurs which result in the LVDF bit being asserted.
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Page 72: Clock Control Unit (Ckcu)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Clock Control Unit (CKCU) Introduction The Clock Control unit (CKCU) provides functions of high speed internal RC oscillator (HSI), High speed external crystal oscillator (HSE), Low speed internal RC oscillator (LSI), Low speed external crystal oscillator (LSE), Phase Lock Loop (PLL), HSE clock monitor, clock prescaler, clock multiplexer and clock gating. -
Page 73: Figure 13. Ckcu Block Diagram
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 CKIN HSI Auto Trimming Prescaler Divider CK_REF Controller CK_LSE 1 ~ 32 CKREFPRE CKREFEN PLLSRC 8 MHz PLLEN HSI RC STCLK (to SysTick) CK_PLL HSIEN SW[2:0] CK_GPIO GPIOAEN 4-16 MHz ( to GPIO port) -
Page 74: Function Descriptions
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Function Descriptions High Speed External Crystal Oscillator – HSE The high speed external 4 to 16 MHz crystal oscillator (HSE) produces a highly accurate clock source to the system clock. The related hardware configuration is shown in the following figure. -
Page 75: High Speed Internal Rc Oscillator - Hsi
The frequency accuracy of the high speed internal RC oscillator HSI can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by HOLTEK for ±2% accuracy at V = 3.3 V and T = 25°C. -
Page 76: Phase Locked Loop - Pll
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Auto Trimming HSI Block Diagram Fine-Trimming Write Register ATCEN Counter Auto Trimming Register Controller TMSEL External 1 kHz pin (CKIN) /1.024 kHz 32.768 kHz REFCLKSEL Fine-Trimming Factory Read Register Trimming Bits Fine [7:0]... -
Page 77: Table 15. Output Divider2 Value Mapping
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Frequency of the PLL output clock can be determined by the following formula: where NR = Ref divider = 2, NF1 = Feedback Divider 1 = 4, NF2 = Feedback Divider 2 = 1 ~ 16, NO1 = Output Divider 1 = 2, NO2 = Output Divider 2 = 1, 2, 4, or 8 Considering the duty cycle with 50%, both input frequency and output frequency is divided by 2. -
Page 78: Low Speed External Crystal Oscillator - Lse
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Low Speed External Crystal Oscillator – LSE The low speed external crystal or ceramic resonator oscillator with 32,768 Hz frequency produces a low power but highly accurate clock source for the circuits of Real-Time-Clock peripheral, Watchdog Timer or system clock. -
Page 79: System Clock (Ck_Sys) Selection
Cortex ® -M0+ MCU HT32F52243/HT32F52253 System Clock (CK_SYS) Selection After the system reset occurs, the default system clock source CK_SYS will be the high speed internal RC oscillator HSI. The CK_SYS may come from the HSI, HSE, LSE, LSI or PLL output clock and it can be switched from one clock source to another by configuring the System Clock Switch bits SW in the Global Clock Control Register GCCR. -
Page 80: Hse Clock Monitor
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 HSE Clock Monitor The HSE Clock Monitor function is enabled by the HSE Clock Monitor Enable bit CKMEN in the Global Clock Control Register GCCR. The HSE clock monitor function should be enabled after the HSE oscillator start-up delay and disabled when the HSE oscillator is stopped. -
Page 81: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Map The following table shows the CKCU register and reset value. Table 18. CKCU Register Map Register Offset Description Reset Value GCFGR 0x000 Global Clock Configuration Register 0x0000_0102 GCCR 0x004 Global Clock Control Register... -
Page 82: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Descriptions Global Clock Configuration Register – GCFGR This register specifies the clock source for PLL / USART / Watchdog Timer / CKOUT. Offset: 0x000 Reset value: 0x0000_0102 LPMOD Reserved Type/Reset 0 RO... -
Page 83: Global Clock Control Register - Gccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Global Clock Control Register – GCCR This register specifies the clock enable bits. Offset: 0x004 Reset value: 0x0000_0803 Reserved Type/Reset Reserved PSRCEN CKMEN Type/Reset 0 RW Reserved HSIEN HSEEN PLLEN HSEGAIN Type/Reset... -
Page 84: Global Clock Status Register - Gcsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [2:0] System Clock Switch 00x: CK_PLL clock out as system clock 010: CK_HSE as system clock 011: CK_HSI as system clock 110: CK_LSE as system clock 111: CK_LSI as system clock Other: CK_HSI as system clock Set and reset by software to select CK_SYS source. -
Page 85: Global Clock Interrupt Register - Gcir
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions PLLRDY PLL Clock Ready Flag 0: PLL is not ready 1: PLL is ready Set by hardware to indicate whether the PLL output is stable to be used. Global Clock Interrupt Register – GCIR This register specifies interrupt enable and flag bits. -
Page 86: Pll Configuration Register - Pllcfgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 PLL Configuration Register – PLLCFGR This register specifies the PLL configuration. Offset: 0x018 Reset value: 0x0000_0000 Reserved PFBD Type/Reset 0 RW 0 RW PFBD POTD Reserved Type/Reset 0 RW 0 RW Reserved... -
Page 87: Ahb Configuration Register - Ahbcfgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 AHB Configuration Register – AHBCFGR This register specifies the system clock frequency. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved AHBPRE Type/Reset 0 RW 0 RW Bits Field... -
Page 88: Ahb Clock Control Register - Ahbccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 AHB Clock Control Register – AHBCCR This register specifies the AHB clock enable control bits. Offset: 0x024 Reset value: 0x0000_0065 Reserved DIVEN Type/Reset Reserved PDEN PCEN PBEN PAEN Type/Reset 0 RW 0 RW... - Page 89 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions APBEN APB bridge Clock Enable 0: APB bridge clock is automatically disabled by hardware during Sleep mode 1: APB bridge clock is always enabled during Sleep mode Set and reset by software. User can set the APBEN bit to 0 to reduce the power consumption if the APB bridge is unused during Sleep mode.
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Page 90: Apb Configuration Register - Apbcfgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 APB Configuration Register – APBCFGR This register specifies the ADC conversion clock frequency. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved ADCDIV Type/Reset 0 RW 0 RW Reserved Type/Reset Reserved Type/Reset Bits... -
Page 91: Apb Clock Control Register 0 - Apbccr0
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 APB Clock Control Register 0 – APBCCR0 This register specifies the APB peripherals clock enable bits. Offset: 0x02C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTIEN AFIOEN UR3EN UR2EN UR1EN UR0EN USR1EN... -
Page 92: Apb Clock Control Register 1 - Apbccr1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions USR0EN USART0 Clock Enable 0: USART0 clock is disabled 1: USART0 clock is enabled Set and reset by software. SPI1EN SPI1 Clock Enable 0: SPI1 clock is disabled 1: SPI1 clock is enabled Set and reset by software. - Page 93 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [30] SCTM2EN SCTM2 Clock Enable 0: SCTM2 clock is disabled 1: SCTM2 clock is enabled Set and reset by software. [29] SCTM1EN SCTM1 Clock Enable 0: SCTM1 clock is disabled 1: SCTM1 clock is enabled Set and reset by software.
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Page 94: Clock Source Status Register - Ckst
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Clock Source Status Register – CKST This register specifies the clock source status. Offset: 0x034 Reset value: 0x0100_0003 Reserved HSIST Type/Reset 0 RO 0 RO Reserved HSEST Type/Reset 0 RO Reserved PLLST... -
Page 95: Apb Peripheral Clock Selection Register 0 - Apbpcsr0
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 APB Peripheral Clock Selection Register 0 – APBPCSR0 This register specifies the APB peripheral clock prescaler selection. Offset: 0x038 Reset value: 0x0000_0000 UR1PCLK UR0PCLK USR1PCLK USR0PCLK Type/Reset 0 RW 0 RW 0 RW... - Page 96 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [17:16] MCTMPCLK MCTM Peripheral Clock Selection 00: PCLK = CK_AHB 01: PCLK = CK_AHB / 2 10: PCLK = CK_AHB / 4 11: PCLK = CK_AHB / 8 PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock...
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Page 97: Apb Peripheral Clock Selection Register 1 - Apbpcsr1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 APB Peripheral Clock Selection Register 1 – APBPCSR1 This register specifies the APB peripheral clock prescaler selection. Offset: 0x03C Reset 0x0000_0000 value: SCTM3PCLK SCTM2PCLK SCTM1PCLK SCTM0PCLK Type/Reset RW 0 RW 0 RW... - Page 98 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [15:14] VDDRPCLK Domain Register Access Clock Selection 00: PCLK = CK_AHB / 4 01: PCLK = CK_AHB / 8 10: PCLK = CK_AHB / 16 11: PCLK = CK_AHB / 32 PCLK = Peripheral Clock;...
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Page 99: Hsi Control Register - Hsicr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 HSI Control Register – HSICR This register is used to control the frequency trimming of the HSI RC oscillation. Offset: 0x040 Reset value: 0xXXXX_0000 where X is undefined Reserved HSICOARSE Type/Reset X RO... -
Page 100: Hsi Auto Trimming Counter Register - Hsiatcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions TRIMEN Trimming Enable 0: HSI Trimming is disabled 1: HSI Trimming is enabled The bit enables the HSI RC oscillator trimming function by the ATC hardware or user program. -
Page 101: Mcu Debug Control Register - Mcudbgcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 MCU Debug Control Register – MCUDBGCR This register specifies the MCU debug control. Offset: 0x304 Reset value: 0x0000_0000 Reserved DBI2C2 DBUR3 DBUR2 DBSCTM3 DBSCTM2 Type/Reset 0 R/W 0 R/W 0 R/W 0 R/W... - Page 102 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [20] DBTRACE TRACESWO Debug Mode Enable 0 : Disable TRACESWO output 1 : Enable TRACESWO output Set and reset by software. [19] DBUR1 UART1 Debug Mode Enable 0: Same behavior as in normal mode 1: UART1 timeout is frozen when the core is halted Set and reset by software.
- Page 103 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions DBMCTM MCTM Debug Mode Enable 0: MCTM counter continues to count even if the core is halted 1: MCTM counter stops counting when the core is halted Set and reset by software.
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Page 104: Reset Control Unit (Rstcu)
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Reset Control Unit (RSTCU) Introduction The Reset Control Unit, RSTCU, has three kinds of reset, the power on reset, system reset and APB unit reset. The power on reset, known as a cold reset, resets the full system during a power up. -
Page 105: Functional Descriptions
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Functional Descriptions Power On Reset The Power on reset, POR, is generated by either an external reset or the internal reset generator. Both types have an internal filter to prevent glitches from causing erroneous reset operations. By referring to Figure 19, the POR15 active low signal will be de-asserted when the internal LDO voltage regulator is ready to provide 1.5 V power. -
Page 106: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Map The following table shows the RSTCU registers and reset values. Table 19. RSTCU Register Map Register Offset Description Reset Value RSTCU Base Address = 0x4008_8000 GRSR 0x100 Global Reset Status Register... -
Page 107: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Descriptions Global Reset Status Register – GRSR This register specifies a variety of reset status conditions. Offset: 0x100 Reset value: 0x0000_0008 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved PORSTF WDTRSTF EXTRSTF NVICRSTF... -
Page 108: Ahb Peripheral Reset Register - Ahbprstr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 AHB Peripheral Reset Register – AHBPRSTR This register specifies several AHB peripherals software reset control bits. Offset: 0x104 Reset value: 0x0000_0000 Reserved DIVRST Type/Reset Reserved Type/Reset Reserved PDRST PCRST PBRST PARST Type/Reset... -
Page 109: Apb Peripheral Reset Register 0 - Apbprstr0
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 APB Peripheral Reset Register 0 – APBPRSTR0 This register specifies several APB peripherals software reset control bits. Offset: 0x108 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTIRST AFIORST UR3RST UR2RST UR1RST UR0RST... -
Page 110: Apb Peripheral Reset Register 1 - Apbprstr1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions USR0RST USART0 Reset Control 0: No reset 1: Reset USART0 This bit is set by software and cleared to 0 by hardware automatically. SPI1RST SPI1 Reset Control 0: No reset 1: Reset SPI1 This bit is set by software and cleared to 0 by hardware automatically. - Page 111 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [31] SCTM3RST SCTM3 Reset Control 0: No reset 1: Reset SCTM3 This bit is set by software and cleared to 0 by hardware automatically. [30] SCTM2RST SCTM2 Reset Control...
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Page 112: General Purpose I/O (Gpio)
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 General Purpose I/O (GPIO) Introduction There are up to 51 General Purpose I/O port, GPIO, named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15 and PD0 ~ PD3 for the devices to implement the logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirement of specific applications. -
Page 113: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Features ▄ Input/output direction control ▄ Schmitt Trigger Input function enable control ▄ Input weak pull-up / pull-down control ▄ Output push-pull / open drain enable control ▄ Output set / reset control ▄... -
Page 114: Table 20. Afio, Gpio And Io Pad Control Signal True Table
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 PxCFGn Input DMUX Output AFIO Control IOPAD AFIO ADEN PxDOUTn PxDINn PxRSTn PxDVn PxINENn PxSETn PxODn PxDIRn PxPDn PxPUn GPIO Figure 21. AFIO/GPIO Control Signal PxDINn/PxDOUTn (x = A ~ D): Data Input/Data Output... -
Page 115: Gpio Locking Mechanism
Cortex ® -M0+ MCU HT32F52243/HT32F52253 GPIO Locking Mechanism The GPIO also offers a lock function to lock the port until a reset event occurs. The PxLOCKR (x = A ~ D) registers are used to lock the port x and lock control options. The value 0x5FA0 is... -
Page 116: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Offset Description Reset Value PCDOUTR 0x020 Port C Data Output Register 0x0000_0000 PCSRR 0x024 Port C Output Set and Reset Control Register 0x0000_0000 PCRR 0x028 Port C Output Reset Control Register... -
Page 117: Port A Input Function Enable Control Register - Painer
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port A Input Function Enable Control Register – PAINER This register is used to enable or disable the GPIO Port A input function. Offset: 0x004 Reset value: 0x0000_0200 Reserved Type/Reset Reserved Type/Reset... -
Page 118: Port A Pull-Up Selection Register - Papur
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port A Pull-Up Selection Register – PAPUR This register is used to enable or disable the GPIO Port A pull-up function. Offset: 0x008 Reset value: 0x0000_3200 Reserved Type/Reset Reserved Type/Reset PAPU Type/Reset... -
Page 119: Port A Pull-Down Selection Register - Papdr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port A Pull-Down Selection Register – PAPDR This register is used to enable or disable the GPIO Port A pull-down function. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PAPD Type/Reset... -
Page 120: Port A Open Drain Selection Register - Paodr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port A Open Drain Selection Register – PAODR This register is used to enable or disable the GPIO Port A open drain function. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset... -
Page 121: Port A Output Current Drive Selection Register - Padrvr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port A Output Current Drive Selection Register – PADRVR This register specifies the GPIO Port A output driving current. Offset: 0x014 Reset value: 0x0000_0000 PADV15 PADV14 PADV13 PADV12 Type/Reset 0 RW 0 RW... -
Page 122: Port A Lock Register - Palockr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port A Lock Register – PALOCKR This register specifies the GPIO Port A lock configuration. Offset: 0x018 Reset value: 0x0000_0000 PALKEY Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW... -
Page 123: Port A Data Input Register - Padinr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port A Data Input Register – PADINR This register specifies the GPIO Port A input data. Offset: 0x01C Reset value: 0x0000_3200 Reserved Type/Reset Reserved Type/Reset PADIN Type/Reset 0 RO 0 RO 1 RO... -
Page 124: Port A Output Set/Reset Control Register - Pasrr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port A Output Set/Reset Control Register – PASRR This register is used to set or reset the corresponding bit of the GPIO Port A output data. Offset: 0x024 Reset value: 0x0000_0000 PARST... -
Page 125: Port A Output Reset Register - Parr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port A Output Reset Register – PARR This register is used to reset the corresponding bit of the GPIO Port A output data. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset... -
Page 126: Port B Input Function Enable Control Register - Pbiner
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port B Input Function Enable Control Register – PBINER This register is used to enable or disable the GPIO Port B input function. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset... -
Page 127: Port B Pull-Up Selection Register - Pbpur
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port B Pull-Up Selection Register – PBPUR This register is used to enable or disable the GPIO Port B pull-up function. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PBPU Type/Reset... -
Page 128: Port B Pull-Down Selection Register - Pbpdr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port B Pull-Down Selection Register – PBPDR This register is used to enable or disable the GPIO Port B pull-down function. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PBPD Type/Reset... -
Page 129: Port B Open Drain Selection Register - Pbodr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port B Open Drain Selection Register – PBODR This register is used to enable or disable the GPIO Port B open drain function. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset... -
Page 130: Port B Output Current Drive Selection Register - Pbdrvr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port B Output Current Drive Selection Register – PBDRVR This register specifies the GPIO Port B output driving current. Offset: 0x014 Reset value: 0x0000_0000 PBDV15 PBDV14 PBDV13 PBDV12 Type/Reset 0 RW 0 RW... -
Page 131: Port B Lock Register - Pblockr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port B Lock Register – PBLOCKR This register specifies the GPIO Port B lock configuration. Offset: 0x018 Reset value: 0x0000_0000 PBLKEY Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW... -
Page 132: Port B Data Input Register - Pbdinr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port B Data Input Register – PBDINR This register specifies the GPIO Port B input data. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PBDIN Type/Reset 0 RO 0 RO 0 RO... -
Page 133: Port B Output Set/Reset Control Register - Pbsrr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port B Output Set/Reset Control Register – PBSRR This register is used to set or reset the corresponding bit of the GPIO Port B output data. Offset: 0x024 Reset value: 0x0000_0000 PBRST... -
Page 134: Port B Output Reset Register - Pbrr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port B Output Reset Register – PBRR This register is used to reset the corresponding bit of the GPIO Port B output data. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset... -
Page 135: Port C Input Function Enable Control Register - Pciner
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port C Input Function Enable Control Register – PCINER This register is used to enable or disable the GPIO Port C input function. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset... -
Page 136: Port C Pull-Up Selection Register - Pcpur
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port C Pull-Up Selection Register – PCPUR This register is used to enable or disable the GPIO Port C pull-up function. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PCPU Type/Reset... -
Page 137: Port C Pull-Down Selection Register - Pcpdr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port C Pull-Down Selection Register – PCPDR This register is used to enable or disable the GPIO Port C pull-down function. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PCPD Type/Reset... -
Page 138: Port C Open Drain Selection Register - Pcodr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port C Open Drain Selection Register – PCODR This register is used to enable or disable the GPIO Port C open drain function. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset... -
Page 139: Port C Output Current Drive Selection Register - Pcdrvr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port C Output Current Drive Selection Register – PCDRVR This register specifies the GPIO Port C output driving current. Offset: 0x014 Reset value: 0x0000_0000 PCDV15 PCDV14 PCDV13 PCDV12 Type/Reset 0 RW 0 RW... -
Page 140: Port C Lock Register - Pclockr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port C Lock Register – PCLOCKR This register specifies the GPIO Port C lock configuration. Offset: 0x018 Reset value: 0x0000_0000 PCLKEY Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW... -
Page 141: Port C Data Input Register - Pcdinr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port C Data Input Register – PCDINR This register specifies the GPIO Port C input data. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PCDIN Type/Reset 0 RO 0 RO 0 RO... -
Page 142: Port C Output Set/Reset Control Register - Pcsrr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port C Output Set/Reset Control Register – PCSRR This register is used to set or reset the corresponding bit of the GPIO Port C output data. Offset: 0x024 Reset value: 0x0000_0000 PCRST... -
Page 143: Port C Output Reset Register - Pcrr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port C Output Reset Register – PCRR This register is used to reset the corresponding bit of the GPIO Port C output data. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset... -
Page 144: Port D Input Function Enable Control Register - Pdiner
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port D Input Function Enable Control Register – PDINER This register is used to enable or disable the GPIO Port D input function. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset... -
Page 145: Port D Pull-Up Selection Register - Pdpur
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port D Pull-Up Selection Register – PDPUR This register is used to enable or disable the GPIO Port D pull-up function. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset... -
Page 146: Port D Pull-Down Selection Register - Pdpdr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port D Pull-Down Selection Register – PDPDR This register is used to enable or disable the GPIO Port D pull-down function. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset... -
Page 147: Port D Open Drain Selection Register - Pdodr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port D Open Drain Selection Register – PDODR This register is used to enable or disable the GPIO Port D open drain function. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset... -
Page 148: Port D Output Current Drive Selection Register - Pddrvr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port D Output Current Drive Selection Register – PDDRVR This register specifies the GPIO Port D output driving current. Offset: 0x014 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset PDDV3 PDDV2... -
Page 149: Port D Lock Register - Pdlockr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port D Lock Register – PDLOCKR This register specifies the GPIO Port D lock configuration. Offset: 0x018 Reset value: 0x0000_0000 PDLKEY Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW... -
Page 150: Port D Data Input Register - Pddinr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port D Data Input Register – PDDINR This register specifies the GPIO Port D input data. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved PDDIN Type/Reset 0 RO... -
Page 151: Port D Output Set/Reset Control Register - Pdsrr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port D Output Set/Reset Control Register – PDSRR This register is used to set or reset the corresponding bit of the GPIO Port D output data. Offset: 0x024 Reset value: 0x0000_0000 Reserved... -
Page 152: Port D Output Reset Register - Pdrr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Port D Output Reset Register – PDRR This register is used to reset the corresponding bit of the GPIO Port D output data. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset... -
Page 153: Alternate Function Input/Output Control Unit (Afio)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Alternate Function Input/Output Control Unit (AFIO) Introduction In order to expand the flexibility of the GPIO or the usage of peripheral functions, each IO pin can be configured to have up to sixteen different functions such as GPIO or IP functions by setting the GPxCFGLR or GPxCFGHR register where x is the different port name. -
Page 154: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Features ▄ APB slave interface for register access ▄ EXTI source selection ▄ Configurable pin function for each GPIO, up to sixteen alternative functions on each pin ▄ AFIO lock mechanism Functional Descriptions External Interrupt Pin Selection The GPIO pins are connected to the 16 EXTI lines as shown in the accompanying figure. -
Page 155: Alternate Function
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Alternate Function Up to sixteen alternative functions can be chosen for each I/O pad by setting the PxCFGn [3:0] field in the GPxCFGLR or GPxCFGHR (n = 0~15, x = A~ D) registers. If the pin is selected as unavailable item which is noted as "N/A"... -
Page 156: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Descriptions EXTI Source Selection Register 0 – ESSR0 This register specifies the IO selection of EXTI0 ~ EXTI7. Offset: 0x000 Reset value: 0x0000_0000 EXTI7PIN EXTI6PIN Type/Reset 0 RW 0 RW 0 RW... -
Page 157: Exti Source Selection Register 1 - Essr1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 EXTI Source Selection Register 1 – ESSR1 This register specifies the IO selection of EXTI8 ~ EXTI15. Offset: 0x004 Reset value: 0x0000_0000 EXTI15PIN EXTI14PIN Type/Reset 0 RW 0 RW 0 RW 0 RW... -
Page 158: Gpio Port X Configuration Low Register - Gpxcfglr, X = A, B, C, D
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 GPIO Port x Configuration Low Register – GPxCFGLR, x = A, B, C, D This low register specifies the alternate function of GPIO Port x. x = A, B, C, D Offset: 0x020, 0x028, 0x030, 0x038... -
Page 159: Gpio Port X Configuration High Register - Gpxcfghr, X = A, B, C, D
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 GPIO Port x Configuration High Register – GPxCFGHR, x = A, B, C, D This high register specifies the alternate function of GPIO Port x. x = A, B, C, D Offset: 0x024, 0x02C, 0x034, 0x03C... -
Page 160: Nested Vectored Interrupt Controller (Nvic)
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Nested Vectored Interrupt Controller (NVIC) Introduction In order to reduce the latency and increase the interrupt processing efficiency, a tightly coupled integrated section, which is named as Nested Vectored Interrupt Controller (NVIC) is provided by the Cortex -M0+. -
Page 161: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Interrupt Exception Exception Vector Priority Description Number Number type Address SCTM1 Configurable 0x078 SCTM1 global interrupt SCTM2 Configurable 0x07C SCTM2 global interrupt SCTM3 Configurable 0x080 SCTM3 global interrupt BFTM0 Configurable 0x084 BFTM0 global interrupt... -
Page 162: Function Descriptions
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Function Descriptions SysTick Calibration The SysTick Calibration Value Register (SCALIB) is provided by the NVIC to give a reference time base of 1 ms for the RTOS tick timer or other purpose. The TENMS field in the SCALIB register has a fixed value of 5000 which is the counter reload value to indicate 1 ms when the clock source comes from the SysTick reference input clock STCLK with a frequency of 5 MHz (40 MHz divide by 8). -
Page 163: External Interrupt / Event Controller (Exti)
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 External Interrupt / Event Controller (EXTI) Introduction The External Interrupt/Event Controller, EXTI, comprises 16 edge detectors which can generate a wake-up event or interrupt requests independently. In interrupt mode there are five trigger types... -
Page 164: Function Descriptions
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Function Descriptions Wakeup Event Management In order to wake up the system from the power saving mode, the EXTI controller provides a function which can monitor external events and send them to the CPU core and the Clock Control Unit, CKCU. -
Page 165: External Interrupt/Event Line Mapping
Cortex ® -M0+ MCU HT32F52243/HT32F52253 External Interrupt/Event Line Mapping All GPIO pins can be selected as EXTI trigger sources by configuring the EXTInPIN [3:0] field in the AFIO ESSRn (n = 0 ~ 1) register to trigger an interrupt or event. Refer to the AFIO section for more details. -
Page 166: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Map The following table shows the EXTI registers and reset values. Table 26. EXTI Register Map Register Offset Description Reset Value EXTICFGR0 0x000 EXTI Interrupt 0 Configuration Register 0x0000_0000 EXTICFGR1 0x004... -
Page 167: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Descriptions EXTI Interrupt Configuration Register n – EXTICFGRn, n = 0 ~ 15 This register is used to specify the debounce function and select the trigger type. Offset: 0x000 (0) ~ 0x03C (15) -
Page 168: Exti Interrupt Control Register - Exticr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 EXTI Interrupt Control Register – EXTICR This register is used to control the EXTI interrupt. Offset: 0x040 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15EN EXTI14EN EXTI13EN EXTI12EN EXTI11EN EXTI10EN EXTI9EN EXTI8EN... -
Page 169: Exti Interrupt Edge Flag Register - Extiedgeflgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR This register is used to indicate if an EXTI edge has been detected. Offset: 0x044 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15EDF EXTI14EDF EXTI13EDF EXTI12EDF EXTI11EDF EXTI10EDF EXTI9EDF EXTI8EDF... -
Page 170: Exti Interrupt Edge Status Register - Extiedgesr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 EXTI Interrupt Edge Status Register – EXTIEDGESR This register indicates the polarity of a detected EXTI edge. Offset: 0x048 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15EDS EXTI14EDS EXTI13EDS EXTI12EDS EXTI11EDS EXTI10EDS EXTI9EDS EXTI8EDS... -
Page 171: Exti Interrupt Wakeup Control Register - Extiwakupcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR This register is used to control the EXTI interrupt and wakeup function. Offset: 0x050 Reset value: 0x0000_0000 EVWUPIEN Reserved Type/Reset Reserved Type/Reset EXTI15WEN EXTI14WEN EXTI13WEN EXTI12WEN EXTI11WEN EXTI10WEN EXTI9WEN EXTI8WEN... -
Page 172: Exti Interrupt Wakeup Polarity Register - Extiwakuppolr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR This register is used to select the EXTI line interrupt wakeup polarity. Offset: 0x054 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15WPOL EXTI14WPOL EXTI13WPOL EXTI12WPOL EXTI11WPOL EXTI10WPOL EXTI9WPOL EXTI8WPOL... -
Page 173: Analog To Digital Converter (Adc)
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Analog to Digital Converter (ADC) Introduction A 12-bit multi-channel Analog to Digital Converter is integrated in the device. There are a total of 14 multiplexed channels including 12 external channels on which the external analog signal can be supplied and 2 internal channels. -
Page 174: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Features ▄ 12-bit SAR ADC engine ▄ Up to 1 MSPS conversion rate ▄ 12 external analog input channels ▄ 2 internal analog input channels for reference voltage detection ▄ Programmable sampling time for conversion channel ▄... -
Page 175: Function Descriptions
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Function Descriptions ADC Clock Setup The ADC clock, CK_ADC is provided by the Clock Controller which is synchronous and divided by with the AHB clock known as HCLK. Refer to the Clock Control Unit chapter for more details. -
Page 176: Figure 28. One Shot Conversion Mode
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Conversion (ex: Sequence Length=8) Cycle Cycle Start of Conversion Single sample End of Conversion Cycle End of Conversion Figure 28. One Shot Conversion Mode Continuous Conversion Mode In the Continuous Conversion Mode, repeated conversion cycle will start automatically without requiring additional A/D start trigger signals after a channels group conversion has completed. - Page 177 ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Discontinuous Conversion Mode The A/D converter will operate in the Discontinuous Conversion Mode for channels group when the A/D conversion mode bit field ADMODE [1:0] in the ADCCONV register is set to 0x3. The group to be converted can have up to 8 channels and can be arranged in a specific sequence by configuring the ADCLSTn registers where n ranges from 0 to 1.
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Page 178: Start Conversion On External Event
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Discontinuous Conversion Mode (ex: Sequence Length=8, Subgroup Length=3 ) Cycle Cycle Subgroup 0 Subgroup 1 Subgroup 2 Subgroup 0 Start of Conversion Single sample End of Conversion Subgroup End of Conversion Cycle End of Conversion Figure 30. -
Page 179: Sampling Time Setting
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Sampling Time Setting The conversion channel sampling time can be programmed according to the input resistance of the input voltage source. This sampling time must be enough for the input voltage source to charge the internal sample and hold capacitor in the A/D converter to the input voltage level. -
Page 180: Interrupts
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Interrupts When an A/D conversion is completed, an End of Conversion EOC event will occur. There are three kinds of EOC events which are known as single sample EOC, subgroup EOC and cycle EOC for A/D conversion. -
Page 181: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Map The following table shows the A/D Converter registers and reset values. Table 28. A/D Converter Register Map Register Offset Description Reset Value ADCCR 0x000 ADC Conversion Control Register 0x0000_0000 ADCLST0... -
Page 182: Register Descriptions
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Descriptions ADC Conversion Control Register – ADCCR This register specifies the mode setting, sequence length, and subgroup length of the ADC conversion mode. Note that once the content of ADCCR is changed, the conversion in progress will be aborted and the A/D converter will return to idle state. -
Page 183: Adc Conversion List Register 0 - Adclst0
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [1:0] ADMODE ADC Conversion Mode ADMODE [1:0] Mode Descriptions After a start trigger, the conversion will be One shot mode executed on the specific channels for the whole conversion sequence once. -
Page 184: Adc Conversion List Register 1 - Adclst1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [28:24] ADSEQ3 ADC Conversion Sequence Select 3 Select the ADC input channel for the 3rd ADC conversion sequence. 0x00: ADC_IN0 0x01: ADC_IN1 0x02: ADC_IN2 0x03: ADC_IN3 0x04: ADC_IN4 0x05: ADC_IN5... -
Page 185: Adc Input Sampling Time Register - Adcstr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [28:24] ADSEQ7 ADC Conversion Sequence Select 7 Select the ADC input channel for the 7th ADC conversion sequence. 0x00: ADC_IN0 0x01: ADC_IN1 0x02: ADC_IN2 0x03: ADC_IN3 0x04: ADC_IN4 0x05: ADC_IN5... -
Page 186: Adc Conversion Data Register Y - Adcdry, Y = 0 ~ 7
Cortex ® -M0+ MCU HT32F52243/HT32F52253 ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7 This register is used to store the conversion data of the conversion sequence order No.y which is specified by the ADSEQy field in the ADCLSTn (n = 0 ~ 1) registers. -
Page 187: Adc Trigger Control Register - Adctcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 ADC Trigger Control Register – ADCTCR This register contains the ADC start conversion trigger enable bits. Offset: 0x070 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved BFTM ADEXTI ADSW Type/Reset... -
Page 188: Adc Trigger Source Register - Adctsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 ADC Trigger Source Register – ADCTSR This register contains the trigger source selection and the software trigger bit of the conversion. Offset: 0x074 Reset value: 0x0000_0000 Reserved Type/Reset 0 RW 0 RW... -
Page 189: Adc Watchdog Control Register - Adcwcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 ADC Watchdog Control Register – ADCWCR This register provides the control bits and status of the ADC watchdog function. Offset: 0x078 Reset value: 0x0000_0000 Reserved ADUCH Type/Reset 0 RO 0 RO 0 RO... -
Page 190: Adc Watchdog Threshold Register - Adctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions ADWUE ADC Watchdog Upper Threshold Enable Bit 0: Disable upper threshold monitor function 1: Enable upper threshold monitor function ADWLE ADC Watchdog Lower Threshold Enable Bit 0: Disable lower threshold monitor function 1: Enable lower threshold monitor function ADC Watchdog Threshold Register –... -
Page 191: Adc Interrupt Enable Register - Adcier
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 ADC Interrupt Enable Register – ADCIER This register contains the ADC interrupt enable bits. Offset: 0x080 Reset value: 0x0000_0000 Reserved ADIEO Type/Reset Reserved ADIEU ADIEL Type/Reset 0 RW Reserved Type/Reset Reserved ADIEC... -
Page 192: Adc Interrupt Raw Status Register - Adciraw
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 ADC Interrupt Raw Status Register – ADCIRAW This register contains the ADC interrupt raw status bits. Offset: 0x084 Reset value: 0x0000_0000 Reserved ADIRAWO Type/Reset Reserved ADIRAWU ADIRAWL Type/Reset 0 RO Reserved Type/Reset... -
Page 193: Adc Interrupt Status Register - Adcisr
Cortex ® -M0+ MCU HT32F52243/HT32F52253 ADC Interrupt Status Register – ADCISR This register contains the ADC interrupt masked status bits. The corresponding interrupt status will be set to 1 if the associated interrupt event occurs and the related enable bit is set to 1. -
Page 194: Adc Interrupt Clear Register - Adciclr
Cortex ® -M0+ MCU HT32F52243/HT32F52253 ADC Interrupt Clear Register – ADCICLR This register provides the clear bits used to clear the interrupt raw and masked status of the ADC. These bits are set to 1 by software to clear the interrupt status and automatically cleared to 0 by hardware after being set to 1. -
Page 195: General-Purpose Timer (Gptm)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 General-Purpose Timer (GPTM) Introduction The General-Purpose Timer consists of one 16-bit up/down-counter, four 16-bit Capture/ Compare Registers (CCRs), one 16-bit Counter-Reload Register (CRR) and several control/status registers. It can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as single pulse generation or PWM output. -
Page 196: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Features ▄ 16-bit up/down auto-reload counter ▄ 16-bit programmable prescaler that allows division of the counter clock frequency by any factor between 1 and 65536 ▄ Up to 4 independent channels for: ●... -
Page 197: Figure 32. Up-Counting Example
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 CK_PSC CNT_EN CK_CNT CNTR CRR Shadow Register PSCR PSCR Shadow Register PSC_CNT Counter Overflow Update Event Flag Write a new value Software clearing Update the new value Figure 32. Up-counting Example Down-Counting In this mode the counter counts continuously from the counter-reload value, which is defined in the CRR register, to 0 in a count-down direction. -
Page 198: Clock Controller
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Center-Aligned Counting In the center-aligned counting mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The Timer module generates an overflow event when the counter counts to the counter-reload value in the up-counting mode and generates an underflow event when the counter counts to 0 in the down-counting mode. -
Page 199: Trigger Controller
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 ▄ STIED: The counter prescaler can count during each rising edge of the STI signal. This mode can be selected by setting the SMSEL field to 0x7 in the MDCFR register. Here the counter will act as an event counter. -
Page 200: Figure 36. Trigger Control Block
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Trigger Controller Block = Edge Trigger Mux + Level Trigger Mux Internal Trigger Input ITI0 ITI0ED ITI1 Edge ITI2 ITI1ED Detection ITI2ED CLKIN Edge Trigger = Internal (ITIx) + Channel input (TIn) -
Page 201: Slave Controller
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Slave Controller The GPTM can be synchronized with an external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which is selected by the SMSEL field in the MDCFR register. -
Page 202: Figure 39. Gptm In Pause Mode
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Pause Mode In the Pause Mode, the selected STI input signal level is used to control the counter start/stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level, here the counter will maintain its present value and will not be reset. -
Page 203: Master Controller
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Master Controller The GPTMs and MCTMs can be linked together internally for timer synchronization or chaining. When one GPTM is configured to be in the Master Mode, the GPTM Master Controller will generate a Master Trigger Output (MTO) signal which includes a reset, a start, a stop signal or a clock source which is selected by the MMSEL field in the MDCFR register to trigger or drive another GPTM or MCTM, if exists, which is configured in the Slave Mode. -
Page 204: Figure 43. Capture/Compare Block Diagram
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 APB Bus Interface CHxCCR CHxPSC (Preload Register) Write CHxCCR Capture Compare Capture Transfer Compare Transfer Controller Controller Update Event Read CHxCCR CHxCCR (Shadow Register) CHxCCS CHxCCS Capture CHxCCG CHxPRE CHxCCR CHxE TM_CNT Figure 43. -
Page 205: Figure 45. Pwm Pulse Width Measurement Example
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Pulse Width Measurement The input capture mode can be also used for pulse width measurement from signals on the GT_CHx pins, TIx. The following example shows how to configure the GPTM operated in the input capture mode to measure the high pulse width and the input period on the GT_CH0 pin using channel 0 and channel 1. -
Page 206: Input Stage
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Input Stage The input stage consists of a digital filter, a channel polarity selection, edge detection and a channel prescaler. The channel 0 input signal (TI0) can be chosen to come from the GT_CH0 signal or the Excusive-OR function of the GT_CH0, GT_CH1 and GT_CH2 signals. -
Page 207: Quadrature Decoder
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Digital Filter The digital filters are embedded in the input stage for the GT_CH0 ~ GT_CH3 pins respectively. The digital filter in the GPTM is an N-event counter where N refers to how many valid transitions are necessary to output a filtered signal. -
Page 208: Table 29. Counting Direction And Encoding Signals
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 TRCED TI0SRC CLKIN Edge Detection GT_CH0 TI0BED TI0XOR GT_CH1 Edge GT_CH2 Detection CH0CCS CLKIN Edge TI0S0 TI0S0ED TI0FP TI0FN Detection Filter sampling CH0PSC CH0PRESCALER CH0P CH0CAP Event TI0F Edge TI1S0ED TI1S0 CH0PSC... -
Page 209: Output Stage
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Quadrature Decoder Counting on Down Both TI0 & TI1 (CH0P = 0, CH1P = 0) Figure 50. Both TI0 and TI1 Quadrature Decoder Counting Output Stage The GPTM has four channels for compare match, single pulse or PWM output function. The channel output GT_CHxO is controlled by the CHxOM, CHxP and CHxE bits in the corresponding CHxOCFR, CHPOLR and CHCTR registers. -
Page 210: Table 30. Compare Match Output Setup
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel Output Reference Signal When the GPTM is used in the compare match output mode, the CHxOREF signal (Channel x Output Reference signal) is defined by the CHxOM bit setup. The CHxOREF signal has several types of output function which defines what happens to the output when the counter value matches the contents of the CHxCCR register. -
Page 211: Figure 53. Toggle Mode Channel Output Reference Signal (Chxpre = 1)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Counter Value CHxOM=0x03, CHxPRE=1 (Output toggle, preload enable) CHxCCR (New value 2) CHxCCR (New value 3) CHxCCR (New value 1) CHxCCR Time Update CHxCCR value CHxOREF (Update Event) Figure 53. Toggle Mode Channel Output Reference Signal (CHxPRE = 1) -
Page 212: Figure 55. Pwm Mode Channel Output Reference Signal And Counter In Down-Counting Mode
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Counter Value Counter Value CHxCCR CHxCCR CHxOM = 0x06 100% CHxOREF CHxOREF CHxCCIF CHxCCIF CHxOM = 0x07 CHxOREF Figure 55. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode CRR = 5... -
Page 213: Update Management
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Update Management The Update event is used to update the CRR, the PSCR, the CHxACR and the CHxCCR values from the actual registers to the corresponding shadow registers. An update event occurs when the counter overflows or underflows, the software update control bit is triggered or an update event from the slave controller is generated. -
Page 214: Figure 58. Single Pulse Mode
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Counter Value CHxCCR Counter Counter stopped reinitialized and held Time TME bit Trigger by STI Cleared by S/W Cleared by Trigger by S/W Update Event CHxOREF delay delay (PWM1) CHxIMAE=0 delay delay... -
Page 215: Asymmetric Pwm Mode
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Counter Value CKDIV = 0 Up-Counting Mode CHxCCR Time CK_CNT ITIx Counter Start Time CHxIMAE CHxOREF (PWM1) Minimum delay (PWM2) Figure 59. Immediate Active Mode Minimum Delay Asymmetric PWM Mode Asymmetric PWM mode allows two center-aligned PWM signals to be generated with a programmable phase shift. -
Page 216: Timer Interconnection
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 CNTR CRR = 8 PWM center align mode CRR = 8 CCR = 3, ACR = X CCR = 3 CHxOREF PWM center align mode CRR = 8 CCR = 5, ACR = X... -
Page 217: Figure 61. Pausing Mctm Using The Gptm Ch0Oref Signal
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Master GPTM CLKIN GPTM CH0OREF GPTM CNTR Slave MCTM MCTM CNTR MCTM TEVIF Software clearing Figure 61. Pausing MCTM using the GPTM CH0OREF Signal Using one timer to trigger another timer start counting ▄... -
Page 218: Figure 63. Trigger Gptm And Mctm With The Gptm Ch0 Input
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Starting two timers synchronously in response to an external trigger ▄ Configure GPTM to operate in the master mode to send its enable signal as a trigger output (MMSEL = 0x01). ▄... -
Page 219: Trigger Adc Start
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Trigger ADC Start To interconnect to the Analog-to-Digital Converter, the GPTM can output the MTO signal or the channel compare match output signal CHxOREF (x = 0 ~ 3) to be used as an Analog-to-Digital Converter input trigger signal. -
Page 220: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Map The following table shows the GPTM registers and reset values. Table 31. GPTM Register Map Register Offset Description Reset Value CNTCFR 0x000 Timer Counter Configuration Register 0x0000_0000 MDCFR 0x004 Timer Mode Configuration Register... -
Page 221: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Descriptions Timer Counter Configuration Register – CNTCFR This register specifies the GPTM counter configuration. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CMSEL Type/Reset 0 RW Reserved CKDIV Type/Reset 0 RW... -
Page 222: Timer Mode Configuration Register - Mdcfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions UEVDIS Update event Disable control 0: Enable the update event request by one of following events: - Counter overflow/underflow - Setting the UEVG bit - Update generation through the slave mode... - Page 223 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [18:16] MMSEL Master Mode Selection Master mode selection is used to select the MTO signal source which is used to synchronize the other slave timer. MMSEL [2:0] Mode Descriptions...
- Page 224 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [10:8] SMSEL Slave Mode Selection SMSEL [2:0] Mode Descriptions The prescaler is clocked directly by the Disable mode internal clock. The counter uses the clock pulse generated from the interaction between the TI0 and Quadrature TI1 signals to drive the counter prescaler.
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Page 225: Timer Trigger Configuration Register - Trcfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Timer Trigger Configuration Register – TRCFR This register specifies the trigger source selection of GPTM. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved TRSEL Type/Reset 0 RW 0 RW... -
Page 226: Timer Control Register - Ctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Timer Control Register – CTR This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE) and Channel PDMA selection bit (CHCCDS). Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved... -
Page 227: Channel 0 Input Configuration Register - Ch0Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 0 Input Configuration Register – CH0ICFR This register specifies the channel 0 input mode configuration. Offset: 0x020 Reset value: 0x0000_0000 TI0SRC Reserved Type/Reset Reserved CH0PSC CH0CCS Type/Reset 0 RW 0 RW... - Page 228 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [3:0] TI0F Channel 0 Input Source TI0 Filter Setting These bits define the frequency divided ratio used to sample the TI0 signal. The Digital filter in the GPTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
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Page 229: Channel 1 Input Configuration Register - Ch1Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 1 Input Configuration Register – CH1ICFR This register specifies the channel 1 input mode configuration. Offset: 0x024 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CH1PSC CH1CCS Type/Reset 0 RW 0 RW 0 RW... - Page 230 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [3:0] TI1F Channel 1 Input Source TI1 Filter Setting These bits define the frequency divided ratio used to sample the TI1 signal. The Digital filter in the GPTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
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Page 231: Channel 2 Input Configuration Register - Ch2Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 2 Input Configuration Register – CH2ICFR This register specifies the channel 2 input mode configuration. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CH2PSC CH2CCS Type/Reset 0 RW 0 RW 0 RW... - Page 232 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [3:0] TI2F Channel 2 Input Source TI2 Filter Setting These bits define the frequency divided ratio used to sample the TI2 signal. The Digital filter in the GPTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
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Page 233: Channel 3 Input Configuration Register - Ch3Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 3 Input Configuration Register – CH3ICFR This register specifies the channel 3 input mode configuration. Offset: 0x02C Reset value: 0x0000_0000 Reserved Type/Reset Reserved CH3PSC CH3CCS Type/Reset 0 RW 0 RW 0 RW... - Page 234 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [3:0] TI3F Channel 3 Input Source TI3 Filter Setting These bits define the frequency divided ratio used to sample the TI3 signal. The Digital filter in the GPTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
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Page 235: Channel 0 Output Configuration Register - Ch0Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 0 Output Configuration Register – CH0OCFR This register specifies the channel 0 output mode configuration. Offset: 0x040 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH0OM[3] Type/Reset Reserved CH0IMAE CH0PRE Reserved... - Page 236 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [8][2:0] CH0OM[3:0] Channel 0 Output Mode Setting These bits define the functional types of the output reference signal CH0OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
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Page 237: Channel 1 Output Configuration Register - Ch1Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 1 Output Configuration Register – CH1OCFR This register specifies the channel 1 output mode configuration. Offset: 0x044 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH1OM[3] Type/Reset Reserved CH1IMAE CH1PRE Reserved... - Page 238 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [8][2:0] CH1OM[3:0] Channel 1 Output Mode Setting These bits define the functional types of the output reference signal CH1OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
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Page 239: Channel 2 Output Configuration Register - Ch2Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 2 Output Configuration Register – CH2OCFR This register specifies the channel 2 output mode configuration. Offset: 0x048 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH2OM[3] Type/Reset Reserved CH2IMAE CH2PRE Reserved... - Page 240 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [8][2:0] CH2OM[3:0] Channel 2 Output Mode Setting These bits define the functional types of the output reference signal CH2OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
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Page 241: Channel 3 Output Configuration Register - Ch3Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 3 Output Configuration Register – CH3OCFR This register specifies the channel 3 output mode configuration. Offset: 0x04C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH3OM[3] Type/Reset Reserved CH3IMAE CH3PRE Reserved... - Page 242 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [8][2:0] CH3OM[3:0] Channel 3 Output Mode Setting These bits define the functional types of the output reference signal CH3OREF 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
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Page 243: Channel Control Register - Chctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel Control Register – CHCTR This register contains the channel capture input or compare output function enable control bits. Offset: 0x050 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3E... -
Page 244: Channel Polarity Configuration Register - Chpolr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel Polarity Configuration Register – CHPOLR This register contains the channel capture input or compare output polarity control. Offset: 0x054 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3P Reserved... -
Page 245: Timer Pdma/Interrupt Control Register - Dictr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Timer PDMA/Interrupt Control Register – DICTR This register contains the timer PDMA and interrupt enable control bits. Offset: 0x074 Reset value: 0x0000_0000 Reserved TEVDE Reserved UEVDE Type/Reset Reserved CH3CCDE CH2CCDE CH1CCDE CH0CCDE... -
Page 246: Timer Event Generator Register - Evgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions CH2CCIE Channel 2 Capture/Compare Interrupt Enable 0: Channel 2 interrupt is disabled 1: Channel 2 interrupt is enabled CH1CCIE Channel 1 Capture/Compare Interrupt Enable 0: Channel 1 interrupt is disabled... - Page 247 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions CH3CCG Channel 3 Capture/Compare Generation A Channel 3 capture/compare event can be generated by setting this bit. It is cleared by hardware automatically. 0: No action 1: Capture/compare event is generated on channel 3 If Channel 3 is configured as an input, the counter value is captured into the CH3CCR register and then the CH3CCIF bit is set.
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Page 248: Timer Interrupt Status Register - Intsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Timer Interrupt Status Register – INTSR This register stores the timer interrupt status. Offset: 0x07C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVIF Reserved UEVIF Type/Reset CH3OCF CH2OCF CH1OCF CH0OCF CH3CCIF... - Page 249 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions CH0OCF Channel 0 Over-Capture Flag This flag is set by hardware and cleared by software. 0: No over-capture event is detected 1: Capture event occurs again when the CH0CCIFbit is already set and it is not yet cleared by software.
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Page 250: Timer Counter Register - Cntr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Timer Counter Register – CNTR This register stores the timer counter value. Offset: 0x080 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CNTV Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW... -
Page 251: Timer Counter Reload Register - Crr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Timer Counter Reload Register – CRR This register specifies the timer counter reload value. Offset: 0x088 Reset value: 0x0000_FFFF Reserved Type/Reset Reserved Type/Reset Type/Reset 1 RW 1 RW 1 RW 1 RW... -
Page 252: Channel 1 Capture/Compare Register - Ch1Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 1 Capture/Compare Register – CH1CCR This register specifies the timer channel 1 capture/compare value. Offset: 0x094 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH1CCV Type/Reset 0 RW 0 RW 0 RW... -
Page 253: Channel 2 Capture/Compare Register - Ch2Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 2 Capture/Compare Register – CH2CCR This register specifies the timer channel 2 capture/compare value. Offset: 0x098 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2CCV Type/Reset 0 RW 0 RW 0 RW... -
Page 254: Channel 3 Capture/Compare Register - Ch3Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 3 Capture/Compare Register – CH3CCR This register specifies the timer channel 3 capture/compare value. Offset: 0x09C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH3CCV Type/Reset 0 RW 0 RW 0 RW... -
Page 255: Channel 0 Asymmetric Compare Register - Ch0Acr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 0 Asymmetric Compare Register – CH0ACR This register specifies the timer channel 0 asymmetric compare value. Offset: 0x0A0 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH0ACV Type/Reset 0 RW 0 RW... -
Page 256: Channel 2 Asymmetric Compare Register - Ch2Acr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 2 Asymmetric Compare Register – CH2ACR This register specifies the timer channel 2 asymmetric compare value. Offset: 0x0A8 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2ACV Type/Reset 0 RW 0 RW... -
Page 257: Basic Function Timer (Bftm)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Basic Function Timer (BFTM) Introduction The Basic Function Timer Module, BFTM, is a 32-bit up-counting counter designed to measure time intervals, generate one shot pulses or generate repetitive interrupts. The BFTM can operate in two modes which are repetitive and one shot modes. -
Page 258: Functional Description
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Functional Description The BFTM is a 32-bit up-counting counter which is driven by the BFTM APB clock, PCLK. The counter value can be changed or read at any time even when the timer is counting. The BFTM supports two operating modes known as the repetitive mode and one shot mode allowing the measurement of time intervals or the generation of periodic time durations. -
Page 259: One Shot Mode
Cortex ® -M0+ MCU HT32F52243/HT32F52253 One Shot Mode By setting the OSM bit in BFTMCR register to 1, the BFTM will operate in the one shot mode. The BFTM starts to count when the CEN bit is set to 1 by the application program. The counter value will remain unchanged if the CEN bit is cleared to 0 by the application program. -
Page 260: Trigger Adc Start
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Trigger ADC Start When a BFTM compare match event occurs, a compare match interrupt f lag, MIF, will be generated which can be used as an A/D Converter input trigger source. Register Map The following table shows the BFTM registers and their reset values. -
Page 261: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Descriptions BFTM Control Register – BFTMCR This register specifies the overall BFTM control bits. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved MIEN Type/Reset 0 RW 0 RW... -
Page 262: Bftm Status Register - Bftmsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 BFTM Status Register – BFTMSR This register specifies the BFTM status. Offset: 0x004 Reset value: 0x0000_0004 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Bits Field Descriptions BFTM Compare Match Interrupt Flag... -
Page 263: Bftm Counter Register - Bftmcntr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 BFTM Counter Register – BFTMCNTR This register specifies the BFTM counter value. Offset: 0x008 Reset value: 0x0000_0000 Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW... -
Page 264: Motor Control Timer (Mctm)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Motor Control Timer (MCTM) Introduction The Motor Control Timer consists of one 16-bit up/down-counter, four 16-bit Capture/Compare Registers (CCRs), one 16-bit Counter-Reload Register (CRR), one 8-bit Repetition Counter (REPR) and several control/status registers. It can be used for a variety of purposes which include general time measurement, input signal pulse width measurement, output waveform generation for signals such as single pulse generation or PWM generation, including dead time insertion. -
Page 265: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Features ▄ 16-bit up/down auto-reload counter. ▄ 16-bit programmable prescaler that allows division the counter clock frequency by any factor between 1 and 65536. ▄ Up to 4 independent channels for: ●... -
Page 266: Functional Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Functional Descriptions Counter Mode Up-Counting In this mode the counter counts continuously from 0 to the counter-reload value, which is defined in the CRR register, in a count-up direction. Once the counter reaches the counter-reload value, the Timer Module generates an overflow event and the counter restarts to count once again from 0. -
Page 267: Figure 71. Down-Counting Example
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 CK_PSC CNT_EN CK_CNT CNTR CRR Shadow Register PSCR PSCR Shadow Register PSC_CNT Counter Underflow Update Event 1 Flag Software clearing Write a new value Update a new value Figure 71. Down-counting Example... -
Page 268: Figure 73. Update Event 1 Dependent Repetition Mechanism Example
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Repetition Down-counter Operation The update event 1 is usually generated at each overflow or underflow event occurrence. However, when the repetition operation is active by assigning a non-zero value into the REPR register, the update event is only generated if the REPR counter has reached zero. -
Page 269: Clock Controller
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Clock Controller The following describes the Timer Module clock controller which determines the internal prescaler counter clock source. ▄ Internal APB clock f CLKIN The default internal clock source is the APB clock f... -
Page 270: Figure 75. Trigger Controller Block
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Trigger Controller Block = Edge Trigger Mux + Level Trigger Mux Internal Trigger Input ITI0 ITI0ED ITI1 Edge ITI2 ITI1ED Detection ITI2ED CLKIN Edge Trigger = Internal (ITIx) + Channel input (TIn) -
Page 271: Slave Controller
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Slave Controller The MCTM can be synchronised with an internal/external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which are selected by the SMSEL field in the MDCFR register. -
Page 272: Figure 78. Mctm In Pause Mode
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Pause Mode In the Pause Mode, the selected STI input signal level is used to control the counter start/stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level. -
Page 273: Master Controller
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Master Controller The MCTMs and GPTMs can be linked together internally for timer synchronisation or chaining. When one MCTM is configured to be in the Master Mode, the MCTM Master Controller will generate a Master Trigger Output (MTO) signal which can reset, restart, stop the Slave counter or be a clock source of the Slave Counter. -
Page 274: Channel Controller
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel Controller The MCTM has four independent channels which can be used as capture inputs or compare match outputs. Each capture input or compare match output channel is composed of a preload register and a shadow register. -
Page 275: Input Stage
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Pulse Width Measurement The input capture mode can be also used for pulse width measurement from signals on the MT_CHx pins, TIx. The following example shows how to configure the MCTM when operated in the input capture mode to measure the high pulse width and the input period on the MT_CH0 pin using channel 0 and channel 1. -
Page 276: Figure 85. Channel 0 And Channel 1 Input Stages
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 TRCED TI0SRC CLKIN Edge Detection MT_CH0 TI0BED TI0XOR MT_CH1 Edge MT_CH2 Detection CH0CCS CLKIN Edge TI0S0 TI0S0ED TI0FP TI0FN Filter Detection sampling CH0PSC CH0PRESCALER CH0P CH0CAP Event TI0F Edge TI1S0 TI1S0ED CH0PSC... -
Page 277: Output Stage
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Digital Filter The digital filters are embedded in the input stage and clock controller block for the MT_CH0 ~ MT_CH3 pins. The digital filter in the MCTM is an N-event counter where N refers to how many valid transitions are necessary to output a filtered signal. -
Page 278: Table 34. Compare Match Output Setup
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Output Enable CHxO Controller CHxO_DT CNTR Output Mode CHxCCR CHxE CHMOE CHxNO_DT x=0~2 Controller CHxP x=0~2 CHOSSI CHOSSR CHxOIS CLKIN CHDTG Output Enable CHxNO Controller CHxOM CHxNE CHxE CHxNP CHxNE CHMOE CHOSSI... -
Page 279: Figure 89. Toggle Mode Channel Output Reference Signal - Chxpre = 0
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Counter Value CHxOM=0x03, CHxPRE=0 (Output toggle, preload disable) CHxCCR (New value 2) CHxCCR (New value 3) CHxCCR (New value 1) CHxCC Time Update CHxCCR value CHxOREF UEV1 (Update Event 1) Figure 89. Toggle Mode Channel Output Reference Signal – CHxPRE = 0... -
Page 280: Figure 91. Pwm Mode Channel Output Reference Signal And Counter In Up-Counting Mode
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Counter Value Counter Value Counter Value CHxCCR CHxCCR CHxCCR = 0x00 CHxOM = 0x06 100% CHxOREF CHxOREF CHxOREF CHxCCIF CHxCCIF CHxCCIF CHxOM = 0x07 100% CHxOREF CHxOREF CHxOREF Figure 91. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode... -
Page 281: Figure 93. Pwm Mode 1 Channel Output Reference Signal And Counter In Center-Aligned Counting Mode
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 CRR = 5 CMSEL= 0x01 Up-counting Down-counting CHxCCR = 3 CHxCCIF CHxCCR = 4 CHxCCIF CHxCCR >= 5 100% CHxCCIF CHxCCR = 0 CHxCCIF Figure 93. PWM Mode 1 Channel Output Reference Signal and Counter in Center-aligned... -
Page 282: Figure 94. Dead-Time Insertion Performed For Complementary Outputs
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 CHxP=0, CHxNP=0, CHMOE=1,CHxE=1, CHxNE=1 CHxOREF Dead-time CHxO CHxNO Dead-time When dead-time greater than negative pulse Dead-time CHxO CHxNO CHxP=0, CHxNP=0, CHMOE=1,CHxE=1, CHxNE=1 CHxOREF Dead-time CHxO Dead-time CHxNO When dead-time greater than positive pulse... -
Page 283: Figure 96. Mt_Brk Pin Digital Filter Diagram With N = 2
Cortex ® -M0+ MCU HT32F52243/HT32F52253 When the MT_BRK input has an active level or the Clock Monitor Circuitry detects a clock failure event, a break event will be generated if the break function is enabled. Meanwhile, each channel output will be forced to a reset state, an inactive or idle state. Moreover, a break event can also be generated by the software asserting the BRKG bit in the EVGR register even if the break function is disabled. -
Page 284: Figure 97. Channel 3 Output With A Break Event Occurrence
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Break event CHMOE CHxOREF CH3P = 0, CH3OIS =0 CH3O CH3P = 0, CH3OIS =1 CH3O CH3P = 1, CH3OIS =0 CH3O CH3P = 1, CH3OIS =1 CH3O Figure 97. Channel 3 Output with a Break Event Occurrence The accompanying diagram shows that the complementary output states when a break event occurs where the complementary outputs are enabled by setting both the CHxE and CHxNE bits to 1. -
Page 285: Figure 99. Channel 0 ~2 Only One Output Enabled When Break Event Occurs
Cortex ® -M0+ MCU HT32F52243/HT32F52253 The accompanying diagram shows the output states in the case of the output being enabled by setting the CHxE bit to 1 and the complementary output being disabled by clearing the CHxNE to 0 when a break event occurs. -
Page 286: Table 35. Output Control Bits For Complementary Output With A Break Event Occurrence
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 CHMOE can be set automatically by update event 1 if the automatic output enable function is enabled by setting the CHAOE bit in the CHBRKCTR register to 1. Channel Complementary Output with Break Function The Channel complementary outputs, CHxO and CHxNO, are enabled by a combination of the CHxE, CHxNE, CHMOE, CHOSSR, CHOSSI control bits. -
Page 287: Update Management
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Update Management The update events are categorised into two different types which are the update event 1, UEV1, and update event 2, UEV2. The update event 1 is used to update the CRR, the PSCR, the CHxACR and the CHxCCR values from the actual registers to the corresponding shadow registers. -
Page 288: Figure 102. Chxe, Chxne And Chxom Updated By Update Event 2
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Update Event 2 The CHxE, CHxNE, CHxOM control bits for the complementary outputs can be preloaded by setting the COMPRE bit in the CTR register. Here the shadow bits of the CHxE, CHxNE, and CHxOM bits will be updated when an update event 2 occurs. -
Page 289: Single Pulse Mode
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Single Pulse Mode Once the timer is set to operate in the single pulse mode, it is not necessary to set the timer enable bit TME in the CTR register to 1 to enable the counter. The trigger to generate a pulse can be sourced from the STI signal rising edge or by setting the TME bit to 1 using software. -
Page 290: Figure 105. Immediate Active Mode Minimum Delay
Cortex ® -M0+ MCU HT32F52243/HT32F52253 In the Single Pulse mode, the STI active edge which sets the TME bit to 1 will enable the counter. However, there exist several clock delays to perform the comparison result between the counter value and the CHxCCR value. In order to reduce the delay to a minimum value, users can set the CHxIMAE bit in each CHxOCFR register. -
Page 291: Asymmetric Pwm Mode
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Asymmetric PWM Mode Asymmetric PWM mode allows two center-aligned PWM signals to be genetated with a programmable phase shift. While the PWM frequency is determined by the value of the CRR register, the duty cycle and the phase-shift are determined by the CHxCCR and CHxACR register. -
Page 292: Timer Interconnection
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Timer Interconnection The timers can be internally connected together for timer chaining or synchronization. This can be implemented by configuring one timer to operate in the master mode while configuring another timer to be in the slave mode. The following figures present several examples of trigger selection for the master and slave modes. -
Page 293: Figure 108. Triggering Gptm With Mctm Update Event 1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Using one timer to trigger another timer to start counting ▄ Configure MCTM to operate in the master mode and to send its Update Event UEV as the trigger output (MMSEL = 0x02). -
Page 294: Figure 109. Trigger Mctm And Gptm With The Mctm Ch0 Input
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Starting two timers synchronously in response to an external trigger ▄ Configure MCTM to operate in the master mode to send its enable signal as a trigger output (MMSEL = 0x01). ▄... -
Page 295: Figure 110. Ch1Xor Input As Hall Sensor Interface
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Using one timer as a hall sensor interface to trigger another timer with update event 2 GPTM: ▄ Configure channel 0 to choose an input XOR function (TI0SRC = 1) ▄ Configure channel 0 to be in the input capture mode and TRCED as capture source (CH0CCS= 0x03) and Enable channel 0 (CH0E=1) ▄... -
Page 296: Trigger Adc Start
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Trigger ADC Start To interconnect to the Analog-to-Digital Converter, the MCTM can output the MTO signal or the channel compare match output signal CHxOREF (x = 0 ~ 3) to be used as an Analog-to-Digital Converter input trigger signal. -
Page 297: Pdma Request
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 PDMA Request The MCTM has a PDMA data transfer interface. There are certain events which can generate PDMA requests if the corresponding enable control bits are set to 1 to enable the PDMA access. -
Page 298: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Map The following table shows the MCTM registers and reset values. Table 37. MCTM Register Map Register Offset Description Reset Value CNTCFR 0x000 Timer Counter Configuration Register 0x0000_0000 MDCFR 0x004 Timer Mode Configuration Register... -
Page 299: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Descriptions Timer Counter Configuration Register – CNTCFR This register specifies the MCTM counter configuration. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CMSEL Type/Reset 0 RW Reserved CKDIV Type/Reset 0 RW... -
Page 300: Timer Mode Configuration Register - Mdcfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions UGDIS Update event 1 interrupt generation disable control 0: Any of the following events will generate an update PDMA request or interrupt - Counter overflow / underflow - Setting the UEV1G bit... - Page 301 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [18:16] MMSEL Master Mode Selection Master mode selection is used to select the MTO signal source which is used to synchronise the other slave timer. MMSEL [2:0] Mode Descriptions...
- Page 302 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [10:8] SMSEL Slave Mode Selection SMSEL [2:0] Mode Descriptions The prescaler is clocked directly by the Disable mode internal clock. Reserved Reserved Reserved The counter value restarts from 0 or the CRR...
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Page 303: Timer Trigger Configuration Register - Trcfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Timer Trigger Configuration Register – TRCFR This register specifies the trigger source selection of MCTM. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved TRSEL Type/Reset 0 RW 0 RW... -
Page 304: Timer Control Register - Ctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Timer Control Register – CTR This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE), Capture/compare control bit and Channel PDMA selection bit (CHCCDS). Offset: 0x010 Reset value: 0x0000_0000... -
Page 305: Channel 0 Input Configuration Register - Ch0Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 0 Input Configuration Register – CH0ICFR This register specifies the channel 0 input mode configuration. Offset: 0x020 Reset value: 0x0000_0000 TI0SRC Reserved Type/Reset Reserved CH0PSC CH0CCS Type/Reset 0 RW 0 RW... - Page 306 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [3:0] TI0F Channel 0 Input Source TI0 Filter Setting These bits define the frequency divided ratio used to sample the TI0 signal. The Digital filter in the MCTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
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Page 307: Channel 1 Input Configuration Register - Ch1Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 1 Input Configuration Register – CH1ICFR This register specifies the channel 1 input mode configuration. Offset: 0x024 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CH1PSC CH1CCS Type/Reset 0 RW 0 RW 0 RW... - Page 308 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [3:0] TI1F Channel 1 Input Source TI1 Filter Setting These bits define the frequency divide ratio used to sample the TI1 signal. The Digital filter in the MCTM is an N-event counter where N is defined as how many...
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Page 309: Channel 2 Input Configuration Register - Ch2Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 2 Input Configuration Register – CH2ICFR This register specifies the channel 2 input mode configuration. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CH2PSC CH2CCS Type/Reset 0 RW 0 RW 0 RW... - Page 310 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [3:0] TI2F Channel 2 Input Source TI2 Filter Setting These bits define the frequency divide ratio used to sample the TI2 signal. The Digital filter in the MCTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
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Page 311: Channel 3 Input Configuration Register - Ch3Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 3 Input Configuration Register – CH3ICFR This register specifies the channel 3 input mode configuration. Offset: 0x02C Reset value: 0x0000_0000 Reserved Type/Reset Reserved CH3PSC CH3CCS Type/Reset 0 RW 0 RW 0 RW... - Page 312 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [3:0] TI3F Channel 3 Input Source TI3 Filter Setting These bits define the frequency divide ratio used to sample the TI3 signal. The digital filter in the GPTM is an N-event counter where N is defined as how many...
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Page 313: Channel 0 Output Configuration Register - Ch0Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 0 Output Configuration Register – CH0OCFR This register specifies the channel 0 output mode configuration. Offset: 0x040 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH0OM[3] Type/Reset Reserved CH0IMAE CH0PRE Reserved... - Page 314 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [8][2:0] CH0OM[3:0] Channel 0 Output Mode Setting These bits define the functional types of the output reference signal CH0OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
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Page 315: Channel 1 Output Configuration Register - Ch1Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 1 Output Configuration Register – CH1OCFR This register specifies the channel 1 output mode configuration. Offset: 0x044 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH1OM[3] Type/Reset Reserved CH1IMAE CH1PRE Reserved... - Page 316 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [8][2:0] CH1OM[3:0] Channel 1 Output Mode Setting These bits define the functional types of the output reference signal CH1OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
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Page 317: Channel 2 Output Configuration Register - Ch2Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 2 Output Configuration Register – CH2OCFR This register specifies the channel 2 output mode configuration. Offset: 0x048 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH2OM[3] Type/Reset Reserved CH2IMAE CH2PRE Reserved... - Page 318 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [8][2:0] CH2OM[3:0] Channel 2 Output Mode Setting These bits define the functional types of the output reference signal CH2OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
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Page 319: Channel 3 Output Configuration Register - Ch3Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 3 Output Configuration Register – CH3OCFR This register specifies the channel 3 output mode configuration. Offset: 0x04C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH3OM[3] Type/Reset Reserved CH3IMAE CH3PRE Reserved... - Page 320 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [8][2:0] CH3OM[3:0] Channel 3 Output Mode Setting These bits define the functional types of the output reference signal CH3OREF 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
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Page 321: Channel Control Register - Chctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel Control Register – CHCTR This register contains the channel capture input or compare output function enable control bits. Offset: 0x050 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3E... - Page 322 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions CH1NE Channel 1 Capture/Compare Complementary Enable 0: Off – Channel 1 complementary output CH1NO is not active. The CH1NO level is then determined by the condition of the CHMOE, CHOSSI, CHOSSR, CH1OIS, CH1OISN and CH1E bits.
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Page 323: Channel Polarity Configuration Register - Chpolr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel Polarity Configuration Register – CHPOLR This register contains the channel capture input or compare output polarity control. Offset: 0x054 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3P CH2NP... -
Page 324: Channel Break Configuration Register - Chbrkcfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions CH0P Channel 0 Capture/Compare Polarity - When Channel 0 is configured as an input 0: Capture event occurs on a Channel 0 rising edge 1: Capture event occurs on a Channel 0 falling edge... -
Page 325: Channel Break Control Register - Chbrkctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel Break Control Register – CHBRKCTR This register specifies the channel break control bits. Offset: 0x070 Reset value: 0x0000_0002 CHDTG Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW... - Page 326 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [11:8] Break Input Filter Setting These bits define the frequency ratio used to sample the MT_BRK signal. The digital filter in the MCTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
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Page 327: Timer Pdma/Interrupt Control Register - Dictr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Timer PDMA/Interrupt Control Register – DICTR This register contains the timer PDAM and interrupt enable control bits. Offset: 0x074 Reset value: 0x0000_0000 Reserved TEVDE UEV2DE UEV1DE Type/Reset 0 RW 0 RW Reserved... - Page 328 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions UEV1IE Update event 1 Interrupt Enable 0: Update event 1 interrupt is disabled 1: Update event 1 interrupt is enabled CH3CCIE Channel 3 Capture/Compare Interrupt Enable 0: Channel 3 interrupt is disabled...
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Page 329: Timer Event Generator Register - Evgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Timer Event Generator Register – EVGR This register contains the software event generation bits. Offset: 0x078 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved BRKG TEVG UEV2G UEV1G Type/Reset 0 WO 0 WO... - Page 330 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions CH3CCG Channel 3 Capture/Compare Generation A Channel 3 capture/compare event can be generated by setting this bit. It is cleared by hardware automatically. 0: No action 1: Capture/compare event is generated on channel 3 If Channel 3 is configured as an input, the counter value is captured into the CH3CCR register and then the CH3CCIF bit is set.
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Page 331: Timer Interrupt Status Register - Intsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Timer Interrupt Status Register – INTSR This register stores the timer interrupt status. Offset: 0x07C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved BRKIF TEVIF UEV2IF UEV1IF Type/Reset 0 W0C 0 W0C... - Page 332 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions CH1OCF Channel 1 Over-capture Flag This flag is set by hardware and cleared by software. 0: No over-capture event is detected 1: Capture event occurs again when the CH1CCIF bit is already set and it is not cleared yet by software.
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Page 333: Timer Counter Register - Cntr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions CH0CCIF Channel 0 Capture/Compare Interrupt Flag - Channel 0 is configured as an output 0: No match event occurs 1: The contents of the counter CNTR have matched the content of the CH0CCR... -
Page 334: Timer Prescaler Register - Pscr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Timer Prescaler Register – PSCR This register specifies the timer prescaler value to generate the counter clock. Offset: 0x084 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PSCV Type/Reset 0 RW 0 RW... -
Page 335: Timer Counter Reload Register - Crr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Timer Counter Reload Register – CRR This register specifies the timer counter reload value. Offset: 0x088 Reset value: 0x0000_FFFF Reserved Type/Reset Reserved Type/Reset Type/Reset 1 RW 1 RW 1 RW 1 RW... -
Page 336: Channel 0 Capture/Compare Register - Ch0Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 0 Capture/Compare Register – CH0CCR This register specifies the timer channel 0 capture/compare value. Offset: 0x090 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH0CCV Type/Reset 0 RW 0 RW 0 RW... -
Page 337: Channel 1 Capture/Compare Register - Ch1Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 1 Capture/Compare Register – CH1CCR This register specifies the timer channel 1 capture/compare value. Offset: 0x094 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH1CCV Type/Reset 0 RW 0 RW 0 RW... -
Page 338: Channel 2 Capture/Compare Register - Ch2Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 2 Capture/Compare Register – CH2CCR This register specifies the timer channel 2 capture/compare value. Offset: 0x098 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2CCV Type/Reset 0 RW 0 RW 0 RW... -
Page 339: Channel 3 Capture/Compare Register - Ch3Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 3 Capture/Compare Register – CH3CCR This register specifies the timer channel 3 capture/compare value. Offset: 0x09C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH3CCV Type/Reset 0 RW 0 RW 0 RW... -
Page 340: Channel 0 Asymmetric Compare Register - Ch0Acr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 0 Asymmetric Compare Register – CH0ACR This register specifies the timer channel 0 asymmetric compare value. Offset: 0x0A0 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH0ACV Type/Reset 0 RW 0 RW... -
Page 341: Channel 2 Asymmetric Compare Register - Ch2Acr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 2 Asymmetric Compare Register – CH2ACR This register specifies the timer channel 2 asymmetric compare value. Offset: 0x0A8 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2ACV Type/Reset 0 RW 0 RW... -
Page 342: Single-Channel Timer (Sctm)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Single-Channel Timer (SCTM) Introduction The Single-Channel Timer consists of one 16-bit up-counter, one 16-bit Capture/Compare Register (CCR), one 16-bit Counter-Reload Register (CRR) and several control/status registers. It can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as single pulse generation or PWM output. -
Page 343: Functional Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Functional Descriptions Counter Mode Up-Counting The counter counts continuously from 0 to the counter-reload value, which is defined in the CRR register. Once the counter reaches the counter-reload value, the Timer Module generates an overflow event and the counter restarts to count once again from 0. -
Page 344: Trigger Controller
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 PSCR Update Event CLKIN (Internal APB clock) CK_PSC CK_CNT PSC Prescaler CNTR TM_CNT STIED (Trigger events) Reset Reset TRSEL SMSEL ECME Start/Stop Slave Restart Overflow UEVG bit mode trigger Figure 114. SCTM Clock Selection Source... -
Page 345: Figure 115. Trigger Control Block
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Trigger Controller Block = Edge Trigger Mux + Level Trigger Mux Edge Trigger = Channel input Edge Trigger Mux TISED Reserved Reserved STIED_S0 others Reserved TRSEL[2:0] TIBED Reserved STIED Reserved STIED_S1 Reserved... -
Page 346: Slave Controller
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Slave Controller The SCTM can be synchronized with an external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which is selected by the SMSEL field in the MDCFR register. -
Page 347: Figure 118. Sctm In Pause Mode
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Pause Mode In the Pause Mode, the selected STI input signal level is used to control the counter start/stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level, here the counter will maintain its present value and will not be reset. -
Page 348: Channel Controller
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel Controller The SCTM channel can be used as the capture inpus or compare match outpus. Capture input or compare match output channel is composed of a preload register and a shadow register. Data access of the APB bus is always through the read/write preload register. -
Page 349: Input Stage
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 CLKIN SCTM_CH CNTR CHCCR CHCCIF CHOCF Figure 121. Input Capture Mode Input Stage The input stage consists of a digital filter, a channel polarity selection, edge detection and a channel prescaler. The channel input signal (TI) is sampled by a digital filter to generate a filtered input signal TIFP. -
Page 350: Output Stage
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Digital Filter The digital filters are embedded in the channel input stage. The digital filter in the SCTM is an N-event counter where N refers to how many valid transitions are necessary to output a filtered signal. -
Page 351: Table 39. Compare Match Output Setup
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel Output Reference Signal When the SCTM is used in the compare match output mode, the CHOREF signal (Channel Output Reference signal) is defined by the CHOM bit setup. The CHOREF signal has several types of output function which defines what happens to the output when the counter value matches the contents of the CHCCR register. -
Page 352: Figure 126. Toggle Mode Channel Output Reference Signal (Chpre = 1)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Counter Value CHOM=0x03, CHPRE=1 (Output toggle, preload enable) CHCCR (New value 2) CHCCR (New value 3) CHCCR (New value 1) CHCCR Time Update CHCCR value CHOREF (Update Event) Figure 126. Toggle Mode Channel Output Reference Signal (CHPRE = 1) -
Page 353: Update Management
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Update Management The Update event is used to update the CRR, the PSCR and the CHCCR values from the actual registers to the corresponding shadow registers. An update event will occur when the counter overflows, the software update control bit is triggered or an update event from the slave controller is generated. -
Page 354: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Map The following table shows the SCTM registers and reset values. Table 40. SCTM Register Map Register Offset Description Reset Value CNTCFR 0x000 Timer Counter Configuration Register 0x0000_0000 MDCFR 0x004 Timer Mode Configuration Register... -
Page 355: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Descriptions Timer Counter Configuration Register – CNTCFR This register specifies the SCTM counter configuration. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CKDIV Type/Reset 0 RW Reserved UGDIS UEVDIS... -
Page 356: Timer Mode Configuration Register - Mdcfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Timer Mode Configuration Register – MDCFR This register specifies the SCTM slave mode selection. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved SMSEL Type/Reset 0 RW 0 RW Reserved Type/Reset... -
Page 357: Timer Trigger Configuration Register - Trcfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Timer Trigger Configuration Register – TRCFR This register specifies the trigger source selection of SCTM. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved TRSEL Type/Reset 0 RW 0 RW... -
Page 358: Timer Control Register - Ctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Timer Control Register – CTR This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE). Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CRBE Type/Reset... -
Page 359: Channel Input Configuration Register - Chicfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel Input Configuration Register – CHICFR This register specifies the channel input mode configuration. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CHPSC CHCCS Type/Reset 0 RW 0 RW 0 RW Reserved... - Page 360 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [3:0] Channel Input Source TI Filter Setting These bits define the frequency divided ratio used to sample the TI signal. The Digital filter in the SCTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
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Page 361: Channel Output Configuration Register - Chocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel Output Configuration Register – CHOCFR This register specifies the channel output mode configuration. Offset: 0x040 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CHPRE Reserved CHOM[2:0] Type/Reset 0 RW... -
Page 362: Channel Control Register - Chctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel Control Register – CHCTR This register contains the channel capture input or compare output function enable control bits. Offset: 0x050 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset... -
Page 363: Channel Polarity Configuration Register - Chpolr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel Polarity Configuration Register – CHPOLR This register contains the channel capture input or compare output polarity control. Offset: 0x054 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Bits... -
Page 364: Timer Interrupt Control Register - Dictr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Timer Interrupt Control Register – DICTR This register contains the timer interrupt enable control bits. Offset: 0x074 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVIE Reserved UEVIE Type/Reset Reserved CHCCIE Type/Reset... -
Page 365: Timer Event Generator Register - Evgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Timer Event Generator Register – EVGR This register contains the software event generation bits. Offset: 0x078 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVG Reserved UEVG Type/Reset Reserved CHCCG Type/Reset Bits... -
Page 366: Timer Interrupt Status Register - Intsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Timer Interrupt Status Register – INTSR This register stores the timer interrupt status. Offset: 0x07C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVIF Reserved UEVIF Type/Reset Reserved CHOCF Reserved CHCCIF Type/Reset... -
Page 367: Timer Counter Register - Cntr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Timer Counter Register – CNTR This register stores the timer counter value. Offset: 0x080 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CNTV Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW... -
Page 368: Timer Counter Reload Register - Crr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Timer Counter Reload Register – CRR This register specifies the timer counter reload value. Offset: 0x088 Reset value: 0x0000_FFFF Reserved Type/Reset Reserved Type/Reset Type/Reset 1 RW 1 RW 1 RW 1 RW... -
Page 369: Channel Capture/Compare Register - Chccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel Capture/Compare Register – CHCCR This register specifies the timer channel capture/compare value. Offset: 0x090 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CHCCV Type/Reset 0 RW 0 RW 0 RW 0 RW... -
Page 370: Real Time Clock (Rtc)
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Real Time Clock (RTC) Introduction The Real Time Clock, RTC, circuitry includes the APB interface, a 24-bit up-counter, a control register, a prescaler, a compare register and a status register. Most of the RTC circuits are located in the V Domain, as shown shaded in the accompanying figure, except for the APB interface. -
Page 371: Functional Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Functional Descriptions RTC Related Register Reset The RTC registers can only be reset by either a V Domain power on reset, POR, or by a V Domain software reset by setting the PWRST bit in the PWRCR register. Other reset events have no effect to clear the RTC registers. -
Page 372: Rtc Counter Operation
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 RTC Counter Operation The RTC provides a 24-bit up-counter which increments at the falling edge of the CK_SECOND clock and whose value can be read from the RTCCNT register asynchronously via the APB bus. -
Page 373: Rtcout Output Pin Configuration
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 RTCOUT Output Pin Configuration The following table shows RTCOUT output format according to the mode, polarity, and event selection setting. Table 42. RTCOUT Output Mode and Active Level Setting ROWM ROES RTCOUT Output Waveform... -
Page 374: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Map The following table shows the RTC registers and reset values. Note all the registers in this unit are located at the V power domain. Table 43. RTC Register Map Register... -
Page 375: Rtc Compare Register - Rtccmp
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 RTC Compare Register – RTCCMP This register defines a specific value to be compared with the RTC counter value. Offset: 0x004 Reset value: 0x0000_0000 (Reset by V Power Domain reset only) Reserved... -
Page 376: Rtc Control Register - Rtccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 RTC Control Register – RTCCR This register specifies a range of RTC circuitry control bits. Offset: 0x008 Reset value: 0x0000_0F04 (Reset by V Power Domain reset only) Reserved Type/Reset Reserved ROLF ROAP... - Page 377 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [11:8] RPRE RTC Clock Prescaler Select CK_SECOND = CK_RTC / 2 RPRE 0000: CK_SECOND = CK_RTC / 2 0001: CK_SECOND = CK_RTC / 2 0010: CK_SECOND = CK_RTC / 2 …...
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Page 378: Rtc Status Register - Rtcsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 RTC Status Register – RTCSR This register stores the counter flags. Offset: 0x00C Reset value: 0x0000_0000 (Reset by V Power Domain reset and RTCEN bit change from 1 to 0) Reserved Type/Reset... -
Page 379: Rtc Interrupt And Wakeup Enable Register - Rtciwen
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 RTC Interrupt and Wakeup Enable Register – RTCIWEN This register contains the interrupt and wakeup enable bits. Offset: 0x010 Reset value: 0x0000_0000 (Reset by V Power Domain reset only) Reserved Type/Reset Reserved... -
Page 380: Watchdog Timer (Wdt)
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Watchdog Timer (WDT) Introduction The Watchdog timer is a hardware timing circuitry that can be used to detect a system lock-up due to software trapped in a deadlock. The Watchdog timer can be operated in a reset mode. The Watchdog timer will generate a reset when the counter counts down to a zero value. -
Page 381: Functional Description
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Functional Description The Watchdog timer is formed from a 12-bit count-down and a fixed 3-bit prescaler. The largest time-out period is 16 seconds, using the LSE or LSI clock and a 1/128 maximum prescaler value. -
Page 382: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 The Watchdog timer should be used in the following manners: ▄ Set the Watchdog timer reload value (WDTV) and reset in the WDTMR0 register. ▄ Set the Watchdog timer delta value (WDTD) and prescaler in the WDTMR1 register. -
Page 383: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Descriptions Watchdog Timer Control Register – WDTCR This register is used to reload the Watchdog timer. Offset: 0x000 Reset value: 0x0000_0000 RSKEY Type/Reset 0 WO 0 WO 0 WO 0 WO... -
Page 384: Watchdog Timer Mode Register 0 - Wdtmr0
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Watchdog Timer Mode Register 0 – WDTMR0 This register specifies the Watchdog timer counter reload value and reset enable control. Offset: 0x004 Reset value: 0x0000_0FFF Reserved Type/Reset Reserved WDTEN Type/Reset WDTSHLT WDTRSTEN Reserved... -
Page 385: Watchdog Timer Mode Register 1 - Wdtmr1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Watchdog Timer Mode Register 1 – WDTMR1 This register specifies the Watchdog delta value and the prescaler selection. Offset: 0x008 Reset value: 0x0000_7FFF Reserved Type/Reset Reserved Type/Reset Reserved WPSC WDTD Type/Reset 1 RW... -
Page 386: Watchdog Timer Status Register - Wdtsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Watchdog Timer Status Register – WDTSR This register specifies the Watchdog timer status. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved WDTERR WDTUF Type/Reset 0 WC Bits Field... -
Page 387: Watchdog Timer Protection Register - Wdtpr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Watchdog Timer Protection Register – WDTPR This register specifies the Watchdog timer protect key configuration. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PROTECT Type/Reset 0 RW 0 RW 0 RW... -
Page 388: Watchdog Timer Clock Selection Register - Wdtcsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Watchdog Timer Clock Selection Register – WDTCSR This register specifies the Watchdog timer clock source selection and lock configuration. Offset: 0x018 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved WDTLOCK... -
Page 389: Inter-Integrated Circuit - I C
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Inter-Integrated Circuit – I Introduction The I C Module is an internal circuit allowing communication with an external I C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line, SDA, and a serial clock line, SCL. -
Page 390: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Features ▄ Two–wire I C serial interface ● Serial data line (SDA) and serial clock (SCL) ▄ Multiple speed modes ● Standard mode – 100 kHz ● Fast mode – 400 kHz ●... -
Page 391: Data Validity
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 START Condition STOP Condition Figure 133. START and STOP Condition Data Validity The data on the SDA line must be stable during the high period of the SCL clock. The SDA data state can only be changed when the clock signal on the SCL line is in a low state. -
Page 392: Addressing Format
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Addressing Format The I C interface starts to transfer data after the master device has sent the address to confirm the targeted slave device. The address frame is sent just after the START signal by master device. The addressing mode selection bit named ADRM in the I2CCR register should be defined to choose either the 7-bit or 10-bit addressing mode. -
Page 393: Data Transfer And Acknowledge
Cortex ® -M0+ MCU HT32F52243/HT32F52253 10-bit Address Format In order to prevent address clashes, due to the limited range of the 7-bit addresses, a new 10-bit address scheme has been introduced. This enhancement can be mixed with the 7-bit addressing mode which increases the available address range about ten times. -
Page 394: Clock Synchronization
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Data Frame Acknowledge bit SCL from Master Data output Transmitter Not acknowledge Data output Receiver acknowledge Figure 138. I C Bus Acknowledge Clock Synchronization Only one master device can generate the SCL clock under normal operation. However when there is more than one master trying to generate the SCL clock, the clock should be synchronized so that the data output can be compared. -
Page 395: Arbitration
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Arbitration A master may start a transfer only if the I C bus line is in the free or idle mode. If two or more masters generate a START signal at approximately the same time, an arbitration procedure will occur. -
Page 396: Address Mask Enable
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Address Mask Enable The I C module provides address mask function for user to decide which address bit can be ignored during the comparison with the address frame sent from the master. The ADRS flag will be asserted when the unmasked address bits and the address frame sent from the master are matched. -
Page 397: Master Receiver Mode
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Close / Continue Transmission After transmitting the last data byte, the STOP bit in the I2CCR register can be set to terminate the transmission or re-assign another slave device by configuring the I2CTAR register to restart a new transfer. -
Page 398: Figure 142. Master Receiver Timing Diagram
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Data Frame In the master receiver mode, data is transmitted from the slave device. Once a data is received by the master device, the RXDNE flag in the I2CSR register is set but it will not hold the SCL line. -
Page 399: Slave Transmitter Mode
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Slave Transmitter Mode Address Frame In the 7-bit addressing mode, the ADRS bit in the I2CSR register is set after the slave device receives the calling address which matches with the slave device address. In the 10-bit addressing mode, the ADRS bit is set when the first header byte is matched and the second address byte is matched respectively. -
Page 400: Slave Receiver Mode
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Slave Receiver Mode Address Frame The ADRS bit in the I2CSR register is set after the slave device receives the calling address which matches with the slave device address. After the ADRS bit has been set to 1, it must be cleared to 0 to continue the data transfer process. -
Page 401: Conditions Of Holding Scl Line
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Conditions of Holding SCL Line The following conditions will cause the SCL line to be held at a logic low state by hardware resulting in all the I C transfers being stopped. Data transfer will be continued after the creating conditions are eliminated. -
Page 402: I 2 C Timeout Function
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 C Timeout Function In order to reduce the occurrence of I C lockup problem due to the reception of erroneous clock source, a timeout function is provided. If the I C bus clock source is not received for a certain timeout period, then a corresponding I C timeout flag will be asserted. -
Page 403: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Map The following table shows the I C registers and reset values. Table 46. I C Register Map Register Offset Description Reset Value I2CCR 0x000 C Control Register 0x0000_2000 I2CIER 0x004... -
Page 404: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Descriptions C Control Register – I2CCR This register specifies the corresponding I C function enable control. Offset: 0x000 (0) Reset 0x0000_2000 value: Reserved Type/Reset Reserved Type/Reset SEQFILTER COMBFILTEREn ENTOUT Reserved DMANACK RXDMAE TXDMAE... - Page 405 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions RXDMAE DMA Mode RX Request Enable Control 0: RX DMA request disabled 1: RX DMA request enabled If the data register is not empty in the receiver mode and the RXDMAE bit is set to 1, the relevant PDMA channel will be activated to move the data from the data register to a specific location which is defined in the corresponding PDMA register.
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Page 406: I 2 C Interrupt Enable Register - I2Cier
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 C Interrupt Enable Register – I2CIER This register specifies the corresponding I C interrupt enable bits. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved RXBFIE TXDEIE RXDNEIE Type/Reset 0 RW 0 RW... -
Page 407: I 2 C Address Register - I2Caddr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions ARBLOSIE Arbitration Loss Interrupt Enable Bit in the I2C multi-master mode 0: Interrupt disabled 1: Interrupt enabled When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by hardware. -
Page 408: I 2 C Status Register - I2Csr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 C Status Register – I2CSR This register contains the I C operation status. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved TXNRX MASTER BUSBUSY RXBF TXDE RXDNE Type/Reset 0 RO 0 RO... - Page 409 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [17] TXDE Data Register Empty Using in Transmitter Mode 0: Data register I2CDR not empty 1: Data register I2CDR empty This bit is set when the I2CDR register is empty in the Transmitter mode. Note that the TXDE bit will be set after the address frame is being transmitted to inform that the data to be transmitted should be loaded into the I2CDR register.
- Page 410 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions ADRS Address Transmit (master mode) / Address Receive (slave mode) Flag Address Sent in Master Mode 0: Address frame has not been transmitted 1: Address frame has been transmitted For the 7-bit addressing mode, this bit is set after the master device receives the address frame acknowledge bit sent from the slave device.
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Page 411: I 2 C Scl High Period Generation Register - I2Cshpgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 C SCL High Period Generation Register – I2CSHPGR This register specifies the I C SCL clock high period interval. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset SHPG Type/Reset 0 RW... -
Page 412: I 2 C Scl Low Period Generation Register - I2Cslpgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 C SCL Low Period Generation Register – I2CSLPGR This register specifies the I C SCL clock low period interval. Offset: 0x014 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset SLPG Type/Reset 0 RW... -
Page 413: C Data Register - I2Cdr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 C Data Register – I2CDR This register specifies the data to be transmitted or received by the I C module. Offset: 0x018 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset DATA... -
Page 414: I 2 C Target Register - I2Ctar
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 C Target Register – I2CTAR This register specifies the target device address to be communicated. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset 0 RW 0 RW Type/Reset 0 RW... -
Page 415: I 2 C Address Mask Register - I2Caddmr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 C Address Mask Register – I2CADDMR This register specifies which bit of the I C address is masked and not compared with corresponding bit of the received address frame. Offset: 0x020 Reset value: 0x0000_0000... -
Page 416: I 2 C Address Snoop Register - I2Caddsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 C Address Snoop Register – I2CADDSR This register is used to indicate the address frame value appeared on the I C bus. Offset: 0x024 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved... -
Page 417: I 2 C Timeout Register - I2Ctout
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 C Timeout Register – I2CTOUT This register specifies the I C Timeout counter preload value and clock prescaler ratio. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset 0 RW 0 RW... -
Page 418: Serial Peripheral Interface (Spi)
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Serial Peripheral Interface (SPI) Introduction The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive functions in both master or slave mode. The SPI interface uses 4 pins, among which are serial data input and output lines MISO and MOSI, the clock line SCK, and the slave select line SEL. -
Page 419: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Features ▄ Master or slave mode ▄ Master mode speed up to f PCLK ▄ Slave mode speed up to f PCLK ▄ Programmable data frame length up to 16 bits ▄... -
Page 420: Spi Serial Frame Format
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 SPI Serial Frame Format The SPI interface format is base on the Clock Polarity, CPOL, and the Clock Phase, CPHA, configurations. ▄ Clock Polarity Bit – CPOL When the Clock Polarity bit is cleared to 0, the SCK line idle state is LOW. When the Clock Polarity bit is set to 1, the SCK line idle state is HIGH. -
Page 421: Figure 148. Spi Continuous Data Transfer Timing Diagram - Cpol = 0, Cpha = 0
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 The following figure shows the continuous data transfer timing diagram of this format. Note that the SEL signal must change to an inactive level between each data frame. SEL (SELAP=0) SEL (SELAP=1) -
Page 422: Figure 150. Spi Continuous Transfer Timing Diagram - Cpol = 0, Cpha = 1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 The following figure shows the continuous data transfer diagram timing. Note that the SEL signal must remain active until the last data transfer has completed. SEL (SELAP=0) SEL (SELAP=1) Data1 Data2 MOSI/MISO Figure 150. -
Page 423: Figure 152. Spi Continuous Transfer Timing Diagram - Cpol = 1, Cpha = 0
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 The following figure shows the continuous data transfer timing of this format. Note that the SEL signal must change to an inactive level between each data frame. SEL (SELAP=0) SEL (SELAP=1) ½... -
Page 424: Status Flags
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 The following figure shows the continuous data transfer timing of this format. Note that the SEL signal must remain active until the last data transfer has completed. SEL (SELAP=0) SEL (SELAP=1) Data1... -
Page 425: Table 49. Spi Mode Fault Trigger Conditions
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Mode Fault – MF The mode fault flag can be used to detect SPI bus usage in the SPI multi-master mode. For the multi-master mode, the SPI module is configured as a master device and the SEL signal is setup as an input signal. -
Page 426: Table 50. Spi Master Mode Sel Pin Status
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Table 50. SPI Master Mode SEL Pin Status. SEL as Input – SELOEN = 0 SEL as Output – SELOEN = 1 Multi-master Support Not support SPI SEL control Use Another GPIO to replace the SEL... -
Page 427: Pdma Interface
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 PDMA Interface The PDMA interface is integrated in the SPI module. The PDMA function can be enabled by setting the TXDMAE or RXDMAE bit to 1 in the transmitter or receiver mode respectively. When... -
Page 428: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Descriptions SPI Control Register 0 – SPICR0 This register specifies the SEL control and the SPI enable bits. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset SELHT GUADT Type/Reset 0 RW... - Page 429 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions SSELC Software Slave Select Control 0: Set the SEL output to an inactive state 1: Set the SEL output to an active state The application Software can setup the SEL output to an active or inactive state by configuring the SSELC bit.
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Page 430: Spi Control Register 1 - Spicr1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 SPI Control Register 1 – SPICR1 This register specifies the SPI parameters including the data length, the transfer format, the SEL active polarity/ mode, the LSB/MSB control, and the master/slave mode. Offset:... - Page 431 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [10:8] FORMAT SPI Data Transfer Format These three bits are used to determine the data transfer format of the SPI interface FORMAT [2:0] CPOL CPHA Others Reserved CPOL: Clock Polarity...
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Page 432: Spi Interrupt Enable Register - Spiier
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 SPI Interrupt Enable Register – SPIIER This register contains the corresponding SPI interrupt enable control bit. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset TOIEN SAIEN MFIEN ROIEN WCIEN... -
Page 433: Spi Clock Prescaler Register - Spicpr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 SPI Clock Prescaler Register – SPICPR This register specifies the SPI clock prescaler ratio. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Type/Reset 0 RW 0 RW 0 RW 0 RW... -
Page 434: Spi Data Register - Spidr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 SPI Data Register – SPIDR This register stores the SPI received or transmitted Data. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Type/Reset 0 RW 0 RW 0 RW 0 RW... -
Page 435: Spi Status Register - Spisr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 SPI Status Register – SPISR This register contains the relevant SPI status. Offset: 0x014 Reset value: 0x0000_0003 Reserved Type/Reset Reserved Type/Reset Reserved BUSY Type/Reset RXBNE TXBE Type/Reset 0 WC 0 WC 0 WC... -
Page 436: Spi Fifo Control Register - Spifcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions RXBNE Receive Buffer Not Empty flag 0: RX buffer empty 1: RX buffer not empty This bit indicates the RX buffer status in the non-FIFO mode. It is also used to indicate if the RX FIFO trigger level has been reached in the FIFO mode. -
Page 437: Spi Fifo Status Register - Spifsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [7:4] RXFTLS RX FIFO Trigger Level Select 0000: Trigger level is 0 0001: Trigger level is 1 1000: Trigger level is 8 Others: Reserved The RXFTLS field is used to specify the RX FIFO trigger level. When the number of... -
Page 438: Spi Fifo Time Out Counter Register - Spiftocr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [3:0] TXFS TX FIFO Status 0000: TX FIFO empty 0001: TX FIFO contains 1 data … 1000: TX FIFO contains 8 data Others: Reserved SPI FIFO Time Out Counter Register – SPIFTOCR This register stores the SPI RX FIFO time out counter compared value. -
Page 439: Universal Synchronous Asynchronous Receiver Transmitter (Usart)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Universal Synchronous Asynchronous Receiver Transmitter (USART) Introduction The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. The USART is used to translate data between parallel and serial interfaces, and is also commonly used for RS232 standard communication. -
Page 440: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Features ▄ Supports both asynchronous and clocked synchronous serial communication modes ▄ Full Duplex Communication Capability ▄ Programming baud rate up to 3 Mbit/s for asynchronous mode and 6 Mbit/s for synchronous mode ▄... -
Page 441: Function Descriptions
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Function Descriptions Serial Data Format The USART module performs a parallel-to-serial conversion on data that is written to the transmit FIFO registers and then sends the data with the following format: Start bit, 7 ~ 9 LSB first data bits, optional Parity bit and finally 1 ~ 2 Stop bits. -
Page 442: Baud Rate Generation
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Baud Rate Generation The baud rate for the USART receiver and transmitter are both set with the same values. The baud-rate divisor, BRD, has the following relationship with the USART clock which is known as CK_USART. -
Page 443: Hardware Flow Control
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Table 53. Baud Rate Deviation Error Calculation – CK_USART = 48 MHz. Baud rate CK_USART = 48 MHz Deviation Kbps Actual Error rate 20000 0.00% 5000 0.00% 19.2 19.2 2500 0.00% 57.6 57.6... -
Page 444: Figure 160. Usart Rts Flow Control
Cortex ® -M0+ MCU HT32F52243/HT32F52253 RTS Flow Control In the RTS flow control, the USART RTS pin is active with a logic low state when the receive data register is empty. It means that the receiver is ready to receive a new data. When the RX FIFO reaches the trigger level which is specified by configuring the RFTL field in the USRFCR register, the USART RTS pin is inactive with a logic high state. -
Page 445: Irda
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 IrDA The USART IrDA mode is provided half-duplex point-to-point wireless communication. The USART module includes an integrated modulator and demodulator which allow a wireless communication using infrared transceivers. The transmitter specifies a logic data ‘0’ as a ‘high’... - Page 446 ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 The IrDA mode provides two operation modes, one is the normal mode, and the other is the low- power mode. IrDA Normal Mode For the IrDA normal mode, the width of each transmitted pulse generated by the transmitter modulator is specified as 3/16th of the baud rate clock period.
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Page 447: Rs485 Mode
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 TX_Data Transmitter Modulation TXSEL RX_Data Receiver Demodulation IrDAEN Figure 163. USART I/O and IrDA Block Diagram RS485 Mode The RS485 mode of USART provides the data on interface is transmitted over a 2-wire twisted pair bus. -
Page 448: Figure 164. Rs485 Interface And Waveform
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 RS-485 Transceiver Differential USART TG = 4 Reference Divisor Clock D7 Parity Stop Start D3 D4 D5 TXENP =0 TXENP =1 Figure 164. RS485 Interface and Waveform RS485 Normal Multi-drop Operation Mode – NMM When the RS485 mode is configured as an addressable slave, it will operate in the Normal Multi- drop Operation Mode, NMM. -
Page 449: Synchronous Master Mode
Cortex ® -M0+ MCU HT32F52243/HT32F52253 RS485 Auto Address Detection Operation Mode – AAD Except in the Normal Multi-drop Operation Mode, the RS485 mode can operate in the Auto Address Detection Operation Mode, AAD, when it is configured as an addressable slave. This mode is enabled by setting the RSAAD filed to 1 in the RS485CR register. - Page 450 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 (CPS=1,WLS[1:0]=01, PBE=0) Clock (CPO=0) Clock (CPO=1) USART TX (From Start Stop Master to Slave) USART RX (From Slave to Master) (CPS=1,WLS[1:0]=00, PBE=1) Clock (CPO=0) Clock (CPO=1) USART TX (From Start Parity Stop...
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Page 451: Interrupts And Status
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 (CPS=0,WLS[1:0]=00, PBE=1) Clock (CPO=0) Clock (CPO=1) USART TX (From Start Parity Stop Master to Slave) USART RX (From Parity Slave to Master) Figure 166. 8-bit Format USART Synchronous Waveform Interrupts and Status... -
Page 452: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Map The following table shows the USART registers and reset values. Table 54. USART Register Map Register Offset Description Reset Value USRDR 0x000 USART Data Register 0x0000_0000 USRCR 0x004 USART Control Register... -
Page 453: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Descriptions USART Data Register – USRDR The register is used to access the USART transmitted and received FIFO data. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Type/Reset... -
Page 454: Usart Control Register - Usrcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 USART Control Register – USRCR The register specifies the serial parameters such as data length, parity, and stop bit for the USART. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Type/Reset... - Page 455 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [10] Number of "STOP bit" 0: One "STOP bit" is generated in the transmitted data 1: Two "STOP bit" is generated when 8- and 9-bit word length is selected.
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Page 456: Usart Fifo Control Register - Usrfcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 USART FIFO Control Register – USRFCR This register specifies the USART FIFO control and configurations including threshold level and reset function. Offset: 0x008 Reset value: 0x0000_0000 Reserved RXFS Type/Reset 0 RO 0 RO... -
Page 457: Usart Interrupt Enable Register - Usrier
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions TX FIFO Reset Setting this bit will generate a reset pulse to reset TX FIFO which will empty the TX FIFO. i.e., the TX pointer will be reset to 0, after a reset signal. This bit returns to 0 automatically after the reset pulse is generated. -
Page 458: Usart Status & Interrupt Flag Register - Usrsifr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions PEIE Parity Error Interrupt Enable 0: Disable interrupt. 1: Enable interrupt An interrupt is generated when the PEI bit is set in the USRSIFR register. OEIE Overrun Error Interrupt Enable 0: Disable interrupt. - Page 459 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions RSADD RS485 Address Detection 0: Address is not detected 1: Address is detected This bit is set to 1 when the receiver detects the address. An interrupt is generated if RSADDIE = 1 in the USRIER register.
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Page 460: Usart Timing Parameter Register - Usrtpr
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 USART Timing Parameter Register – USRTPR This register contains the USART timing parameters including the transmitter time guard parameters and the receive FIFO time-out value together with the RX FIFO time-out interrupt enable control. -
Page 461: Usart Irda Control Register - Irdacr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 USART IrDA Control Register – IrDACR This register is used to control the IrDA mode of USART. Offset: 0x018 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset IrDAPSC Type/Reset 0 RW 0 RW... -
Page 462: Usart Rs485 Control Register - Rs485Cr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 USART RS485 Control Register – RS485CR This register is used to control the RS485 mode of USART. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset ADDMATCH Type/Reset 0 RW 0 RW... -
Page 463: Usart Synchronous Control Register - Syncr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 USART Synchronous Control Register – SYNCR This register is used to control the USART synchronous mode. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Reserved CLKEN Type/Reset 0 RW... -
Page 464: Usart Divider Latch Register - Usrdlr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 USART Divider Latch Register – USRDLR The register is used to determine the USART clock divided ratio to generate the appropriate baud rate. Offset: 0x024 Reset value: 0x0000_0010 Reserved Type/Reset Reserved Type/Reset... -
Page 465: Usart Test Register - Usrtstr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 USART Test Register – USRTSTR This register controls the USART debug mode. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset 0 RW Bits Field Descriptions [1:0] Loopback Test Mode Select... -
Page 466: Universal Asynchronous Receiver Transmitter (Uart)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Univer sal Asynchr onous Receiver Transmitter (UART) Introduction The Universal Asynchronous Receiver Transceiver, UART, provides a flexible full duplex data exchange using asynchronous transfer. The UART is used to translate data between parallel and serial interfaces, and is also commonly used for RS232 standard communication. -
Page 467: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Features ▄ Supports asynchronous serial communication modes ▄ Full Duplex Communication Capability ▄ Programming baud rate up to 3 Mbit/s. ▄ Fully programmable serial communication functions including: ● Word length: 7, 8, or 9-bit character ●... -
Page 468: Baud Rate Generation
Cortex ® -M0+ MCU HT32F52243/HT32F52253 Baud Rate Generation The baud rate for the UART receiver and transmitter are both set with the same values. The baud-rate divisor, BRD, has the following relationship with the UART clock which is known as CK_UART. -
Page 469: Interrupts And Status
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Table 56. Baud Rate Deviation Error Calculation – CK_UART = 48 MHz. Baud rate CK_UART = 48 MHz Kbps Actual Deviation Error rate 20000 0.00% 5000 0.00% 19.2 19.2 2500 0.00% 57.6 57.6... -
Page 470: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Map The following table shows the UART registers and reset values. Table 57. UART Register Map Register Offset Description Reset Value URDR 0x000 UART Data Register 0x0000_0000 URCR 0x004 UART Control Register... -
Page 471: Uart Control Register - Urcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 UART Control Register – URCR The register specifies the serial parameters such as data length, parity, and stop bit for the UART. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved... - Page 472 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [9:8] Word Length Select 00: 7 bits 01: 8 bits 10: 9 bits 11: Reserved RXDMAEN UART RX DMA Enable 0: Disabled 1: Enabled TXDMAEN UART TX DMA Enable...
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Page 473: Uart Interrupt Enable Register - Urier
Cortex ® -M0+ MCU HT32F52243/HT32F52253 UART Interrupt Enable Register – URIER This register is used to enable the related UART interrupt function. The UART module generates interrupts to the controller when the corresponding events occur and the corresponding interrupt enable bits are set. -
Page 474: Uart Status & Interrupt Flag Register - Ursifr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 UART Status & Interrupt Flag Register – URSIFR This register contains the corresponding UART status. Offset: 0x010 Reset value: 0x0000_0180 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset TXDE Reserved RXDR Reserved Type/Reset 0 WC... -
Page 475: Uart Divider Latch Register - Urdlr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions Parity Error Indicator This bit is set to 1 whenever the received character does not have a valid "parity bit". Writing 1 to this bit clears the flag. Overrun Error Indicator An overrun error will occur only after the receive data register is full and when the next character has been completely received in the receive shift register. -
Page 476: Uart Test Register - Urtstr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 UART Test Register – URTSTR This register controls the UART debug mode. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset 0 RW Bits Field Descriptions [1:0] Loopback Test Mode Select... -
Page 477: Peripheral Direct Memory Access (Pdma)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Peripheral Direct Memory Access (PDMA) Introduction The Peripheral Direct Memory Access circuitry, PDMA, provides 6 unidirectional channels for dedicated peripherals to implement the peripheral-to-memory and memory-to-peripheral data transfer. The memory-to-memory data transfer such as the FLASH-to-SRAM or SRAM-to- SRAM type is also supported and requested by the application program. -
Page 478: Functional Description
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Functional Description AHB Master The PDMA is an AHB master connected to other AHB peripherals such as the FLASH memory, the SRAM memory and the AHB-to-APB bridges through the bus-matrix. The CPU and PDMA can access different AHB slaves at the same time via the bus-matrix. -
Page 479: Channel Transfer
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Table 58. PDMA Channel Assignments PDMA Channel Number SPIx (x = 0, 1) SPI0_RX SPI0_TX SPI1_RX SPI1_TX USARTx USR0_RX USR0_TX USR1_RX USR1_TX (x = 0, 1) UARTx UR1_RX UR1_TX UR2_RX UR2_TX UR0_RX... -
Page 480: Transfer Request
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Channel 0: priority=very high, block count=2, block length=2 Channel 1: priority=high, block count=3, block length=4 Channel 2: priority=low, block count=3, block length=6 Priority : CH0 > CH1 > CH2 Priority: CH1 > CH2 Priority: CH1 >... -
Page 481: Auto-Reload
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Linear Address Mode After data is transferred, the current address will be increased or decreased by 1, 2 or 4 depending upon the data bit width setting. Circular Address Mode After data is transferred, the current address will be increased or decreased by 1, 2 or 4 depending upon the data bit width setting. -
Page 482: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Map The following table shows the PDMA registers and the reset values. Table 60. PDMA Register Map Register Offset Description Reset Value PDMA Base Address = 0x4009_0000 PDMA Channel 0 Registers... -
Page 483: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Descriptions PDMA Channel n Control Register – PDMACHnCR, n = 0 ~ 5 This register is used to specify the PDMA channel n data transfer configuration. Offset: 0x000 (0), 0x018 (1), 0x030 (2), 0x048 (3), 0x060 (4), 0x078 (5) - Page 484 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions SRCAMODn Channel n Source Address Mode selection 0: Linear address mode 1: Circular address mode In the linear address mode, the current source address value can be incremented or decremented, determined by the SRCAINCn bit value during a complete transfer.
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Page 485: Pdma Channel N Source Address Register - Pdmachnsadr, N = 0 ~ 5
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 PDMA Channel n Source Address Register – PDMACHnSADR, n = 0 ~ 5 This register specifies the source address of the PDMA channel n. Offset: 0x004 (0), 0x01C (1), 0x034 (2), 0x04C (3), 0x064 (4), 0x07C (5) -
Page 486: Pdma Channel N Transfer Size Register - Pdmachntsr, N = 0 ~ 5
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 PDMA Channel n Transfer Size Register – PDMACHnTSR, n = 0 ~ 5 This register is used to specify the block transaction count and block transaction length. Offset: 0x010 (0), 0x028 (1), 0x040 (2), 0x058 (3), 0x070 (4), 0x088 (5) -
Page 487: Pdma Channel N Current Transfer Size Register - Pdmachnctsr, N = 0 ~ 5
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 PDMA Channel n Current Transfer Size Register – PDMACHnCTSR, n = 0 ~ 5 This register is used to indicate the current block transaction count. Address: 0x014 (0), 0x02C (1), 0x044 (2), 0x05C (3), 0x074 (4), 0x08C (5) - Page 488 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Bits Field Descriptions [29], [24], TEISTAn Channel n Transfer Error Interrupt Status (n = 0 ~ 5) 0: No Transfer Error occurs [19], [14], 1: Transfer Error occurs [9], [4] This bit is set by hardware and is cleared by writing a "1" into the corresponding interrupt status clear bit in the PDMAISR register.
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Page 489: Pdma Interrupt Status Clear Register - Pdmaiscr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 PDMA Interrupt Status Clear Register – PDMAISCR This register is used to clear the corresponding interrupt status bits in the PDMAISR Register. Offset: 0x128 Reset value: 0x0000_0000 Reserved TEICLR5 TCICLR5 HTICLR5 BEICLR5... -
Page 490: Pdma Interrupt Enable Register - Pdmaier
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 PDMA Interrupt Enable Register – PDMAIER This register is used to enable or disable the related interrupts of the PDMA channel 0 ~ 5. Offset: 0x130 Reset value: 0x0000_0000 Reserved TEIE5 TCIE5... -
Page 491: Cyclic Redundancy Check (Crc)
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Cyclic Redundancy Check (CRC) Introduction The CRC (Cyclic Redundancy Check) calculation unit is an error detection technique test algorithm and uses to verify data transmission or storage data correctness. A CRC calculation takes a data stream or a block of data as input and generates a 16-bit or 32-bit output remainder. -
Page 492: Function Descriptions
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Function Descriptions This unit only enables the calculation in the CRC16, CCITT CRC16 and IEEE-802.3 CRC32 polynomial. In this unit, the generator polynomial is fixed to the numeric values for those modes; therefore, the CRC value based on other generator polynomials cannot be calculated. -
Page 493: Crc With Pdma
Cortex ® -M0+ MCU HT32F52243/HT32F52253 CRC with PDMA A PDMA channel with software trigger may be used to transfer data into the CRC unit. If a huge block data is needed to calculate. The recommended PDMA model is to use the PDMA to transfer all available words of data and uses software writes to transfer the other remaining bytes. -
Page 494: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Descriptions CRC Control Register – CRCCR This register specifies the corresponding CRC function enable control. Offset : 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset SUMCMPL SUMBYRV SUMBIRV DATCMPL DATBYRV DATBIRV... -
Page 495: Crc Seed Register - Crcsdr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 CRC Seed Register – CRCSDR This register is used to specify the CRC seed. Offset: 0x004 Reset value: 0x0000_0000 SEED Type/Reset 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO... -
Page 496: Crc Data Register - Crcdr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 CRC Data Register – CRCDR This register is used to specify the CRC input data. Offset: 0x00C Reset value: 0x0000_0000 CRCDATA Type/Reset 0 WO 0 WO 0 WO 0 WO 0 WO... -
Page 497: Divider (Div)
® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Divider (DIV) Introduction In order to enhance the MCU performance, a divider is integrated in this device. The divider can implement the signed or unsigned 32-bit data division operation. An error flag will be generated when the divide by zero condition occurs. -
Page 498: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Register Map The following table shows the DIV registers and reset values. Table 62. DIV Register Map Register Offset Description Reset Value 0x000 Divider control register 0x0000_0008 0x004 Dividend data register 0x0000_0000... -
Page 499: Dividend Data Register - Ddr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Dividend Data Register – DDR The register is used to specify the dividend data. Offset: 0x004 Reset value: 0x0000_0000 Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW... -
Page 500: Quotient Data Register - Qtr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F52243/HT32F52253 Quotient Data Register – QTR The register is used to store the quotient data. Offset: 0x00C Reset value: 0x0000_0000 Type/Reset 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO... - Page 501 Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.
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