Timer Trigger Configuration Register - Trcfr; Table 29. Gptm Internal Trigger Connection - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Timer Trigger Configuration Register – TRCFR
This register specifies the trigger source selection of GPTM.
Offset: 0x008
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[3:0] TRSEL
Rev. 1.00
30 29 28
22 21 20
14 13 12
6 5 4
Reserved
Descriptions
Trigger Source Selection
These bits are used to select the trigger input (STI) for counter synchronization.
0000: Software Trigger by setting the UEVG bit
0001: Filtered input of channel 0 (TI0S0)
0010: Filtered input of channel 1 (TI1S1)
0011: Reserved
1000: Channel 0 Edge Detector (TI0BED)
1001: Internal Timing Module Trigger 0 (ITI0)
1010: Internal Timing Module Trigger 1 (ITI1)
1011: Internal Timing Module Trigger 2 (ITI2)
Others: Reserved
Note: These bits must be updated only when they are not in use, i.e. the slave mode
is disabled by setting the SMSEL field to 0x0.

Table 29. GPTM Internal Trigger Connection

Slave Timing Module
GPTM PWM0
217 of 486
27 26
Reserved
19 18
Reserved
11 10
Reserved
3 2
RW 0 RW
ITI0 ITI1
MCTM PWM1
25 24
17 16
9 8
1 0
TRSEL
0 RW 0 RW 0
ITI2
July 31, 2018