Holtek HT32F54231 User Manual

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Holtek 32-Bit Microcontroller with Arm

Cortex

-M0+ Core

HT32F54231/HT32F54241

HT32F54243/HT32F54253

User Manual

Revision: V1.00

Date: January 28, 2022

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Summary of Contents for Holtek HT32F54231

Page 1 Holtek 32-Bit Microcontroller with Arm ® Cortex ® -M0+ Core HT32F54231/HT32F54241 HT32F54243/HT32F54253 User Manual Revision: V1.00 Date: January 28, 2022...
Page 2: Table Of Contents
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Table of Contents 1 Introduction ......................25 Overview ..........................25 Features ..........................25 Device Information ....................... 30 Block Diagram ........................31 2 Document Conventions ..................33 3 System Architecture ..................... 34 ®...
Page 3 ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Flash Vector Mapping Control Register – VMCR ................63 Flash Manufacturer and Device ID Register – MDID ..............64 Flash Page Number Status Register – PNSR ................65 Flash Page Size Status Register – PSSR ..................66 Device ID Register –...
Page 4 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 AHB Configuration Register – AHBCFGR ..................96 AHB Clock Control Register – AHBCCR ..................97 APB Configuration Register – APBCFGR ..................99 APB Clock Control Register 0 – APBCCR0 .................. 100 APB Clock Control Register 1 – APBCCR1 .................. 102 Clock Source Status Register –...
Page 5 ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port A Output Set/Reset Control Register – PASRR ..............136 Port A Output Reset Register – PARR ..................137 Port B Data Direction Control Register – PBDIRCR ..............137 Port B Input Function Enable Control Register – PBINER ............138 Port B Pull-Up Selection Register –...
Page 6 ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 EXTI Source Selection Register 0 – ESSR0 ................171 EXTI Source Selection Register 1 – ESSR1 ................172 GPIO Port x Configuration Low Register – GPxCFGLR, x = A, B, C, D ........173 GPIO Port x Configuration High Register –...
Page 7 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Voltage Monitor ........................196 Register Map ........................196 Register Descriptions ......................197 ADC Conversion Control Register – ADCCR ................197 ADC Conversion List Register 0 – ADCLST0 ................199 ADC Conversion List Register 1 – ADCLST1 ................200 ADC Input Sampling Time Register –...
Page 8 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Master Controller .......................... 231 Channel Controller ........................232 Input Stage ........................... 234 Quadrature Decoder ........................236 Output Stage ..........................237 Update Management ........................241 Single Pulse Mode ........................242 Asymmetric PWM Mode ....................... 244 Timer Interconnection ........................
Page 9 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Functional Descriptions ..................... 287 Counter Mode ..........................287 Clock Controller ..........................291 Trigger Controller .......................... 292 Slave Controller ..........................293 Master Controller .......................... 295 Channel Controller ........................296 Input Stage ........................... 299 Output Stage ..........................
Page 10 ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 0 Asymmetric Compare Register – CH0ACR ..............364 Channel 1 Asymmetric Compare Register – CH1ACR ..............364 Channel 2 Asymmetric Compare Register – CH2ACR ..............365 Channel 3 Asymmetric Compare Register – CH3ACR ..............365 16 Single-Channel Timer (SCTM) .................
Page 11 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 BFTM Control Register – BFTMCR ....................397 BFTM Status Register – BFTMSR ....................398 BFTM Counter Value Register – BFTMCNTR ................399 BFTM Compare Value Register – BFTMCMPR ................399 18 Real Time Clock (RTC) ..................400 Introduction ........................
Page 12 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Data Transfer and Acknowledge ....................423 Clock Synchronization ........................423 Arbitration ............................. 424 General Call Addressing ....................... 424 Bus Error ............................424 Address Mask Enable ........................425 Address Snoop ..........................425 Operation Mode ..........................425 Conditions of Holding SCL Line ....................
Page 13 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 SPI FIFO Status Register – SPIFSR .................... 466 SPI FIFO Time Out Counter Register – SPIFTOCR ..............467 22 Universal Synchronous Asynchronous Receiver Transmitter (USART) ..468 Introduction ........................468 Features ..........................469 Functional Descriptions .....................
Page 14 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 UART Test Register – URTSTR ....................505 24 Peripheral Direct Memory Access (PDMA) ............. 506 Introduction ........................506 Features ..........................506 Functional Description ....................... 507 AHB Master ..........................507 PDMA Channel ..........................507 PDMA Request Mapping ......................
Page 15 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 CRC with PDMA ........................... 528 Register Map ........................528 Register Descriptions ......................528 CRC Control Register – CRCCR ....................528 CRC Seed Register – CRCSD ..................... 529 CRC Checksum Register – CRCCSR ..................530 CRC Data Register –...
Page 16 ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Touch Key Status Register – TKSR ....................561 Touch Key Module n Control Register – TKMnCR ............... 563 TKMn Key Configuration Register – TKMnKCFGR ..............565 Touch Key Module n Status Register – TKMnSR (n = 0 ~ 3) ............567 Touch Key Module n Reference Oscillator Capacitor Register –...
Page 17 List of Tables Table 1. Features and Peripheral List ..................... 30 Table 2. Document Conventions ......................33 Table 3. HT32F54231/HT32F54241 Register Map ................. 39 Table 4. HT32F54243/HT32F54253 Register Map ................. 40 Table 5. Flash Memory and Option Byte ....................45 Table 6.
Page 18 ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Table 40. Compare Match Output Setup ....................375 Table 41. SCTM Register Map ......................378 Table 42. BFTM Register Map ......................397 Table 43. LSE Startup Mode Operating Current and Startup Time ............401 Table 44.
Page 19 ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 List of Figures Figure 1. HT32F54231/HT32F54241 Block Diagram ................31 Figure 2. HT32F54243/HT32F54253 Block Diagram ................32 Figure 3. Cortex ® -M0+ Block Diagram ....................35 Figure 4. Bus Architecture ........................36 Figure 5. HT32F54231/HT32F54241 Memory Map ................37 Figure 6.
Page 20 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Figure 40. Up-counting Example ......................225 Figure 41. Down-counting Example ...................... 225 Figure 42. Center-aligned Counting Example ..................226 Figure 43. GPTM Clock Source Selection .................... 227 Figure 44. Trigger Controller Block ....................... 228 Figure 45.
Page 21 ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Figure 81. MCTM in Restart Mode ....................... 293 Figure 82. MCTM in Pause Mode ......................294 Figure 83. MCTM in Trigger Mode ......................294 Figure 84. Master MCTMn and Slave GPTMm Connection ..............295 Figure 85.
Page 22 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Figure 121. SCTM in Restart Mode ...................... 370 Figure 122. SCTM in Pause Mode ....................... 371 Figure 123. SCTM in Trigger Mode ...................... 371 Figure 124. Capture/Compare Block Diagram ..................372 Figure 125. Input Capture Mode ......................373 Figure 126.
Page 23 ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Figure 162. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 1 ........450 Figure 163. SPI Dual Mode Bit Sequence – CPOL = 0, CPHA = 0, DFL = 0x8 (16-bit), MSB Transmitted First ................................
Page 24 Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Figure 200. Touch Key Interrupts ......................551 Figure 201. Touch Key Manual Scan Mode Flowchart – TKMOD[1:0] = 01 ......... 551 Figure 202. Touch Key Auto Scan Mode Flowchart – TKMOD[1:0] = 00 ..........552 Figure 203.
Page 25: Introduction
HT32F54231/HT32F54241/HT32F54243/HT32F54253 Introduction Overview This user manual provides detailed information including how to use the HT32F54231/ HT32F54241/HT32F54243/HT32F54253 devices, system and bus architecture, memory organization and peripheral instructions. The target audiences for this document are software developers, application developers and hardware developers. For more information regarding pin assignment, package and electrical characteristics, please refer to the HT32F54231/HT32F54241/ HT32F54243/HT32F54253 datasheet.
Page 26 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Reset Control Unit – RSTCU ▆ ● Supply supervisor: ♦ Power-On Reset / Power-Down Reset – POR / PDR ♦ Brown-Out Detector – BOD ♦ Programmable Low Voltage Detector – LVD Clock Control Unit – CKCU ▆...
Page 27 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 I/O Ports – GPIO ▆ ● Up to 54 GPIOs ● Port A, B, C, D are mapped on 16 external interrupts – EXTI ● Almost all I/O pins have configurable output driving current Motor Control Timer –...
Page 28 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Inter-integrated Circuit – I ▆ ● Supports both master and slave modes with a frequency of up to 1 MHz ● Provides an arbitration function and clock synchronization ● Supports 7-bit and 10-bit addressing modes and general call addressing ●...
Page 29 Hardware Upper or lower threshold comparators ● Keys are organised into several groups, with each group known as a module For the HT32F54231/HT32F54241, having a module number, M0 to M5 ♦ For the HT32F54243/HT32F54253, having a module number, M0 to M6 ♦...
Page 30: Device Information
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Device Information Table 1. Features and Peripheral List Peripherals HT32F54231 HT32F54241 HT32F54243 HT32F54253 Main Flash (KB) Option Bytes Flash (KB) SRAM (KB) MCTM GPTM SCTM Timers BFTM USART Communication UART Hardware Divider...
Page 31: Block Diagram
32 kHz Touch key TKEY23 WAKEUP VDDA 32,768 Hz VSSA nRST Powered by V Powered by V CORE X32KIN X32KOUT Power supply: Bus: Control signal: Alternate function: Figure 1. HT32F54231/HT32F54241 Block Diagram Rev. 1.00 31 of 576 January 28, 2022...
Page 32: Figure 2. Ht32F54243/Ht32F54253 Block Diagram
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 PA ~ PC[15:0], PD[5:0] SWCLK SWDIO BOOT Powered by V Powered by V CORE /PDR Flash Memory Flash SW-DP XTALIN Interface Memory XTALOUT 4 ~ 16 MHz ® Cortex -M0+ ULDO Processor...
Page 33: Document Conventions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Document Conventions The conventions used in this document are shown in the following table. Table 2. Document Conventions Notation Example Description The number string with a 0x prefix indicates a hexadecimal 0x5a05 number.
Page 34: System Architecture
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 System Architecture The system architecture of the device that includes the Arm Cortex -M0+ processor, bus ® ® architecture and memory organization will be described in the following sections. The Cortex ®...
Page 35: Bus Architecture
-M0+ Block Diagram Bus Architecture The HT32F54231/HT32F54241 series consist of one master and four slaves in the bus architecture. The HT32F54243/HT32F54253 series consist of two masters and four slaves in the bus architecture. The system bus and Peripheral Direct Memory Access (PDMA) are the masters while the internal SRAM access bus, the internal Flash memory access bus, the AHB peripherals access bus and the AHB to APB bridge are the slaves.
Page 36: Memory Organization
-M0+ system peripherals. Refer to the Arm ® Cortex ® -M0+ Technical Reference Manual for more information. The following figure shows the memory map of the HT32F54231/HT32F54241/HT32F54243/HT32F54253 series of devices, including Code, SRAM, peripheral, and other pre-defined regions. Rev. 1.00 36 of 576 January 28, 2022...
Page 37: Memory Map
0x1F00_0000 0x4001_B000 Reserved Reserved 0x4001_A000 TKEY 0x0001_0000 0x4001_1000 Reserved 0x4001_0000 0x4000_5000 Reserved 64 KB 0x4000_4000 SPI0 64 KB on-chip Flash 0x4000_2000 Reserved 0x4000_1000 UART0 0x0000_0000 0x4000_0000 USART Figure 5. HT32F54231/HT32F54241 Memory Map Rev. 1.00 37 of 576 January 28, 2022...
Page 38: Figure 6. Ht32F54243/Ht32F54253 Memory Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 0x400F_FFFF 0xFFFF_FFFF Reserved 0x400C_C000 0x400C_A000 Reserved 0x400B_8000 Reserved GPIO A ～ D 0x400B_0000 Reserved 0x4009_2000 PDMA_REG 0x4009_0000 0x4008_C000 Reserved 0xE010_0000 0x4008_A000 Private peripheral bus 0x4008_8000 CKCU & RSTCU 0xE000_0000 0x4008_2000 Reserved 0x4008_0000...
Page 39: Table 3. Ht32F54231/Ht32F54241 Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Table 3. HT32F54231/HT32F54241 Register Map Start Address End Address Peripheral 0x4000_0000 0x4000_0FFF USART 0x4000_1000 0x4000_1FFF UART0 0x4000_2000 0x4000_3FFF Reserved 0x4000_4000 0x4000_4FFF SPI0 0x4000_5000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF 0x4001_1000 0x4001_9FFF Reserved 0x4001_A000 0x4001_AFFF...
Page 40: Table 4. Ht32F54243/Ht32F54253 Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Start Address End Address Peripheral 0x4008_0000 0x4008_1FFF 0x4008_2000 0x4008_7FFF Reserved 0x4008_8000 0x4008_9FFF CKCU & RSTCU 0x4008_A000 0x4008_BFFF 0x4008_C000 0x400A_FFFF Reserved 0x400B_0000 0x400B_1FFF GPIO A 0x400B_2000 0x400B_3FFF GPIO B 0x400B_4000 0x400B_5FFF GPIO C...
Page 41 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Start Address End Address Peripheral 0x4005_9000 0x4005_9FFF Reserved 0x4005_A000 0x4005_AFFF LEDC 0x4005_B000 0x4006_7FFF Reserved 0x4006_8000 0x4006_8FFF 0x4006_9000 0x4006_9FFF Reserved 0x4006_A000 0x4006_AFFF RTC & PWRCU 0x4006_B000 0x4006_DFFF Reserved 0x4006_E000 0x4006_EFFF GPTM 0x4006_F000 0x4007_3FFF...
Page 42: Embedded Flash Memory
Programming (ISP), In Application Programming (IAP) or In Circuit Programming (ICP). For more information, refer to the Flash Memory Controller section. Embedded SRAM Memory The HT32F54231/HT32F54241/HT32F54243/HT32F54253 device series contain an up to 16 KB on-chip SRAM which is located at address 0x2000_0000. It supports byte, half-word and word access operations.
Page 43: Flash Memory Controller (Fmc)
● 64 KB (instruction/data + Option Byte) for the HT32F54241 and HT32F54243 ● 32 KB (instruction/data + Option Byte) for the HT32F54231 Page size of 1 KB, totally up to 128 pages depending on the main Flash size ▆ Wide access interface with a pre-fetch buffer to reduce instruction gaps ▆...
Page 44: Functional Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Functional Descriptions Flash Memory Map The following figure is the Flash memory map of the system. The address ranges from 0x0000_0000 to 0x1FFF_FFFF (0.5 GB). The address from 0x1F00_0000 to 0x1F00_07FF is mapped to the Boot Loader Block with a capacity of 2 KB.
Page 45: Flash Memory Architecture
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Flash Memory Architecture The Flash memory consists of up to 128 KB main Flash Block with 1 KB per page and 2 KB Information Block for Boot Loader. The main Flash memory contains a total of 128 pages (or 64 pages for 64 KB device and so on) which can be erased individually.
Page 46: Booting Configuration
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Booting Configuration The system provides two kinds of booting modes which can be selected using the BOOT pin. The BOOT pin status is sampled during the power-on reset or system reset. Once the logic value is decided, the first 4 words of vector will be remapped to the corresponding source according to the booting mode.
Page 47: Figure 10. Page Erase Operation Flowchart
® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Note that a correct address of the target page must be confirmed. The software may run out of control if the target erase page is under the code fetching or data accessing status. The FMC will not provide any notification when this happens.
Page 48: Mass Erase
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Mass Erase The FMC provides a mass erase function which is used to initialize all the main Flash memory contents to a high state. The following steps show the mass erase operation register access sequence.
Page 49: Word Programming
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Word Programming The FMC provides a 32-bit word programming function which is used to modify the Flash memory contents. The following steps show the word programming operation register access sequence. 1. Check the OPCR register to confirm that no Flash memory operation is in progress (OPM [3:0] is equal to 0xE or 0x6).
Page 50: Option Byte Description
0x008 Reserved 0xFFFF_FFFF 0x00C For the HT32F54231 the variable “X” is equal to 31. 0xFFFF_FFFF For the HT32F54241 the variable “X” is equal to 62. For the HT32F54243 the variable “X” is equal to 63. For the HT32F54253 the variable “X” is equal to 126.
Page 51: Page Erase/Program Protection
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Page Erase/Program Protection The FMC provides a page erase/program protection function to prevent unexpected operations on the protected Flash memory area. The page erase (CMD [3:0] = 0x8 in the OCMR register) or word programming (CMD [3:0] = 0x4) command will not be accepted by the FMC on the protected pages.
Page 52: Security Protection
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Security Protection The FMC provides a security protection function to prevent illegal code/data access to the Flash memory. This function is useful for protecting the software/firmware from illegal users. The function is activated by setting OB_CP [0] in the Option Byte. Once the function has been enabled, all the main Flash data access through ICP/Debug mode, programming and page erase operation will not be allowed except the user’s application.
Page 53: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Map The following table shows the FMC registers and reset values. Table 11. FMC Register Map Register Offset Description Reset Value TADR 0x000 Flash Target Address Register 0x0000_0000 WRDR 0x004 Flash Write Data Register...
Page 54: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Descriptions Flash Target Address Register – TADR This register specifies the target address of the page erase and word programming operations. Offset: 0x000 Reset value: 0x0000_0000 TADB Type/Reset 0 RW 0 RW...
Page 55: Flash Write Data Register - Wrdr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Flash Write Data Register – WRDR This register specifies the data to be written for the programming operation. Offset: 0x004 Reset value: 0x0000_0000 WRDB Type/Reset 0 RW 0 RW 0 RW 0 RW...
Page 56: Flash Operation Command Register - Ocmr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Flash Operation Command Register – OCMR This register is used to specify the Flash operation commands that include word programming, page erase and mass erase. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset...
Page 57: Flash Operation Control Register - Opcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Flash Operation Control Register – OPCR This register is used for controlling the command commitment and checking the status of the FMC operations. Offset: 0x010 Reset value: 0x0000_000C Reserved Type/Reset Reserved Type/Reset...
Page 58: Flash Operation Interrupt Enable Register - Oier
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Flash Operation Interrupt Enable Register – OIER This register is used to enable or disable the FMC interrupt function. The FMC will generate the interrupt when the corresponding interrupt enable bit is set and the interrupt condition occurs.
Page 59: Flash Operation Interrupt And Status Register - Oisr
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Flash Operation Interrupt and Status Register – OISR This register indicates the FMC interrupt status which is used to check if a Flash operation has been finished or if an error has occurred. The status bits, bit [4:0], if set high, are available to trigger the interrupts when the corresponding enable bits in the OIER register are set high.
Page 60 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions OBEF Option Byte Checksum Error Flag 0: Option Byte checksum is correct 1: Option Byte checksum is incorrect This bit will be set high when the Option Byte checksum is incorrect. The Option Byte Checksum Error interrupt will be generated if the OBEIEN bit in the OIER register is set.
Page 61: Flash Page Erase/Program Protection Status Register - Ppsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Flash Page Erase/Program Protection Status Register – PPSR This register indicates the page protection status of the Flash page erase/program protection functions. Offset: 0x020 (0) ~ 0x02C (3) Reset value: 0xXXXX_XXXX PPSBn...
Page 62: Flash Security Protection Status Register - Cpsr
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Flash Security Protection Status Register – CPSR This register indicates the Flash memory security protection status. The content of this register is not dynamically updated and will only be reloaded by the Option Byte loader which is activated when any kind of reset occurs.
Page 63: Flash Vector Mapping Control Register - Vmcr
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Flash Vector Mapping Control Register – VMCR This register is used to control the vector mapping. The reset value of the VMCR register is determined by the external booting pin, BOOT, during the power-on reset period.
Page 64: Flash Manufacturer And Device Id Register - Mdid
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Flash Manufacturer and Device ID Register – MDID This register specifies the manufacture ID and device part number information which can be used as the product identity. Offset: 0x180 Reset value: 0x0376_XXXX...
Page 65: Flash Page Number Status Register - Pnsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Flash Page Number Status Register – PNSR This register indicates the Flash memory page number. Offset: 0x184 Reset value: 0x0000_00XX PNSB Type/Reset 0 RO 0 RO 0 RO 0 RO 0 RO...
Page 66: Flash Page Size Status Register - Pssr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Flash Page Size Status Register – PSSR This register indicates the page size in bytes. Offset: 0x188 Reset value: 0x0000_0400 PSSB Type/Reset 0 RO 0 RO 0 RO 0 RO 0 RO...
Page 67: Flash Pre-Fetch Control Register - Cfcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Flash Pre-fetch Control Register – CFCR This register is used for controlling the FMC pre-fetch module. Offset: 0x200 Reset value: 0x0000_0011 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved PFBE Reserved WAIT Type/Reset...
Page 68: Custom Id Register N - Cidrn (N = 0 ~ 3)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Custom ID Register n – CIDRn (n = 0 ~ 3) This register specifies the custom ID information which can be used as the custom identity. Offset: 0x310 (0) ~ 0x31C (3) Reset value: 0xXXXX_XXXX –...
Page 69: Power Control Unit (Pwrcu)
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Power Control Unit (PWRCU) Introduction The power consumption can be regarded as one of the most important issues for many embedded system applications. Accordingly the Power Control Unit, PWRCU, provides many types of power saving modes such as Sleep, Deep-Sleep1 and Deep-Sleep2 modes.
Page 70: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Features Two power domains: V and V power domains ▆ CORE Three power saving modes: Sleep, Deep-Sleep1 and Deep-Sleep2 modes ▆ Internal Voltage regulator supplies V voltage source ▆ CORE Additional ultra-low power voltage regulator supplies V voltage source with low static ▆...
Page 71: Figure 14. Power-On Reset / Power-Down Reset Waveform
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Hysteresis Time POR Delay Time RSTD RESET Figure 14. Power-On Reset / Power-Down Reset Waveform Low Voltage Detector / Brown-Out Detector The Low Voltage Detector, LVD, can detect whether the supply voltage V...
Page 72: Vcore Power Domain
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Power Domain CORE The main functions that include high speed internal oscillator, HSI, MCU core logic, AHB/APB peripherals and memories and so on are located in this power domain. Once the V...
Page 73: Table 13. Enter/Exit Power Saving Modes
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Table 13. Enter/Exit Power Saving Modes Mode Entry Mode Mode Exit LDOOFF ULDOON Instruction SLEEPDEEP WFI: Any interrupt WFE: Any wakeup event Sleep Any interrupt (NVIC on) or Any interrupt with SEVONPEND = 1...
Page 74: Register Map
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 WAKEUPn Pin Wakeup The software can set the WUPnEN bit in register PWRCR to 1 to enable the WAKEUPn pin function before entering the power saving mode, waiting for a wakeup trigger signal occurrence on the WAKEUPn pin to wake up the system from the power saving mode.
Page 75: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Descriptions Power Control Status Register – PWRSR This register indicates power control status. Offset: 0x100 Reset value: 0x0000_0010 (Reset only by V domain power on reset) CORE Reserved Type/Reset Reserved Type/Reset...
Page 76: Power Control Register - Pwrcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Power Control Register – PWRCR This register provides power control bits for the different kinds of power saving modes. Offset: 0x104 Reset value: 0x0000_0000 Reserved Type/Reset Reserved WUP1TYPE WUP0TYPE Type/Reset 0 RW...
Page 77 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions WUP0EN External WAKEUP0 Pin Enable 0: Disable WAKEUP0 pin function 1: Enable WAKEUP0 pin function The software can set the WUP0EN bit as 1 to enable the WAKEUP0 pin function before entering the power saving mode.
Page 78: Low Voltage / Brown Out Detect Control And Status Register - Lvdcsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Low Voltage / Brown Out Detect Control and Status Register – LVDCSR This register specifies flags, enable bits and option bits for low voltage detector. Offset: 0x110 Reset value: 0x0000_0000 Reserved Type/Reset...
Page 79: Power Control Ldo Status Register - Pwrldosr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [16] LVDEN Low Voltage Detect Enable 0: Disable Low Voltage Detect 1: Enable Low Voltage Detect Setting this bit to 1 will generate an LVD event when the V power is equal to or lower than the voltage set by LVDS bits.
Page 80: Clock Control Unit (Ckcu)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Clock Control Unit (CKCU) Introduction The Clock Control unit, CKCU, provides functions of High Speed Internal RC oscillator (HSI), High Speed External crystal oscillator (HSE), Low Speed Internal RC oscillator (LSI), Low Speed External crystal oscillator (LSE), Phase Lock Loop (PLL), HSE clock monitor, clock prescaler, clock multiplexer and clock gating.
Page 81: Figure 15. Ckcu Block Diagram
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 CKREFPRE Prescaler Divider CK_REF CK_LSE ÷ 1 ~ 32 ÷ 2 HSI Auto CKREFEN Trimming Controller CK_IN STCLK ÷ 8 (to SysTick) 8 MHz PLLSRC HSI RC CK_GPIO PAEN PLLEN ( to GPIO port)
Page 82: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Features 4 ~ 16 MHz external crystal oscillator (HSE) ▆ Internal 8 MHz RC oscillator (HSI) with configuration option calibration and custom trimming ▆ capability PLL with selectable clock source (from HSE or HSI) for system clock ▆...
Page 83: High Speed Internal Rc Oscillator - Hsi
The frequency accuracy of the high speed internal RC oscillator HSI can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by Holtek for ±2 % accuracy at V = 5.0 V and T = 25 °C.
Page 84: Figure 17. Hsi Auto Trimming Block Diagram
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Auto Trimming HSI Block Diagram Fine-Trimming Write Register ATCEN Counter Auto Trimming Register Controller TMSEL External pin (CKIN) 1 kHz /1.024 kHz 32.768 kHz REFCLKSEL Fine-Trimming Factory Read Register Trimming Bits HSIFINE [7:0]...
Page 85: Phase Locked Loop - Pll
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Phase Locked Loop – PLL This PLL can provide a 4 ~ 60 MHz clock output which is 1 ~ 15 multiples of a fundamental reference frequency of 4 ~ 16 MHz. The rationale of the clock synthesizer relies on the digital Phase...
Page 86: Low Speed External Crystal Oscillator - Lse
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Table 17. Feedback Divider 2 Value Mapping Feedback Divider 2 Setup Bits B3 ~ B0 (PFBD Field in the PLLCFGR Register) (Feedback Divider 2 Value) 0000 0001 0010 0011 0100 0101 0110...
Page 87: Low Speed Internal Rc Oscillator - Lsi
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Low Speed Internal RC Oscillator – LSI The low speed internal RC oscillator with a frequency of about 32 kHz produces a low power clock source for the circuits of Real-Time-Clock peripheral, Watchdog Timer or system clock. The LSI is also a low cost clock source because no external component is needed to make it oscillate.
Page 88: Hse Clock Monitor
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 HSE Clock Monitor The main function of the oscillator check is enabled by the HSE Clock Monitor Enable bit CKMEN in the Global Clock Control Register (GCCR). The HSE clock monitor should be enabled after the HSE oscillator start-up delay and be disabled when the HSE oscillator is stopped.
Page 89: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Map The following table shows the CKCU registers and reset values. Table 19. CKCU Register Map Register Offset Description Reset Value GCFGR 0x000 Global Clock Configuration Register 0x0000_0302 GCCR 0x004 Global Clock Control Register...
Page 90: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Descriptions Global Clock Configuration Register – GCFGR This register specifies the clock source for PLL/CKOUT. Offset: 0x000 Reset value: 0x0000_0302 LPMOD Reserved Type/Reset 0 WC 0 RO Reserved Type/Reset CKREFPRE Reserved...
Page 91: Global Clock Control Register - Gccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Global Clock Control Register – GCCR This register specifies the clock enable bits. Offset: 0x004 Reset value: 0x0000_0803 Reserved Type/Reset Reserved PSRCEN CKMEN Type/Reset 0 RW Reserved HSIEN HSEEN PLLEN HSEGAIN Type/Reset...
Page 92: Global Clock Status Register - Gcsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions HSEGAIN External High Speed Clock Gain Selection 0: HSE low gain mode 1: HSE high gain mode [2:0] System Clock Switch 00x: CK_PLL clock out as system clock 010: CK_HSE as system clock...
Page 93: Global Clock Interrupt Register - Gcir
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions HSIRDY Internal High Speed Clock Ready Flag 0: Internal 8 MHz RC oscillator clock is not ready 1: Internal 8 MHz RC oscillator clock is ready Set by hardware to indicate whether the HSI is stable or not.
Page 94: Pll Configuration Register - Pllcfgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 PLL Configuration Register – PLLCFGR This register specifies PLL configuration. Offset: 0x018 Reset value: 0x0000_0000 Reserved REFDIV Reserved PFBD Type/Reset 0 RW 0 RW PFBD POTD Reserved Type/Reset 0 RW 0 RW...
Page 95: Pll Control Register - Pllcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 PLL Control Register – PLLCR This register specifies Bypass mode control of PLL. Offset: 0x01C Reset value: 0x0000_0000 PLLBPS Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Bits Field Descriptions [31] PLLBPS...
Page 96: Ahb Configuration Register - Ahbcfgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 AHB Configuration Register – AHBCFGR This register specifies the system clock frequency. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved AHBPRE Type/Reset 0 RW 0 RW Bits Field...
Page 97: Ahb Clock Control Register - Ahbccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 AHB Clock Control Register – AHBCCR This register specifies clock enable bits of AHB peripherals. Offset: 0x024 Reset value: 0x0000_0065 Reserved DIVEN Type/Reset Reserved PDEN PCEN PBEN PAEN Type/Reset 0 RW 0 RW...
Page 98 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions APBEN APB bridge Clock Enable 0: APB bridge clock is automatically disabled by hardware during Sleep mode 1: APB bridge clock is always enabled during Sleep mode Set and reset by software. Users can set APBEN as 0 to reduce power consumption if the APB bridge is unused during Sleep mode.
Page 99: Apb Configuration Register - Apbcfgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 APB Configuration Register – APBCFGR This register specifies the ADC conversion clock frequency. Offset: 0x028 Reset value: 0x0001_0000 Reserved Type/Reset Reserved ADCDIV Type/Reset 0 RW 0 RW Reserved Type/Reset Reserved Type/Reset Bits...
Page 100: Apb Clock Control Register 0 - Apbccr0
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 APB Clock Control Register 0 – APBCCR0 This register specifies clock enable bits of APB peripherals. Offset: 0x02C Reset value: 0x0000_0000 Reserved LEDC Reserved Type/Reset Reserved Type/Reset EXTIEN AFIOEN UR3EN UR2EN UR1EN...
Page 101 0: USART0 clock is disabled 1: USART0 clock is enabled Set and reset by software. Since there is only one USART in the HT32F54231/HT32F54241 devices, the pins, registers and control bits related to the USART do not have the serial number “0”. SPI1EN...
Page 102: Apb Clock Control Register 1 - Apbccr1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 APB Clock Control Register 1 – APBCCR1 This register specifies clock enable bits of APB peripherals. Offset: 0x030 Reset value: 0x0000_0000 SCTM3EN SCTM2EN SCTM1EN SCTM0EN Reserved ADCCEN Type/Reset RW 0 RW 0 RW...
Page 103 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [18] TOUCHKEYEN Touch Key Clock Enable 0: Touch Key clock is disabled 1: Touch Key clock is enabled Set and reset by software. [17] BFTM1EN BFTM1 Clock Enable 0: BFTM1 clock is disabled 1: BFTM1 clock is enabled Set and reset by software.
Page 104: Clock Source Status Register - Ckst
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Clock Source Status Register – CKST This register specifies status of various clock sources. Offset: 0x034 Reset value: 0x0100_0003 Reserved HSIST Type/Reset 0 RO 0 RO 0 RO Reserved HSEST Type/Reset 0 RO...
Page 105: Apb Peripheral Clock Selection Register 0 - Apbpcsr0
11: PCLK = CK_AHB / 8 PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock Since there is only one USART in the HT32F54231/HT32F54241 devices, the pins, registers and control bits related to the USART do not have the serial number “0”.
Page 106 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [21:20] GPTMPCLK GPTM Peripheral Clock Selection 00: PCLK = CK_AHB 01: PCLK = CK_AHB / 2 10: PCLK = CK_AHB / 4 11: PCLK = CK_AHB / 8 PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock...
Page 107: Apb Peripheral Clock Selection Register 1 - Apbpcsr1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [3:2] I2C1PCLK C1 Peripheral Clock Selection 00: PCLK = CK_AHB 01: PCLK = CK_AHB / 2 10: PCLK = CK_AHB / 4 11: PCLK = CK_AHB / 8 PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock...
Page 108 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [27:26] SCTM1PCLK SCTM1 Peripheral Clock Selection 00: PCLK = CK_AHB 01: PCLK = CK_AHB / 2 10: PCLK = CK_AHB / 4 11: PCLK = CK_AHB / 8 PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock...
Page 109: Hsi Control Register - Hsicr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [1:0] AFIOPCLK AFIO Peripheral Clock Selection 00: PCLK = CK_AHB 01: PCLK = CK_AHB / 2 10: PCLK = CK_AHB / 4 11: PCLK = CK_AHB / 8 PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock HSI Control Register –...
Page 110: Hsi Auto Trimming Counter Register - Hsiatcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions TMSEL Trimming Mode Selection 0: Automatic by Auto Trimming Controller 1: Manual by user program This bit is used to select the HSI RC oscillator trimming function by ATC hardware or user programming via the HSIFINE field in this register.
Page 111: Apb Peripheral Clock Selection Register 2 - Apbpcsr2
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 APB Peripheral Clock Selection Register 2 – APBPCSR2 This register specifies the APB peripheral clock prescaler selection. Offset: 0x048 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TOUCHKEYPCLK Reserved Type/Reset 0 RW...
Page 112: Mcu Debug Control Register - Mcudbgcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 MCU Debug Control Register – MCUDBGCR This register specifies the debug control of MCU. Offset: 0x304 Reset value: 0x0000_0000 Reserved DBLEDC DBI2C2 DBUR3 DBUR2 DBSCTM3 DBSCTM2 Type/Reset RW 0 0 RW 0 RW...
Page 113 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [23] DBSCTM1 SCTM1 Debug Mode Enable 0: SCTM1 counter continues even if the core is halted 1: SCTM1 counter is stopped when the core is halted Set and reset by software.
Page 114 1: USART0 FIFO timeout is frozen when the core is halted Set and reset by software. Since there is only one USART in the HT32F54231/HT32F54241 devices, the pins, registers and control bits related to the USART do not have the serial number “0”.
Page 115: Reset Control Unit (Rstcu)
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Reset Control Unit (RSTCU) Introduction The Reset Control Unit, RSTCU, has three kinds of reset, the power-on reset, system reset and APB unit reset. The power-on reset, known as a cold reset, resets the full system during a power up.
Page 116: System Reset
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 DD33 CORE PORRESETn SYSRESETn = 25 μs *Typical. = 100 μs = 150 μs * This timing is dependent on the internal LDO regulator output capacitor value. Figure 21. Power-On Reset Sequence...
Page 117: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Descriptions Global Reset Status Register – GRSR This register specifies a variety of reset status conditions. Offset: 0x100 Reset value: 0x0000_0008 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved PORSTF WDTRSTF EXTRSTF NVICRSTF...
Page 118: Ahb Peripheral Reset Register - Ahbprstr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 AHB Peripheral Reset Register – AHBPRSTR This register specifies several AHB peripherals software reset control bits. Offset: 0x104 Reset value: 0x0000_0000 Reserved DIVRST Type/Reset Reserved Type/Reset Reserved PDRST PCRST PBRST PARST Type/Reset...
Page 119: Apb Peripheral Reset Register 0 - Apbprstr0
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 APB Peripheral Reset Register 0 – APBPRSTR0 This register specifies several APB peripherals software reset control bits. Offset: 0x108 Reset value: 0x0000_0000 Reserved LEDCRST Reserved Type/Reset Reserved Type/Reset EXTIRST AFIORST UR3RST UR2RST...
Page 120 This bit is set by software and cleared to 0 by hardware automatically. Since there is only one USART in the HT32F54231/HT32F54241 devices, the pins, registers and control bits related to the USART do not have the serial number “0”.
Page 121: Apb Peripheral Reset Register 1 - Apbprstr1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 APB Peripheral Reset Register 1 – APBPRSTR1 This register specifies several APB peripherals software reset control bits. Offset: 0x10C Reset value: 0x0000_0000 SCTM3RST SCTM2RST SCTM1RST SCTM0RST Reserved ADCRST Type/Reset RW 0 RW...
Page 122 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [17] BFTM1RST BFTM1 Reset Control 0: No reset 1: Reset BFTM1 This bit is set by software and cleared to 0 by hardware automatically. [16] BFTM0RST BFTM0 Reset Control...
Page 123: General Purpose I/O (Gpio)
There are up to 40 General Purpose I/O ports, GPIO, named PA0 ~ PA15, PB0 ~ PB15 and PC0 ~ PC7 for the HT32F54231/HT32F54241 devices and up to 54 General Purpose I/O ports, GPIO, named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15 and PD0 ~ PD5 for the HT32F54243/HT32F54253 devices to implement the logic input/output functions.
Page 124: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Features Input/output direction control ▆ Schmitt Trigger Input function enable control ▆ Input weak pull-up/pull-down control ▆ Output push-pull/open-drain enable control ▆ Output set/reset control ▆ Output drive current selection ▆ External interrupt with programmable trigger edge – using EXTI configuration registers ▆...
Page 125: Table 21. Afio, Gpio And I/O Pad Control Signal True Table
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 PxCFGn Input DMUX Output AFIO Control IOPAD AFIO ADEN PxDOUTn PxDINn PxRSTn PxDVn PxINENn PxSETn PxODn PxDIRn PxPDn PxPUn GPIO Figure 23. AFIO/GPIO Control Signal PxDINn/PxDOUTn (x = A ~ D): Data Input/Data Output...
Page 126: Gpio Locking Mechanism
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 GPIO Locking Mechanism The GPIO also offers a lock function to lock the port until a reset event occurs. The PxLOCKR (x = A ~ D) registers are used to lock the port x and lock control options. The value 0x5FA0 is...
Page 127 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Offset Description Reset Value PCDINR 0x01C Port C Data Input Register 0x0000_0000 PCDOUTR 0x020 Port C Data Output Register 0x0000_0000 PCSRR 0x024 Port C Output Set/Reset Control Register 0x0000_0000 PCRR 0x028...
Page 128: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Descriptions Port A Data Direction Control Register – PADIRCR This register is used to control the direction of the GPIO Port A pin as input or output. Offset: 0x000 Reset value: 0x0000_0000...
Page 129: Port A Input Function Enable Control Register - Painer
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port A Input Function Enable Control Register – PAINER This register is used to enable or disable the GPIO Port A input function. Offset: 0x004 Reset value: 0x0000_0200 Reserved Type/Reset Reserved Type/Reset...
Page 130: Port A Pull-Up Selection Register - Papur
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port A Pull-Up Selection Register – PAPUR This register is used to enable or disable the GPIO Port A pull-up function. Offset: 0x008 Reset value: 0x0000_3200 Reserved Type/Reset Reserved Type/Reset PAPU Type/Reset...
Page 131: Port A Pull-Down Selection Register - Papdr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port A Pull-Down Selection Register – PAPDR This register is used to enable or disable the GPIO Port A pull-down function. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PAPD Type/Reset...
Page 132: Port A Open-Drain Selection Register - Paodr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port A Open-Drain Selection Register – PAODR This register is used to enable or disable the GPIO Port A open-drain function. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PAOD Type/Reset...
Page 133: Port A Drive Current Selection Register - Padrvr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port A Drive Current Selection Register – PADRVR This register specifies the GPIO Port A output driving current. Offset: 0x014 Reset value: 0x0000_0000 PADV15 PADV14 PADV13 PADV12 Type/Reset 0 RW 0 RW...
Page 134: Port A Lock Register - Palockr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port A Lock Register – PALOCKR This register specifies the GPIO Port A lock configuration. Offset: 0x018 Reset value: 0x0000_0000 PALKEY Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...
Page 135: Port A Data Input Register - Padinr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port A Data Input Register – PADINR This register specifies the GPIO Port A input data. Offset: 0x01C Reset value: 0x0000_3200 Reserved Type/Reset Reserved Type/Reset PADIN Type/Reset 0 RO 0 RO 1 RO...
Page 136: Port A Output Set/Reset Control Register - Pasrr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port A Output Set/Reset Control Register – PASRR This register is used to set or reset the corresponding bit of the GPIO Port A output data. Offset: 0x024 Reset value: 0x0000_0000 PARST...
Page 137: Port A Output Reset Register - Parr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port A Output Reset Register – PARR This register is used to reset the corresponding bit of the GPIO Port A output data. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 138: Port B Input Function Enable Control Register - Pbiner
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port B Input Function Enable Control Register – PBINER This register is used to enable or disable the GPIO Port B input function. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 139: Port B Pull-Up Selection Register - Pbpur
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port B Pull-Up Selection Register – PBPUR This register is used to enable or disable the GPIO Port B pull-up function. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PBPU Type/Reset...
Page 140: Port B Pull-Down Selection Register - Pbpdr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port B Pull-Down Selection Register – PBPDR This register is used to enable or disable the GPIO Port B pull-down function. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PBPD Type/Reset...
Page 141: Port B Open-Drain Selection Register - Pbodr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port B Open-Drain Selection Register – PBODR This register is used to enable or disable the GPIO Port B open-drain function. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PBOD Type/Reset...
Page 142: Port B Drive Current Selection Register - Pbdrvr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port B Drive Current Selection Register – PBDRVR This register specifies the GPIO Port B output driving current. Offset: 0x014 Reset value: 0x0000_0000 PBDV15 PBDV14 PBDV13 PBDV12 Type/Reset 0 RW 0 RW...
Page 143: Port B Lock Register - Pblockr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port B Lock Register – PBLOCKR This register specifies the GPIO Port B lock configuration. Offset: 0x018 Reset value: 0x0000_0000 PBLKEY Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...
Page 144: Port B Data Input Register - Pbdinr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port B Data Input Register – PBDINR This register specifies the GPIO Port B input data. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PBDIN Type/Reset 0 RO 0 RO 0 RO...
Page 145: Port B Output Set/Reset Control Register - Pbsrr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port B Output Set/Reset Control Register – PBSRR This register is used to set or reset the corresponding bit of the GPIO Port B output data. Offset: 0x024 Reset value: 0x0000_0000 PBRST...
Page 146: Port B Output Reset Register - Pbrr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port B Output Reset Register – PBRR This register is used to reset the corresponding bit of the GPIO Port B output data. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 147: Port C Data Direction Control Register - Pcdircr
GPIO Port C pin n Direction Control Bits (n = 0 ~ x) 0: Pin n is in input mode 1: Pin n is in output mode For the HT32F54231/HT32F54241 devices the variable “x” is equal to 7 while the variable “x” is equal to 15 for the HT32F54243/HT32F54253 devices. Rev. 1.00...
Page 148: Port C Input Function Enable Control Register - Pciner
When the pin n input function is disabled, the input Schmitt trigger will be turned off and the Schmitt trigger output will remain at a zero state. For the HT32F54231/HT32F54241 devices the variable “x” is equal to 7 while the variable “x” is equal to 15 for the HT32F54243/HT32F54253 devices.
Page 149: Port C Pull-Up Selection Register - Pcpur
0: Pin n pull-up function is disabled 1: Pin n pull-up function is enabled For the HT32F54231/HT32F54241 devices the variable “x” is equal to 7 while the variable “x” is equal to 15 for the HT32F54243/HT32F54253 devices. Note: When the pull-up and pull-down functions are both enabled, the pull-up function will have the higher priority and therefore the pull-down function will be blocked and disabled.
Page 150: Port C Pull-Down Selection Register - Pcpdr
0: Pin n pull-down function is disabled 1: Pin n pull-down function is enabled For the HT32F54231/HT32F54241 devices the variable “x” is equal to 7 while the variable “x” is equal to 15 for the HT32F54243/HT32F54253 devices. Note: When the pull-up and pull-down functions are both enabled, the pull-up function will have the higher priority and therefore the pull-down function will be blocked and disabled.
Page 151: Port C Open-Drain Selection Register - Pcodr
0: Pin n Open-Drain output is disabled (The output type is CMOS output) 1: Pin n Open-Drain output is enabled (The output type is open-drain output) For the HT32F54231/HT32F54241 devices the variable “x” is equal to 7 while the variable “x” is equal to 15 for the HT32F54243/HT32F54253 devices.
Page 152: Port C Drive Current Selection Register - Pcdrvr
01: 8 mA source/sink current 10: 12 mA source/sink current 11: 16 mA source/sink current For the HT32F54231/HT32F54241 devices the variable “x” is equal to 7 while the variable “x” is equal to 15 for the HT32F54243/HT32F54253 devices Rev. 1.00...
Page 153: Port C Lock Register - Pclockr
PCLKEY and PCLOCKn (lock control bit) should be written together and cannot be changed until a system reset or GPIO Port C reset occurs. For the HT32F54231/HT32F54241 devices the variable “x” is equal to 7 while the variable “x” is equal to 15 for the HT32F54243/HT32F54253 devices.
Page 154: Port C Data Input Register - Pcdinr
0: The input data of corresponding pin is 0 1: The input data of corresponding pin is 1 For the HT32F54231/HT32F54241 devices the variable “x” is equal to 7 while the variable “x” is equal to 15 for the HT32F54243/HT32F54253 devices.
Page 155: Port C Output Data Register - Pcdoutr
0: Data to be output on pin n is 0 1: Data to be output on pin n is 1 For the HT32F54231/HT32F54241 devices the variable “x” is equal to 7 while the variable “x” is equal to 15 for the HT32F54243/HT32F54253 devices.
Page 156: Port C Output Set/Reset Control Register - Pcsrr
Note that when the PCRSTn bit in this register or the PCRSTn bit in the PCRR register is enabled, the reset function on the PCDOUTn bit will take effect. For the HT32F54231/HT32F54241 devices the variable “x” is equal to 7 while the variable “x” is equal to 15 for the HT32F54243/HT32F54253 devices.
Page 157: Port C Output Reset Register - Pcrr
GPIO Port C pin n Output Reset Control Bits (n = 0 ~ x) 0: No effect on the PCDOUTn bit 1: Reset the PCDOUTn bit For the HT32F54231/HT32F54241 devices the variable “x” is equal to 7 while the variable “x” is equal to 15 for the HT32F54243/HT32F54253 devices. Rev. 1.00...
Page 158: Port D Data Direction Control Register - Pddircr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port D Data Direction Control Register – PDDIRCR This register is used to control the direction of GPIO Port D pin as input or output. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset...
Page 159: Port D Input Function Enable Control Register - Pdiner
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port D Input Function Enable Control Register – PDINER This register is used to enable or disable the GPIO Port D input function. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 160: Port D Pull-Up Selection Register - Pdpur
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port D Pull-Up Selection Register – PDPUR This register is used to enable or disable the GPIO Port D pull-up function. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset...
Page 161: Port D Pull-Down Selection Register - Pdpdr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port D Pull-Down Selection Register – PDPDR This register is used to enable or disable the GPIO Port D pull-down function. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset...
Page 162: Port D Open-Drain Selection Register - Pdodr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port D Open-Drain Selection Register – PDODR This register is used to enable or disable the GPIO Port D open-drain function. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset...
Page 163: Port D Drive Current Selection Register - Pddrvr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port D Drive Current Selection Register – PDDRVR This register specifies the GPIO Port D output driving current. Offset: 0x014 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved PDDV5 PDDV4 Type/Reset 0 RW...
Page 164: Port D Lock Register - Pdlockr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port D Lock Register – PDLOCKR This register specifies the GPIO Port D lock configuration. Offset: 0x018 Reset value: 0x0000_0000 PDLKEY Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...
Page 165: Port D Data Input Register - Pddinr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port D Data Input Register – PDDINR This register specifies the GPIO Port D input data. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved PDDIN Type/Reset 0 RO...
Page 166: Port D Output Set/Reset Control Register - Pdsrr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port D Output Set/Reset Control Register – PDSRR This register is used to set or reset the corresponding bit of the GPIO Port D output data. Offset: 0x024 Reset value: 0x0000_0000 Reserved...
Page 167: Port D Output Reset Register - Pdrr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Port D Output Reset Register – PDRR This register is used to reset the corresponding bit of the GPIO Port D output data. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 168: Alternate Function Input/Output Control Unit (Afio)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Alternate Function Input/Output Control Unit (AFIO) Introduction In order to expand the flexibility of the GPIO or the usage of peripheral functions, each I/O pin can be configured to have up to sixteen different functions such as GPIO or IP functions by setting the GPxCFGLR or GPxCFGHR register where x is the different port name.
Page 169: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Features APB slave interface for register access ▆ EXTI source selection ▆ Configurable pin function for each GPIO, up to sixteen alternative functions on each pin ▆ AFIO lock mechanism ▆ Functional Descriptions External Interrupt Pin Selection The GPIO pins are connected to the 16 EXTI lines as shown in the accompanying figure.
Page 170: Alternate Function
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Alternate Function Up to sixteen alternative functions can be chosen for each I/O pad by setting the PxCFGn [3:0] field in the GPxCFGLR or GPxCFGHR (n = 0 ~ 15, x = A ~ D) registers. If the pin is selected as unavailable item which is noted as “N/A”...
Page 171: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Descriptions EXTI Source Selection Register 0 – ESSR0 This register specifies the I/O selection of EXTI0 ~ EXTI7. Offset: 0x000 Reset value: 0x0000_0000 EXTI7PIN EXTI6PIN Type/Reset 0 RW 0 RW 0 RW...
Page 172: Exti Source Selection Register 1 - Essr1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 EXTI Source Selection Register 1 – ESSR1 This register specifies the I/O selection of EXTI8 ~ EXTI15. Offset: 0x004 Reset value: 0x0000_0000 EXTI15PIN EXTI14PIN Type/Reset 0 RW 0 RW 0 RW 0 RW...
Page 173: Gpio Port X Configuration Low Register - Gpxcfglr, X = A, B, C, D
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 GPIO Port x Configuration Low Register – GPxCFGLR, x = A, B, C, D This low register specifies the alternate function of GPIO Port x, x = A, B, C, D Offset: 0x020, 0x028, 0x030, 0x038...
Page 174: Gpio Port X Configuration High Register - Gpxcfghr, X = A, B, C, D
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 GPIO Port x Configuration High Register – GPxCFGHR, x = A, B, C, D This high register specifies the alternate function of GPIO Port x, x = A, B, C, D Offset: 0x024, 0x02C, 0x034, 0x03C...
Page 175: Nested Vectored Interrupt Controller (Nvic)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Nested Vectored Interrupt Controller (NVIC) Introduction In order to reduce the latency and increase the interrupt processing efficiency, a tightly coupled integrated section, which is named as Nested Vectored Interrupt Controller (NVIC) is provided by the Cortex -M0+.
Page 176: Features
3. Refer to the PWRCU chapter for the relevant configuration descriptions about the WAKEUP-pin wakeup interrupt. 4. These exception types are only available for the HT32F54243/HT32F54253 devices. 5. Since there is only one USART in the HT32F54231/HT32F54241 devices, this exception type related to the USART do not have the serial number "0". Features...
Page 177: Functional Descriptions
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Functional Descriptions SysTick Calibration The SysTick Calibration Value Register (SYST_CALIB) is provided by the NVIC to give a reference time base of 1ms for the RTOS tick timer or other purposes. The TENMS field in the SYST_CALIB register has a fixed value of 7500 which is the Counter-Reload value to indicate 1 ms when the clock source comes from the SysTick reference input clock STCLK with a frequency of 7.5 MHz...
Page 178: External Interrupt/Event Controller (Exti)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 External Interrupt/Event Controller (EXTI) Introduction The External Interrupt/Event Controller, EXTI, comprises 16 edge detectors which can generate wakeup events or interrupt requests independently. In the interrupt mode there are five trigger types which can be selected as the external interrupt trigger type, low level, high level, negative edge, positive edge and both edges, selectable using the SRCnTYPE field in the EXTICFGRn (n = 0 ~ 15) register.
Page 179: Functional Descriptions
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Functional Descriptions Wakeup Event Management In order to wake up the system from the power saving mode, the EXTI controller provides a function which can monitor external events and send them to the MCU core and the Clock Control Unit, CKCU.
Page 180: Interrupt And Debounce
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 EXTIn EXTInWFL EVWUP interrupt High/Low EVWUPIEN (NVIC) level detector EXTInWPOL EXTInWEN EXTInEN (Note) EXTIn interrupt (NVIC) CMP_WAKEUP CMPWPEN CMP interrupt CMPRIEN (NVIC) RTC_WAKEUP OV / CM / CSECWEN OV / CM RTC interrupt...
Page 181: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Map The following table shows the EXTI registers and reset values. Table 27. EXTI Register Map Register Offset Description Reset Value EXTICFGR0 0x000 EXTI Interrupt 0 Configuration Register 0x0000_0000 EXTICFGR1 0x004...
Page 182: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Descriptions EXTI Interrupt n Configuration Register – EXTICFGRn, n = 0 ~ 15 This register is used to specify the debounce function and select the trigger type. Offset: 0x000 (0) ~ 0x03C (15)
Page 183: Exti Interrupt Control Register - Exticr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 EXTI Interrupt Control Register – EXTICR This register is used to control the EXTI interrupt. Offset: 0x040 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15EN EXTI14EN EXTI13EN EXTI12EN EXTI11EN EXTI10EN EXTI9EN EXTI8EN...
Page 184: Exti Interrupt Edge Flag Register - Extiedgeflgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR This register is used to indicate if an EXTI edge has been detected. Offset: 0x044 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15EDF EXTI14EDF EXTI13EDF EXTI12EDF EXTI11EDF EXTI10EDF EXTI9EDF EXTI8EDF...
Page 185: Exti Interrupt Edge Status Register - Extiedgesr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 EXTI Interrupt Edge Status Register – EXTIEDGESR This register indicates the polarity of a detected EXTI edge. Offset: 0x048 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15EDS EXTI14EDS EXTI13EDS EXTI12EDS EXTI11EDS EXTI10EDS EXTI9EDS EXTI8EDS...
Page 186: Exti Interrupt Wakeup Control Register - Extiwakupcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR This register is used to control the EXTI interrupt and wakeup function. Offset: 0x050 Reset value: 0x0000_0000 EVWUPIEN Reserved Type/Reset Reserved Type/Reset EXTI15WEN EXTI14WEN EXTI13WEN EXTI12WEN EXTI11WEN EXTI10WEN EXTI9WEN EXTI8WEN...
Page 187: Exti Interrupt Wakeup Polarity Register - Extiwakuppolr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR This register is used to select the EXTI line interrupt wakeup polarity. Offset: 0x054 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15WPOL EXTI14WPOL EXTI13WPOL EXTI12WPOL EXTI11WPOL EXTI10WPOL EXTI9WPOL EXTI8WPOL...
Page 188: Analog To Digital Converter (Adc)
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Analog to Digital Converter (ADC) Introduction A 12-bit multi-channel Analog to Digital Converter (ADC) with a Voltage Reference Generator ) is integrated in the devices. There are a total of 14 multiplexed channels including 10 external channels on which the external analog signal can be supplied and 4 internal channels.
Page 189: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Features 12-bit SAR ADC engine ▆ Up to 1 Msps conversion rate ▆ Up to 10 external analog input channels ▆ 1 channel for internal voltage reference (V ▆ 1 channel for monitor external V power support pin ▆...
Page 190: Functional Descriptions
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Functional Descriptions ADC Clock Setup The ADC clock, CK_ADC is provided by the Clock Controller which is synchronous and divided by with the AHB clock known as HCLK. Refer to the Clock Control Unit chapter for more details.
Page 191: Figure 31. One Shot Conversion Mode
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Conversion (ex: Sequence Length=8) Cycle Cycle Start of Conversion Single sample End of Conversion Cycle End of Conversion Figure 31. One Shot Conversion Mode Continuous Conversion Mode In the Continuous Conversion Mode, repeated conversion cycle will restart automatically without requiring additional A/D start trigger signals after a channel group conversion has completed.
Page 192 ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Discontinuous Conversion Mode The A/D converter will operate in the Discontinuous Conversion Mode for channels group when the A/D conversion mode bit field ADMODE [1:0] in the ADCCR register is set to 0x3. The group to be converted can have up to 8 channels and can be arranged in a specific sequence by configuring the ADCLSTn registers where n ranges from 0 to 1.
Page 193: Start Conversion On External Event
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Discontinuous Conversion Mode (ex: Sequence Length=8, Subgroup Length=3 ) Cycle Cycle Subgroup 0 Subgroup 1 Subgroup 2 Subgroup 0 Start of Conversion Single sample End of Conversion Subgroup End of Conversion Cycle End of Conversion Figure 33.
Page 194: Sampling Time Setting
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Sampling Time Setting The conversion channel sampling time can be programmed according to the input resistance of the input voltage source. This sampling time must be enough for the input voltage source to charge the internal sample and hold capacitor in the A/D converter to the input voltage level.
Page 195: Interrupts
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Interrupts When an A/D conversion is completed, an End of Conversion EOC event will occur. There are three kinds of EOC events which are known as single sample EOC, subgroup EOC and cycle EOC for A/D conversion.
Page 196: Vdda Voltage Monitor
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Voltage Reference Generator (V VREFEN Bandgap VREFVAL[5:0] AFIO15 VREFSEL[1:0] Figure 34. Voltage Reference Generator Block Diagram Voltage Monitor The MVDDAEN bit in the VREFCR register allows the applications to measure the V voltage on the VDDA pin.
Page 197: Register Descriptions
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Descriptions ADC Conversion Control Register – ADCCR This register specifies the mode setting, sequence length and subgroup length of the ADC conversion mode. Note that once the content of ADCCR is changed, the conversion in progress will be aborted and the A/D converter will return to an idle state.
Page 198 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [1:0] ADMODE ADC Conversion Mode ADMODE [1:0] Mode Descriptions After a start trigger, the conversion will be One shot mode executed on the specific channels for the whole conversion sequence once.
Page 199: Adc Conversion List Register 0 - Adclst0
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 ADC Conversion List Register 0 – ADCLST0 This register specifies the conversion sequence order No.0 ~ No.3 of the ADC. Offset: 0x004 Reset value: 0x0000_0000 Reserved ADSEQ3 Type/Reset 0 RW 0 RW...
Page 200: Adc Conversion List Register 1 - Adclst1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 ADC Conversion List Register 1 – ADCLST1 This register specifies the conversion sequence order No.4 ~ No.7 of the ADC. Offset: 0x008 Reset value: 0x0000_0000 Reserved ADSEQ7 Type/Reset 0 RW 0 RW...
Page 201: Adc Input Sampling Time Register - Adcstr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 ADC Input Sampling Time Register – ADCSTR This register specifies the A/D converter input channel sampling time. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset ADST Type/Reset 0 RW...
Page 202: Adc Conversion Data Register Y - Adcdry, Y = 0 ~ 7
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7 This register is used to store the conversion data of the conversion sequence order No.y which is specified by the ADSEQy field in the ADCLSTn (n = 0 ~ 1) registers.
Page 203: Adc Trigger Control Register - Adctcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 ADC Trigger Control Register – ADCTCR This register contains the ADC start conversion trigger enable bits. Offset: 0x070 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved ADEXTI ADSW Type/Reset 0 RW...
Page 204: Adc Trigger Source Register - Adctsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 ADC Trigger Source Register – ADCTSR This register contains the trigger source selection and the software trigger bit of the conversion. Offset: 0x074 Reset value: 0x0000_0000 Reserved TM0E Type/Reset 0 RW 0 RW...
Page 205: Adc Watchdog Control Register - Adcwcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 ADC Watchdog Control Register – ADCWCR This register provides the control bits and status of the ADC watchdog function. Offset: 0x078 Reset value: 0x0000_0000 Reserved ADUCH Type/Reset 0 RO 0 RO 0 RO...
Page 206: Adc Watchdog Threshold Register - Adctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions ADWUE ADC Watchdog Upper Threshold Enable Bit 0: Disable upper threshold monitor function 1: Enable upper threshold monitor function ADWLE ADC Watchdog Lower Threshold Enable Bit 0: Disable lower threshold monitor function 1: Enable lower threshold monitor function ADC Watchdog Threshold Register –...
Page 207: Adc Interrupt Enable Register - Adcier
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 ADC Interrupt Enable Register – ADCIER This register contains the ADC interrupt enable bits. Offset: 0x080 Reset value: 0x0000_0000 Reserved ADIEO Type/Reset Reserved ADIEU ADIEL Type/Reset 0 RW Reserved Type/Reset Reserved ADIEC...
Page 208: Adc Interrupt Raw Status Register - Adciraw
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 ADC Interrupt Raw Status Register – ADCIRAW This register contains the ADC interrupt raw status bits. Offset: 0x084 Reset value: 0x0000_0000 Reserved ADIRAWO Type/Reset Reserved ADIRAWU ADIRAWL Type/Reset 0 RO Reserved Type/Reset...
Page 209: Adc Interrupt Status Register - Adcisr
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 ADC Interrupt Status Register – ADCISR This register contains the ADC interrupt masked status bits. The corresponding interrupt status will be set to 1 if the associated interrupt event occurs and the related enable bit is set to 1.
Page 210: Adc Interrupt Clear Register - Adciclr
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 ADC Interrupt Clear Register – ADCICLR This register provides the clear bits used to clear the interrupt raw and masked status of the ADC. These bits are set to 1 by software to clear the interrupt status and automatically cleared to 0 by hardware after being set to 1.
Page 211: Adc Dma Request Register - Adcdmar
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 ADC DMA Request Register – ADCDMAR This register contains the ADC DMA request enable bits. Offset: 0x090 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved ADDMAC ADDMAG ADDMAS Type/Reset 0 RW...
Page 212: Voltage Reference Control Register - Vrefcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Voltage Reference Control Register – VREFCR This register contains the internal voltage reference control bits. Offset: 0x0A0 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved MVDDAEN Type/Reset Reserved VREFSEL Reserved VREFEN Type/Reset...
Page 213: Voltage Reference Value Register - Vrefvalr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Voltage Reference Value Register – VREFVALR This register contains the internal voltage reference trim value. Offset: 0x0A4 Reset value: 0x0000_00XX (Various depending on Flash Manufacture Privilege Information Block) Reserved Type/Reset Reserved Type/Reset...
Page 214: Comparator (Cmp) (Ht32F54243/Ht32F54253 Only)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Comparator (CMP) (HT32F54243/ HT32F54253 only) Introduction Two general purpose comparators (CMP) are implemented within the devices. They can be configured either as standalone comparators or combined with the different kinds of peripheral IP.
Page 215: Functional Descriptions
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Functional Descriptions Comparator Inputs and Output The I/O pins used as comparator input or output must be configured in the AFIO controller registers. The detailed comparator input and output information will be referred in pin assignment table in the datasheet.
Page 216: Interrupts And Wakeup
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Interrupts and Wakeup The comparator can generate an interrupt when its output waveform generates a rising or falling edge and its corresponding interrupt enable control bit is also set. For example, when a comparator output rising edge occurs, the comparator rising edge flag bit CMPRF in the Comparator Transition Flag Register CMPTFRn will be set.
Page 217: Power Mode And Hysteresis
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Power Mode and Hysteresis The comparator response time can be programmed to meet the trade-off between the power consumption and application speed requirements. The bit CMPSM in the CMPCRn register can be programmed as “0” to make the comparator operate in the low speed mode with low power consumption.
Page 218: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Descriptions Comparator Control Register n – CMPCRn, n = 0 or 1 This register contains the comparator function and voltage reference control bits. Offset: 0x000 (n = 0), 0x100 (n = 1)
Page 219 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [13:11] CMPOSEL Comparator 0 Output Selection 000: No selection 001: GPTM capture channel 3 010: MCTM capture channel 3 011: MCTM break input 1 100: ADC trigger input Others: Reserved...
Page 220: Comparator Voltage Reference Value Register N - Cvrvalrn, N = 0 Or 1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Comparator Voltage Reference Value Register n – CVRVALRn, n = 0 or 1 The register is used to set the comparator voltage reference level. Offset: 0x004 (n = 0), 0x104 (n = 1)
Page 221: Comparator Interrupt Enable Register N - Cmpiern, N = 0 Or 1
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Comparator Interrupt Enable Register n – CMPIERn, n = 0 or 1 The register is used to enable the comparator n interrupt when the comparator output transition event occurs. Offset: 0x008 (n = 0), 0x108 (n = 1)
Page 222: Comparator Transition Flag Register N - Cmptfrn, N = 0 Or 1
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Comparator Transition Flag Register n – CMPTFRn, n = 0 or 1 This register contains the comparator n output transition detection enable bits and relevant flags. Offset: 0x00C (n = 0), 0x10C (n = 1)
Page 223: General-Purpose Timer (Gptm)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 General-Purpose Timer (GPTM) Introduction The General-Purpose Timer consists of one 16-bit up/down-counter, four 16-bit Capture/Compare Registers (CCRs), one 16-bit Counter-Reload Register (CRR) and several control/status registers. It can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as single pulse generation or PWM output.
Page 224: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Features 16-bit up/down auto-reload counter ▆ 16-bit programmable prescaler that allows division of the prescaler clock source by any factor ▆ between 1 and 65536 to generate the counter clock frequency Up to 4 independent channels for: ▆...
Page 225: Figure 40. Up-Counting Example
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 CK_PSC CNT_EN CK_CNT CNTR CRR Shadow Register PSCR PSCR Shadow Register PSC_CNT Counter Overflow Update Event Flag Write a new value Update the new value Software clearing Figure 40. Up-counting Example Down-Counting...
Page 226: Clock Controller
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Center-Aligned Counting In the center-aligned counting mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The Timer module generates an overflow event when the counter counts to the counter-reload value in the up-counting mode and generates an underflow event when the counter counts to 0 in the down-counting mode.
Page 227: Figure 43. Gptm Clock Source Selection
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 STIED: ▆ The counter prescaler can count during each rising edge of the STI signal. This mode can be selected by setting the SMSEL field to 0x7 in the MDCFR register. Here the counter will act as an event counter.
Page 228: Trigger Controller
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Trigger Controller The trigger controller is used to select the trigger source and setup the trigger level or trigger edge condition. For the internal trigger input, it can be selected by the Trigger Selection bits TRSEL in the TRCFR register.
Page 229: Slave Controller
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Slave Controller The GPTM can be synchronized with an external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which can be selected by the SMSEL field in the MDCFR register.
Page 230: Figure 47. Gptm In Pause Mode
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Pause Mode In the Pause Mode, the selected STI input signal level is used to control the counter start/stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level, here the counter will maintain its present value and will not be reset.
Page 231: Master Controller
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Master Controller The GPTMs and TMs can be linked together internally for timer synchronization or chaining. When one GPTM is configured to be in the Master Mode, the GPTM Master Controller will generate a Master Trigger Output (MTO) signal which includes a reset, a start, a stop signal or a clock source which is selected by the MMSEL field in the MDCFR register to trigger or drive another GPTM or TM, if exists, which is configured in the Slave Mode.
Page 232: Channel Controller
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel Controller The GPTM has four independent channels which can be used as capture inputs or compare match outputs. Each capture input or compare match output channel is composed of a preload register and a shadow register. Data access of the APB bus is always implemented by reading/writing the preload register.
Page 233: Figure 52. Input Capture Mode
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Capture Counter Value Transferred to CHxCCR When the channel is used as a capture input, the counter value is captured into the Channel Capture/Compare Register (CHxCCR) when an effective input signal transition occurs. Once the capture event occurs, the CHxCCIF flag in the INTSR register is set accordingly.
Page 234: Input Stage
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Restart mode Restart mode Reset counter value Reset counter value GT_CH0 (TI0) Capture CH0 Capture CH1 CNTR CH0CCR CH1CCR Figure 53. PWM Pulse Width Measurement Example Input Stage The input stage consists of a digital filter, a channel polarity selection, edge detection and a channel prescaler.
Page 235: Figure 55. Channel 2 And Channel 3 Input Stages
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 TRCED CH2CCS CLKIN GT_CH2 TI2FP Filter TI2S2 Edge TI2S2ED sampling TI2FN Detection CH2PSC TI2F CH2PRESCALER CH2P CH2CAP Event TI3S2 Edge TI3S2ED CH2PSC Detection TI2S3 Edge TI2S3ED Detection CH3P CH3PSC TI3FP GT_CH3 CH3PRESCALER...
Page 236: Quadrature Decoder
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Quadrature Decoder The Quadrature Decoder function uses two quadrantal inputs TI0 and TI1 derived from the GT_CH0 and GT_CH1 pins respectively to interact to generate the counter value. The DIR bit is modified by hardware automatically during each input source transition. The input source can be either TI0 only, TI1 only or both TI0 and TI1, the selection made by setting the SMSEL field to 0x1, 0x2 or 0x3.
Page 237: Output Stage
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Table 31. Counting Direction and Encoding Signals TI0S0 TI1S1 Counting Mode Level Rising Falling Rising Falling TI1S1 = High Down — — Counting on TI0 only (SMSEL = 0x1) TI1S1 = Low Down —...
Page 238: Table 32. Compare Match Output Setup
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel Output Reference Signal When the GPTM is used in the compare match output mode, the Channel x Output Reference signal, CHxOREF, is defined by the CHxOM field setup. The CHxOREF signal has several types of output function which defines what happens to the output when the counter value matches the contents of the CHxCCR register.
Page 239: Figure 61. Toggle Mode Channel Output Reference Signal (Chxpre = 1)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Counter Value CHxOM=0x3, CHxPRE=1 (Output toggle, preload enable) CHxCCR (New value 2) CHxCCR (New value 3) CHxCCR (New value 1) CHxCCR Time Update CHxCCR value CHxOREF (Update Event) Figure 61. Toggle Mode Channel Output Reference Signal (CHxPRE = 1)
Page 240: Figure 63. Pwm Mode Channel Output Reference Signal And Counter In Down-Counting Mode
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Counter Value Counter Value CHxCCR CHxCCR CHxOM = 0x6 100% CHxOREF CHxOREF CHxCCIF CHxCCIF CHxOM = 0x7 CHxOREF Figure 63. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode CRR = 5...
Page 241: Update Management
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Update Management The Update event is used to update the CRR, the PSCR, the CHxACR and the CHxCCR values from the actual registers to the corresponding shadow registers. An update event occurs when the counter overflows or underflows, the software update control bit is triggered or an update event from the slave controller is generated.
Page 242: Single Pulse Mode
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Single Pulse Mode Once the timer is set to operate in the single pulse mode, it is not necessary to set the timer enable bit TME in the CTR register to 1 to enable the counter. The trigger to generate a pulse can be sourced from the STI signal rising edge or by setting the TME bit to 1 using software.
Page 243: Figure 67. Immediate Active Mode Minimum Delay
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 In the Single Pulse mode, the STI active edge which sets the TME bit to 1 will enable the counter. However, there exist several clock delays to perform the comparison result between the counter value and the CHxCCR value. In order to reduce the delay to a minimum value, the user can set the CHxIMAE bit in each CHxOCFR register.
Page 244: Asymmetric Pwm Mode
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Asymmetric PWM Mode Asymmetric PWM mode allows two center-aligned PWM signals to be generated with a programmable phase shift. While the PWM frequency is determined by the value of the CRR register, the duty cycle and the phase-shift are determined by the CHxCCR and CHxACR register.
Page 245: Figure 69. Pausing Pwm0 Using The Gptm Ch0Oref Signal
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Master GPTM CLKIN GPTM CH0OREF GPTM CNTR Slave PWM0 PWM0 CNTR PWM0 TEVIF Software clearing Figure 69. Pausing PWM0 Using the GPTM CH0OREF Signal Using one Timer to Trigger another Timer Start Counting Configure GPTM to operate in the master mode to send its Update Event UEV as the trigger ▆...
Page 246: Figure 71. Trigger Gptm And Pwm0 With The Gptm Ch0 Input
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Starting Two Timers Synchronously in Response to an External Trigger Configure GPTM to operate in the master mode to send its enable signal as a trigger output ▆ (MMSEL = 0x1). Configure GPTM slave mode to receive its input trigger source from GT_CH0 pin (TRSEL = 0x1).
Page 247: Trigger Peripherals Start
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Trigger Peripherals Start To interconnect to the peripherals, such as ADC, Timer and so on, the GPTM could output the MTO signal or the channel compare match output signal CHxOREF (x = 0 ~ 3) to be used as peripherals input trigger signal and depending on the MCU specification.
Page 248: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Map The following table shows the GPTM registers and reset values. The PDMA related describes are only available for the HT32F54243/HT32F54253 devices. Table 33. GPTM Register Map Register Offset Description Reset Value...
Page 249: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Descriptions Timer Counter Configuration Register – CNTCFR This register specifies the GPTM counter configuration. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CMSEL Type/Reset 0 RW Reserved CKDIV Type/Reset 0 RW...
Page 250: Timer Mode Configuration Register - Mdcfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions UGDIS Update event interrupt generation disable control 0: Any of the following events will generate an update PDMA request or interrupt - Counter overflow/underflow - Setting the UEVG bit...
Page 251 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [18:16] MMSEL Master Mode Selection Master mode selection is used to select the MTO signal source which is used to synchronize the other slave timer. MMSEL [2:0] Mode Descriptions...
Page 252 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [10:8] SMSEL Slave Mode Selection SMSEL [2:0] Mode Descriptions The prescaler is clocked directly by the internal Disable Mode clock. The counter uses the clock pulse generated from the interaction between the TI0 and TI1 signals to Quadrature drive the counter prescaler.
Page 253: Timer Trigger Configuration Register - Trcfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Timer Trigger Configuration Register – TRCFR This register specifies the trigger source selection of GPTM. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved TRSEL Type/Reset 0 RW 0 RW...
Page 254: Timer Control Register - Ctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Timer Control Register – CTR This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE) and Channel PDMA selection bit (CHCCDS). Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved...
Page 255: Channel 0 Input Configuration Register - Ch0Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 0 Input Configuration Register – CH0ICFR This register specifies the channel 0 input mode configuration. Offset: 0x020 Reset value: 0x0000_0000 TI0SRC Reserved Type/Reset Reserved CH0PSC CH0CCS Type/Reset 0 RW 0 RW...
Page 256: Channel 1 Input Configuration Register - Ch1Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [3:0] TI0F Channel 0 Input Source TI0 Filter Setting These bits define the frequency divided ratio used to sample the TI0 signal. The Digital filter in the GPTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
Page 257 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [17:16] CH1CCS Channel 1 Capture/Compare Selection 00: Channel 1 is configured as an output 01: Channel 1 is configured as an input derived from the TI1 signal 10: Channel 1 is configured as an input derived from the TI0 signal...
Page 258: Channel 2 Input Configuration Register - Ch2Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 2 Input Configuration Register – CH2ICFR This register specifies the channel 2 input mode configuration. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CH2PSC CH2CCS Type/Reset 0 RW 0 RW 0 RW...
Page 259: Channel 3 Input Configuration Register - Ch3Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [3:0] TI2F Channel 2 Input Source TI2 Filter Setting These bits define the frequency divided ratio used to sample the TI2 signal. The Digital filter in the GPTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
Page 260 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [17:16] CH3CCS Channel 3 Capture/Compare Selection 00: Channel 3 is configured as an output 01: Channel 3 is configured as an input derived from the TI3 signal 10: Channel 3 is configured as an input derived from the TI2 signal...
Page 261: Channel 0 Output Configuration Register - Ch0Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 0 Output Configuration Register – CH0OCFR This register specifies the channel 0 output mode configuration. Offset: 0x040 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH0OM[3] Type/Reset Reserved CH0IMAE CH0PRE Reserved...
Page 262 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [8][2:0] CH0OM[3:0] Channel 0 Output Mode Setting These bits define the functional types of the output reference signal CH0OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
Page 263: Channel 1 Output Configuration Register - Ch1Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 1 Output Configuration Register – CH1OCFR This register specifies the channel 1 output mode configuration. Offset: 0x044 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH1OM[3] Type/Reset Reserved CH1IMAE CH1PRE Reserved...
Page 264 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [8][2:0] CH1OM[3:0] Channel 1 Output Mode Setting These bits define the functional types of the output reference signal CH1OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
Page 265: Channel 2 Output Configuration Register - Ch2Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 2 Output Configuration Register – CH2OCFR This register specifies the channel 2 output mode configuration. Offset: 0x048 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH2OM[3] Type/Reset Reserved CH2IMAE CH2PRE Reserved...
Page 266 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [8][2:0] CH2OM[3:0] Channel 2 Output Mode Setting These bits define the functional types of the output reference signal CH2OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
Page 267: Channel 3 Output Configuration Register - Ch3Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 3 Output Configuration Register – CH3OCFR This register specifies the channel 3 output mode configuration. Offset: 0x04C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH3OM[3] Type/Reset Reserved CH3IMAE CH3PRE Reserved...
Page 268 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [8][2:0] CH3OM[3:0] Channel 3 Output Mode Setting These bits define the functional types of the output reference signal CH3OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
Page 269: Channel Control Register - Chctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel Control Register – CHCTR This register contains the channel capture input or compare output function enable control bits. Offset: 0x050 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3E...
Page 270: Channel Polarity Configuration Register - Chpolr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel Polarity Configuration Register – CHPOLR This register contains the channel capture input or compare output polarity control. Offset: 0x054 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3P Reserved...
Page 271: Timer Pdma/Interrupt Control Register - Dictr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Timer PDMA/Interrupt Control Register – DICTR This register contains the timer PDMA and interrupt enable control bits. Offset: 0x074 Reset value: 0x0000_0000 Reserved TEVDE Reserved UEVDE Type/Reset Reserved CH3CCDE CH2CCDE CH1CCDE CH0CCDE...
Page 272: Timer Event Generator Register - Evgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions CH1CCIE Channel 1 Capture/Compare Interrupt Enable 0: Channel 1 interrupt is disabled 1: Channel 1 interrupt is enabled CH0CCIE Channel 0 Capture/Compare Interrupt Enable 0: Channel 0 interrupt is disabled 1: Channel 0 interrupt is enabled Timer Event Generator Register –...
Page 273 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions CH3CCG Channel 3 Capture/Compare Generation A Channel 3 capture/compare event can be generated by setting this bit. It is cleared by hardware automatically. 0: No action 1: Capture/compare event is generated on channel 3 If Channel 3 is configured as an input, the counter value is captured into the CH3CCR register and then the CH3CCIF bit is set.
Page 274: Timer Interrupt Status Register - Intsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Timer Interrupt Status Register – INTSR This register stores the timer interrupt status. Offset: 0x07C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVIF Reserved UEVIF Type/Reset CH3OCF CH2OCF CH1OCF CH0OCF CH3CCIF...
Page 275 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions CH0OCF Channel 0 Over-Capture Flag This flag is set by hardware and cleared by software. 0: No over-capture event is detected 1: Capture event occurs again when the CH0CCIF bit is already set and it is not yet cleared by software.
Page 276: Timer Counter Register - Cntr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions CH0CCIF Channel 0 Capture/Compare Interrupt Flag - Channel 0 is configured as an output: 0: No match event occurs 1: The content of the counter CNTR has matched the content of the CH0CCR...
Page 277: Timer Prescaler Register - Pscr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Timer Prescaler Register – PSCR This register specifies the timer prescaler value to generate the counter clock. Offset: 0x084 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PSCV Type/Reset 0 RW 0 RW...
Page 278: Timer Counter-Reload Register - Crr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Timer Counter-Reload Register – CRR This register specifies the timer counter-reload value. Offset: 0x088 Reset value: 0x0000_FFFF Reserved Type/Reset Reserved Type/Reset Type/Reset 1 RW 1 RW 1 RW 1 RW 1 RW...
Page 279: Channel 0 Capture/Compare Register - Ch0Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 0 Capture/Compare Register – CH0CCR This register specifies the timer channel 0 capture/compare value. Offset: 0x090 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH0CCV Type/Reset 0 RW 0 RW 0 RW...
Page 280: Channel 1 Capture/Compare Register - Ch1Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 1 Capture/Compare Register – CH1CCR This register specifies the timer channel 1 capture/compare value. Offset: 0x094 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH1CCV Type/Reset 0 RW 0 RW 0 RW...
Page 281: Channel 2 Capture/Compare Register - Ch2Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 2 Capture/Compare Register – CH2CCR This register specifies the timer channel 2 capture/compare value. Offset: 0x098 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2CCV Type/Reset 0 RW 0 RW 0 RW...
Page 282: Channel 3 Capture/Compare Register - Ch3Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 3 Capture/Compare Register – CH3CCR This register specifies the timer channel 3 capture/compare value. Offset: 0x09C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH3CCV Type/Reset 0 RW 0 RW 0 RW...
Page 283: Channel 0 Asymmetric Compare Register - Ch0Acr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 0 Asymmetric Compare Register – CH0ACR This register specifies the timer channel 0 asymmetric compare value. Offset: 0x0A0 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH0ACV Type/Reset 0 RW 0 RW...
Page 284: Channel 2 Asymmetric Compare Register - Ch2Acr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 2 Asymmetric Compare Register – CH2ACR This register specifies the timer channel 2 asymmetric compare value. Offset: 0x0A8 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2ACV Type/Reset 0 RW 0 RW...
Page 285: Motor Control Timer (Mctm)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Motor Control Timer (MCTM) Introduction The Motor Control Timer consists of one 16-bit up/down-counter, four 16-bit Capture/Compare Registers (CCRs), one 16-bit Counter-Reload Register (CRR), one 8-bit Repetition Counter (REPR) and several control/status registers. It can be used for a variety of purposes which include general time measurement, input signal pulse width measurement, output waveform generation for signals such as single pulse generation or PWM generation, including dead time insertion.
Page 286: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Features 16-bit up/down auto-reload counter ▆ 16-bit programmable prescaler that allows division the prescaler clock source by any factor ▆ between 1 and 65536 to generate the counter clock frequency Up to 4 independent channels for: ▆...
Page 287: Functional Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Functional Descriptions Counter Mode Up-Counting In this mode the counter counts continuously from 0 to the counter-reload value, which is defined in the CRR register, in a count-up direction, then restarts from 0 and generates a counter overflow event.
Page 288: Figure 75. Down-Counting Example
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Down-Counting In this mode the counter counts continuously from the counter-reload value, which is defined in the CRR register, to 0 in a count-down direction, then restarts from the counter-reload value and generates a counter underflow event. This action will continue repeatedly. The counting direction bit DIR in the CNTCFR register should be set to 1 for the down-counting mode.
Page 289: Figure 76. Center-Aligned Counting Example
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Center-Aligned Counting In the center-aligned counting mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The Timer Module generates an overflow event when the counter counts to the counter-reload value in the up-counting mode and generates an underflow event when the counter counts to 0 in the down-counting mode.
Page 290: Figure 77. Update Event 1 Dependent Repetition Mechanism Example
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Repetition Down-Counter Operation The update event 1 is usually generated at each overflow or underflow event occurrence. However, when the repetition operation is active by assigning a non-zero value into the REPR register, the update event is only generated if the REPR counter has reached zero.
Page 291: Clock Controller
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Clock Controller The following describes the Timer Module clock controller which determines the internal prescaler counter clock source. Internal APB clock f ▆ CLKIN The default internal clock source is the APB clock f...
Page 292: Trigger Controller
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Trigger Controller The trigger controller is used to select the trigger source and setup the trigger level and edge trigger conditions. For the internal trigger input (ITIx), it can be selected by the Trigger Selection bits, TRSEL, in the TRCFR register.
Page 293: Slave Controller
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Slave Controller The MCTM can be synchronised with an internal/external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which are selected by the SMSEL field in the MDCFR register.
Page 294: Figure 82. Mctm In Pause Mode
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Pause Mode In the Pause Mode, the selected STI input signal level is used to control the counter start/stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level.
Page 295: Master Controller
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Master Controller The MCTMs and GPTMs can be linked together internally for timer synchronisation or chaining. When one MCTM is configured to be in the Master Mode, the MCTM Master Controller will generate a Master Trigger Output (MTO) signal which can reset, restart, stop the Slave counter or be a clock source of the Slave Counter.
Page 296: Channel Controller
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel Controller The MCTM has four independent channels which can be used as capture inputs or compare match outputs. Each capture input or compare match output channel is composed of a preload register and a shadow register. Data access of the APB bus is always implemented by reading/writing the preload register.
Page 297: Figure 87. Input Capture Mode
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Capture Counter Value Transferred to CHxCCR When the channel is used as a capture input, the counter value is captured into the Channel Capture/Compare Register (CHxCCR) when an effective input signal transition occurs. Once the capture event occurs, the CHxCCIF flag in the INTSR register is set accordingly.
Page 298: Figure 88. Pwm Pulse Width Measurement Example
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Pulse Width Measurement The input capture mode can be also used for pulse width measurement from signals on the MT_ CHx pins, TIx. The following example shows how to configure the MCTM when operated in the input capture mode to measure the high pulse width and the input period on the MT_CH0 pin using channel 0 and channel 1.
Page 299: Input Stage
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Input Stage The input stage consists of a digital filter, a channel polarity selection, edge detection and a channel prescaler. The channel 0 input signal TI0 can be chosen to come from the MT_CH0 signal or the Excusive-OR function of the MT_CH0, MT_CH1 and MT_CH2 signals.
Page 300: Figure 91. Ti0 Digital Filter Diagram With N = 2
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Digital Filter The digital filters are embedded in the input stage and clock controller block for the MT_CH0 ~ MT_CH3 pins. The digital filter in the MCTM is an N-event counter where N refers to how many valid transitions are necessary to output a filtered signal.
Page 301: Output Stage
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Output Stage The MCTM supports complementary outputs for channels 0, 1 and 2 with dead time insertion. The MCTM channel 3 output function is almost the same as that of GPTM channel 3 except for the break function.
Page 302: Table 35. Compare Match Output Setup
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel Output Reference Signal When the MCTM is used in the compare match output mode, the CHxOREF signal (Channel x Output Reference signal) is defined by the CHxOM field setup. The CHxOREF signal has several types of output function which defines what happens to the output when the counter value matches the contents of the CHxCCR register.
Page 303: Figure 94. Toggle Mode Channel Output Reference Signal - Chxpre = 1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Counter Value CHxOM=0x3, CHxPRE=1 (Output toggle, preload enable) CHxCCR (New value 2) CHxCCR (New value 3) CHxCCR (New value 1) CHxCCR Time Update CHxCCR value CHxOREF UEV1 (Update Event 1) Figure 94. Toggle Mode Channel Output Reference Signal – CHxPRE = 1...
Page 304: Figure 96. Pwm Mode Channel Output Reference Signal And Counter In Down-Counting Mode
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Counter Value Counter Value CHxCCR CHxCCR CHxOM = 0x6 100% CHxOREF CHxOREF CHxCCIF CHxCCIF CHxOM = 0x7 CHxOREF CHxOREF Figure 96. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode...
Page 305: Figure 98. Dead-Time Insertion Performed For Complementary Outputs
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Dead Time Generator An 8-bit dead time generator function is included for channels 0 ~ 2. The dead time insertion is enabled by setting both the CHxE and CHxNE bits. The relationship between the CHxO and...
Page 306: Figure 99. Mctm Break Signal Bolck Diagram
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Break Function The MCTM includes break function and one input signal for MCTM break. The MT_BRK is default function and from the external MT_BRK pin. The detailed block diagram is shown as below figure.
Page 307: Figure 101. Channel 3 Output With A Break Event Occurrence
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 When using the break function, the channel output enable signals and output levels are changed depending on several control bits which include the CHMOE, CHOSSI, CHOSSR, CHxOIS and CHxOISN bits. Once a break event occurs, the output enable bit CHMOE will be cleared asynchronously.
Page 308: Figure 102. Channel 0 ~ 2 Complementary Outputs With A Break Event Occurrence
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 The accompanying diagram shows that the complementary output states when a break event occurs where the complementary outputs are enabled by setting both the CHxE and CHxNE bits to 1. Break event CHMOE...
Page 309: Figure 103. Channel 0 ~ 2 Only One Output Enabled When Break Event Occurs
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 The accompanying diagram shows the output states in the case of the output being enabled by setting the CHxE bit to 1 and the complementary output being disabled by clearing the CHxNE to 0 when a break event occurs.
Page 310: Figure 104. Hardware Protection When Both Chxo And Chxno Are In Active Condition
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 The CHxO and CHxNO complementary outputs should not be set to an active level at the same time. The hardware will protect the MCTM circuitry to force only one channel output to be in the active state.
Page 311: Table 36. Output Control Bits For Complementary Output With A Break Event Occurrence
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Table 36. Output Control Bits for Complementary Output with a Break Event Occurrence Control Bits Output Status MT_CHxN Pin Output CHMOE CHOSSI CHOSSR CHxE CHxNE MT_CHx Pin Output State State Output disabled - floating...
Page 312: Update Management
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Update Management The update events are categorised into two different types which are the update event 1, UEV1, and update event 2, UEV2. The update event 1 is used to update the CRR, the PSCR, the CHxACR and the CHxCCR values from the actual registers to the corresponding shadow registers.
Page 313: Figure 106. Chxe, Chxne And Chxom Updated By Update Event 2
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Update Event 2 The CHxE, CHxNE, CHxOM control bits for the complementary outputs can be preloaded by setting the COMPRE bit in the CTR register. Here the shadow bits of the CHxE, CHxNE and CHxOM bits will be updated when an update event 2 occurs.
Page 314: Single Pulse Mode
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Single Pulse Mode Once the timer is set to operate in the single pulse mode, it is not necessary to set the timer enable bit TME in the CTR register to 1 to enable the counter. The trigger to generate a pulse can be sourced from the STI signal rising edge or by setting the TME bit to 1 using software.
Page 315: Figure 109. Immediate Active Mode Minimum Delay
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 In the Single Pulse mode, the STI active edge which sets the TME bit to 1 will enable the counter. However, there exist several clock delays to perform the comparison result between the counter value and the CHxCCR value. In order to reduce the delay to a minimum value, users can set the CHxIMAE bit in each CHxOCFR register.
Page 316: Asymmetric Pwm Mode
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Asymmetric PWM Mode Asymmetric PWM mode allows two center-aligned PWM signals to be genetated with a programmable phase shift. While the PWM frequency is determined by the value of the CRR register, the duty cycle and the phase-shift are determined by the CHxCCR and CHxACR register.
Page 317: Timer Interconnection
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Timer Interconnection The timers can be internally connected together for timer chaining or synchronization. This can be implemented by configuring one timer to operate in the master mode while configuring another timer to be in the slave mode. The following figures present several examples of trigger selection for the master and slave modes.
Page 318: Figure 112. Triggering Gptm With Mctm Update Event 1
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Using one timer to trigger another timer to start counting Configure MCTM to operate in the master mode and to send its Update Event 1 UEV1 as the ▆ trigger output (MMSEL = 0x2).
Page 319: Figure 113. Trigger Mctm And Gptm With The Mctm Ch0 Input
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Starting two timers synchronously in response to an external trigger Configure MCTM to operate in the master mode to send its enable signal as a trigger output ▆ (MMSEL = 0x1). Configure MCTM slave mode to receive its input trigger source from MT_CH0 pin (TRSEL = 0x1).
Page 320: Figure 114. Ch0Xor Input As Hall Sensor Interface
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Using one timer as a hall sensor interface to trigger another timer with update event 2 GPTM Configure channel 0 to choose an input XOR function (TI0SRC = 1) ▆ Configure channel 0 to be in the input capture mode and TRCED as capture source (CH0CCS= ▆...
Page 321: Trigger Peripheral Start
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Trigger Peripheral Start To interconnect to the peripherals, such as ADC, Timer and so on, the MCTM can output the MTO signal or the channel compare match output signal CHxOREF (x = 0 ~ 3) to be used as a peripheral input trigger signal, depending on the MCU specification.
Page 322: Pdma Request (Ht32F54243/Ht32F54253 Only)
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 PDMA Request (HT32F54243/HT32F54253 only) The MCTM has a PDMA data transfer interface. There are certain events which can generate PDMA requests if the corresponding enable control bits are set to 1 to enable the PDMA access.
Page 323: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Map The following table shows the MCTM registers and reset values. The PDMA related describes are only available for the HT32F54243/HT32F54253 devices. Table 38. MCTM Register Map Register Offset Description Reset Value...
Page 324: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Descriptions Timer Counter Configuration Register – CNTCFR This register specifies the MCTM counter configuration. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CMSEL Type/Reset 0 RW Reserved CKDIV Type/Reset 0 RW...
Page 325: Timer Mode Configuration Register - Mdcfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions UGDIS Update event 1 interrupt generation disable control 0: Any of the following events will generate an update PDMA request or interrupt - Counter overflow / underflow - Setting the UEV1G bit...
Page 326 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [18:16] MMSEL Master Mode Selection Master mode selection is used to select the MTO signal source which is used to synchronise the other slave timer. MMSEL [2:0] Mode Descriptions...
Page 327 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [10:8] SMSEL Slave Mode Selection SMSEL [2:0] Mode Descriptions Disable mode The prescaler is clocked directly by the internal clock. Reserved Reserved Reserved The counter value restarts from 0 or the CRR shadow...
Page 328: Timer Trigger Configuration Register - Trcfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Timer Trigger Configuration Register – TRCFR This register specifies the trigger source selection of MCTM. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved TRSEL Type/Reset 0 RW 0 RW...
Page 329: Timer Control Register - Ctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Timer Control Register – CTR This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE), Capture/compare control bit and Channel PDMA selection bit (CHCCDS). Offset: 0x010 Reset value: 0x0000_0000...
Page 330: Channel 0 Input Configuration Register - Ch0Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 0 Input Configuration Register – CH0ICFR This register specifies the channel 0 input mode configuration. Offset: 0x020 Reset value: 0x0000_0000 TI0SRC Reserved Type/Reset Reserved CH0PSC CH0CCS Type/Reset 0 RW 0 RW...
Page 331 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [3:0] TI0F Channel 0 Input Source TI0 Filter Setting These bits define the frequency divided ratio used to sample the TI0 signal. The Digital filter in the MCTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
Page 332: Channel 1 Input Configuration Register - Ch1Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 1 Input Configuration Register – CH1ICFR This register specifies the channel 1 input mode configuration. Offset: 0x024 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CH1PSC CH1CCS Type/Reset 0 RW 0 RW 0 RW...
Page 333 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [3:0] TI1F Channel 1 Input Source TI1 Filter Setting These bits define the frequency divide ratio used to sample the TI1 signal. The Digital filter in the MCTM is an N-event counter where N is defined as how many...
Page 334: Channel 2 Input Configuration Register - Ch2Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 2 Input Configuration Register – CH2ICFR This register specifies the channel 2 input mode configuration. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CH2PSC CH2CCS Type/Reset 0 RW 0 RW 0 RW...
Page 335 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [3:0] TI2F Channel 2 Input Source TI2 Filter Setting These bits define the frequency divide ratio used to sample the TI2 signal. The Digital filter in the MCTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
Page 336: Channel 3 Input Configuration Register - Ch3Icfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 3 Input Configuration Register – CH3ICFR This register specifies the channel 3 input mode configuration. Offset: 0x02C Reset value: 0x0000_0000 Reserved Type/Reset Reserved CH3PSC CH3CCS Type/Reset 0 RW 0 RW 0 RW...
Page 337 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [3:0] TI3F Channel 3 Input Source TI3 Filter Setting These bits define the frequency divide ratio used to sample the TI3 signal. The digital filter in the GPTM is an N-event counter where N is defined as how many...
Page 338: Channel 0 Output Configuration Register - Ch0Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 0 Output Configuration Register – CH0OCFR This register specifies the channel 0 output mode configuration. Offset: 0x040 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH0OM[3] Type/Reset Reserved CH0IMAE CH0PRE Reserved...
Page 339 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [8][2:0] CH0OM[3:0] Channel 0 Output Mode Setting These bits define the functional types of the output reference signal CH0OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
Page 340: Channel 1 Output Configuration Register - Ch1Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 1 Output Configuration Register – CH1OCFR This register specifies the channel 1 output mode configuration. Offset: 0x044 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH1OM[3] Type/Reset Reserved CH1IMAE CH1PRE Reserved...
Page 341 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [8][2:0] CH1OM[3:0] Channel 1 Output Mode Setting These bits define the functional types of the output reference signal CH1OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
Page 342: Channel 2 Output Configuration Register - Ch2Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 2 Output Configuration Register – CH2OCFR This register specifies the channel 2 output mode configuration. Offset: 0x048 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH2OM[3] Type/Reset Reserved CH2IMAE CH2PRE Reserved...
Page 343 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [8][2:0] CH2OM[3:0] Channel 2 Output Mode Setting These bits define the functional types of the output reference signal CH2OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
Page 344: Channel 3 Output Configuration Register - Ch3Ocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 3 Output Configuration Register – CH3OCFR This register specifies the channel 3 output mode configuration. Offset: 0x04C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH3OM[3] Type/Reset Reserved CH3IMAE CH3PRE Reserved...
Page 345 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [8][2:0] CH3OM[3:0] Channel 3 Output Mode Setting These bits define the functional types of the output reference signal CH3OREF 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
Page 346: Channel Control Register - Chctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel Control Register – CHCTR This register contains the channel capture input or compare output function enable control bits. Offset: 0x050 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3E...
Page 347 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions CH1NE Channel 1 Capture/Compare Complementary Enable 0: Off – Channel 1 complementary output CH1NO is not active. The CH1NO level is then determined by the condition of the CHMOE, CHOSSI, CHOSSR, CH1OIS, CH1OISN and CH1E bits.
Page 348: Channel Polarity Configuration Register - Chpolr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel Polarity Configuration Register – CHPOLR This register contains the channel capture input or compare output polarity control. Offset: 0x054 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3P CH2NP...
Page 349: Channel Break Configuration Register - Chbrkcfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions CH0P Channel 0 Capture/Compare Polarity - When Channel 0 is configured as an input (CH0CCS = 0x1/0x2/0x3) 0: Capture event occurs on a Channel 0 rising edge 1: Capture event occurs on a Channel 0 falling edge...
Page 350: Channel Break Control Register - Chbrkctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel Break Control Register – CHBRKCTR This register specifies the channel break control bits. Offset: 0x070 Reset value: 0x0000_0000 CHDTG Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW...
Page 351 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [11:8] Break Input Filter Setting These bits define the frequency ratio used to sample the MT_BRK signal. The digital filter in the MCTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
Page 352: Timer Pdma/Interrupt Control Register - Dictr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Timer PDMA/Interrupt Control Register – DICTR This register contains the timer PDAM and interrupt enable control bits. Offset: 0x074 Reset value: 0x0000_0000 Reserved TEVDE UEV2DE UEV1DE Type/Reset 0 RW 0 RW Reserved...
Page 353 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions UEV1IE Update event 1 Interrupt Enable 0: Update event 1 interrupt is disabled 1: Update event 1 interrupt is enabled CH3CCIE Channel 3 Capture/Compare Interrupt Enable 0: Channel 3 interrupt is disabled...
Page 354: Timer Event Generator Register - Evgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Timer Event Generator Register – EVGR This register contains the software event generation bits. Offset: 0x078 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved BRKG TEVG UEV2G UEV1G Type/Reset 0 WO 0 WO...
Page 355 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions CH3CCG Channel 3 Capture/Compare Generation A Channel 3 capture/compare event can be generated by setting this bit. It is cleared by hardware automatically. 0: No action 1: Capture/compare event is generated on channel 3 If Channel 3 is configured as an input, the counter value is captured into the CH3CCR register and then the CH3CCIF bit is set.
Page 356: Timer Interrupt Status Register - Intsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Timer Interrupt Status Register – INTSR This register stores the timer interrupt status. Offset: 0x07C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved BRKIF TEVIF UEV2IF UEV1IF Type/Reset 0 W0C 0 W0C...
Page 357 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions CH2OCF Channel 2 Over-capture Flag This flag is set by hardware and cleared by software. 0: No over-capture event is detected 1: Capture event occurs again when the CH2CCIF bit is already set and it is not...
Page 358: Timer Counter Register - Cntr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions CH0CCIF Channel 0 Capture/Compare Interrupt Flag - Channel 0 is configured as an output 0: No match event occurs 1: The contents of the counter CNTR have matched the content of the CH0CCR...
Page 359: Timer Prescaler Register - Pscr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Timer Prescaler Register – PSCR This register specifies the timer prescaler value to generate the counter clock. Offset: 0x084 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PSCV Type/Reset 0 RW 0 RW...
Page 360: Timer Counter-Reload Register - Crr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Timer Counter-Reload Register – CRR This register specifies the timer Counter-Reload value. Offset: 0x088 Reset value: 0x0000_FFFF Reserved Type/Reset Reserved Type/Reset Type/Reset 1 RW 1 RW 1 RW 1 RW 1 RW...
Page 361: Channel 0 Capture/Compare Register - Ch0Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 0 Capture/Compare Register – CH0CCR This register specifies the timer channel 0 capture/compare value. Offset: 0x090 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH0CCV Type/Reset 0 RW 0 RW 0 RW...
Page 362: Channel 2 Capture/Compare Register - Ch2Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [15:0] CH1CCV Channel 1 Capture/Compare Value - When Channel 1 is configured as an output The CH1CCR value is compared with the counter value and the comparison result is used to trigger the CH1OREF output signal.
Page 363: Channel 3 Capture/Compare Register - Ch3Ccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 3 Capture/Compare Register – CH3CCR This register specifies the timer channel 3 capture/compare value. Offset: 0x09C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH3CCV Type/Reset 0 RW 0 RW 0 RW...
Page 364: Channel 0 Asymmetric Compare Register - Ch0Acr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 0 Asymmetric Compare Register – CH0ACR This register specifies the timer channel 0 asymmetric compare value. Offset: 0x0A0 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH0ACV Type/Reset 0 RW 0 RW...
Page 365: Channel 2 Asymmetric Compare Register - Ch2Acr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 2 Asymmetric Compare Register – CH2ACR This register specifies the timer channel 2 asymmetric compare value. Offset: 0x0A8 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2ACV Type/Reset 0 RW 0 RW...
Page 366: Single-Channel Timer (Sctm)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Single-Channel Timer (SCTM) Introduction The Single-Channel Timer consists of one 16-bit up-counter, one 16-bit Capture/Compare Register (CCR), one 16-bit Counter-Reload Register (CRR) and several control/status registers. It can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as PWM output.
Page 367: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Features 16-bit auto-reload up-counter ▆ 16-bit programmable prescaler that allows division of the prescaler clock source by any factor ▆ between 1 and 65536 to generate the counter clock frequency Single channel for: ▆...
Page 368: Clock Controller
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Clock Controller The following describes the Timer Module clock controller which determines the clock source of the internal prescaler counter. Internal APB clock f ▆ CLKIN The default internal clock source is the APB clock f...
Page 369: Trigger Controller
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Trigger Controller The trigger controller is used to select the trigger source and setup the trigger level or edge trigger condition. For the internal trigger input, it can be selected by the Trigger Selection bits TRSEL in the TRCFR register.
Page 370: Slave Controller
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Slave Controller The SCTM can be synchronized with an external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which is selected by the SMSEL field in the MDCFR register.
Page 371: Figure 122. Sctm In Pause Mode
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Pause Mode In the Pause Mode, the selected STI input signal level is used to control the counter start/stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level, here the counter will maintain its present value and will not be reset.
Page 372: Channel Controller
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel Controller The SCTM channel can be used as the capture input or compare match output. The capture input or compare match output channel is composed of a preload register and a shadow register. Data access of the APB bus is always implemented by reading/writing the preload register.
Page 373: Figure 125. Input Capture Mode
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Capture Counter Value Transferred to CHCCR When the channel is used as a capture input, the counter value is captured into the Channel Capture/Compare Register (CHCCR) when an effective input signal transition occurs. Once the capture event occurs, the CHCCIF flag in the INTSR register is set accordingly.
Page 374: Input Stage
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Input Stage The input stage consists of a digital filter, a channel polarity selection, edge detection and a channel prescaler. The channel input signal (TI) is sampled by a digital filter to generate a filtered input signal TIFP.
Page 375: Output Stage
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Output Stage The SCTM output has function for compare match or PWM output. The channel output SCTM_ CHO is controlled by the CHOM, CHP and CHE bits in the corresponding CHOCFR, CHPOLR and CHCTR registers.
Page 376: Figure 129. Toggle Mode Channel Output Reference Signal (Chpre = 0)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Counter Value CHOM=0x3, CHPRE=0 (Output toggle, preload disable) CHCCR (New value 2) CHCCR (New value 3) CHCCR (New value 1) CHCCR Time Update CHCCR value CHOREF (Update Event) Figure 129. Toggle Mode Channel Output Reference Signal (CHPRE = 0)
Page 377: Update Management
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Counter Value Counter Value Counter Value CHCCR CHCCR CHCCR = 0x0000 CHOM = 0x6 100% CHOREF CHOREF CHOREF CHCCIF CHCCIF CHCCIF CHOM = 0x7 CHOREF Figure 131. PWM Mode Channel Output Reference Signal...
Page 378: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Update Event Management Counter Overflow UEVG UEV (Update PSCR, CRR, CHCCR Shadow Registers) Slave Restart mode UEVDIS Update Event Interrupt Management Counter Overflow UEV interrupt UEVG UEVDIS Slave Restart mode UGDIS Figure 132. Update Event Setting Diagram Register Map The following table shows the SCTM registers and reset values.
Page 379: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Descriptions Timer Counter Configuration Register – CNTCFR This register specifies the SCTM counter configuration. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CKDIV Type/Reset 0 RW Reserved UGDIS UEVDIS...
Page 380: Timer Mode Configuration Register - Mdcfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Timer Mode Configuration Register – MDCFR This register specifies the SCTM slave mode selection. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved SMSEL Type/Reset 0 RW 0 RW Reserved Type/Reset...
Page 381: Timer Trigger Configuration Register - Trcfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Timer Trigger Configuration Register – TRCFR This register specifies the trigger source selection of SCTM. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved TRSEL Type/Reset 0 RW 0 RW...
Page 382: Timer Control Register - Ctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Timer Control Register – CTR This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE). Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CRBE Type/Reset...
Page 383: Channel Input Configuration Register - Chicfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel Input Configuration Register – CHICFR This register specifies the channel input mode configuration. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CHPSC CHCCS Type/Reset 0 RW 0 RW 0 RW Reserved...
Page 384 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [3:0] Channel Input Source TI Filter Setting These bits define the frequency divided ratio used to sample the TI signal. The Digital filter in the SCTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
Page 385: Channel Output Configuration Register - Chocfr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel Output Configuration Register – CHOCFR This register specifies the channel output mode configuration. Offset: 0x040 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CHPRE Reserved CHOM Type/Reset 0 RW...
Page 386: Channel Control Register - Chctr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel Control Register – CHCTR This register contains the channel capture input or compare output function enable control bit. Offset: 0x050 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset...
Page 387: Channel Polarity Configuration Register - Chpolr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel Polarity Configuration Register – CHPOLR This register contains the channel capture input or compare output polarity control. Offset: 0x054 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Bits...
Page 388: Timer Interrupt Control Register - Dictr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Timer Interrupt Control Register – DICTR This register contains the timer interrupt enable control bits. Offset: 0x074 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVIE Reserved UEVIE Type/Reset Reserved CHCCIE Type/Reset...
Page 389: Timer Event Generator Register - Evgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Timer Event Generator Register – EVGR This register contains the software event generation bits. Offset: 0x078 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVG Reserved UEVG Type/Reset Reserved CHCCG Type/Reset Bits...
Page 390: Timer Interrupt Status Register - Intsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Timer Interrupt Status Register – INTSR This register stores the timer interrupt status. Offset: 0x07C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVIF Reserved UEVIF Type/Reset Reserved CHOCF Reserved CHCCIF Type/Reset...
Page 391: Timer Counter Register - Cntr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Timer Counter Register – CNTR This register stores the timer counter value. Offset: 0x080 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CNTV Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...
Page 392: Timer Counter-Reload Register - Crr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Timer Counter-Reload Register – CRR This register specifies the timer Counter-Reload value. Offset: 0x088 Reset value: 0x0000_FFFF Reserved Type/Reset Reserved Type/Reset Type/Reset 1 RW 1 RW 1 RW 1 RW 1 RW...
Page 393: Channel Capture/Compare Register - Chccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel Capture/Compare Register – CHCCR This register specifies the timer channel capture/compare value. Offset: 0x090 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CHCCV Type/Reset 0 RW 0 RW 0 RW 0 RW...
Page 394: Basic Function Timer (Bftm)
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Basic Function Timer (BFTM) Introduction The Basic Function Timer is a 32-bit up-counting counter designed to measure time intervals, generate one shot pulses or generate repetitive interrupts. The BFTM can operate in two modes which are repetitive and one shot modes.
Page 395: Functional Description
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Functional Description The BFTM is a 32-bit up-counting counter which is driven by the BFTM APB clock, PCLK. The counter value can be changed or read at any time even when the timer is counting. The BFTM supports two operating modes known as the repetitive mode and one shot mode allowing the measurement of time intervals or the generation of periodic time durations.
Page 396: One Shot Mode
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 One Shot Mode By setting the OSM bit in BFTMCR register to 1, the BFTM will operate in the one shot mode. The BFTM starts to count when the CEN bit is set to 1 by the application program. The counter value will remain unchanged if the CEN bit is cleared to 0 by the application program.
Page 397: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Map The following table shows the BFTM registers and reset values. Table 42. BFTM Register Map Register Offset Description Reset Value BFTMCR 0x000 BFTM Control Register 0x0000_0000 BFTMSR 0x004 BFTM Status Register...
Page 398: Bftm Status Register - Bftmsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 BFTM Status Register – BFTMSR This register specifies the BFTM status. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Bits Field Descriptions BFTM Compare Match Interrupt Flag...
Page 399: Bftm Counter Value Register - Bftmcntr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 BFTM Counter Value Register – BFTMCNTR This register specifies the BFTM counter value. Offset: 0x008 Reset value: 0x0000_0000 Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW...
Page 400: Real Time Clock (Rtc)
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Real Time Clock (RTC) Introduction The Real Time Clock, RTC, circuitry includes the APB interface, a 24-bit up-counter, a control register, a prescaler, a compare register and a status register. Most of the RTC circuits are located in...
Page 401: Functional Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Functional Descriptions RTC Related Register Reset The RTC registers can be reset by either a V Domain power on reset, POR, or by a V Domain software reset by setting the PWCURST bit in the PWRCR register. Other reset events have no effect to clear the RTC registers.
Page 402: Rtc Counter Operation
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 RTC Counter Operation The RTC provides a 24-bit up-counter which increases at the falling edge of the CK_SECOND clock and whose value can be read from the RTCCNT register asynchronously via the APB bus.
Page 403: Table 44. Rtcout Output Mode And Active Level Setting
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Table 44. RTCOUT Output Mode and Active Level Setting ROWM ROES RTCOUT Output Waveform RTCCMP RTCCNT RTCOUT (ROAP = 0) (Compare match) RTCOUT (ROAP = 1) ROLF (Pulse mode) RTCCMP RTCCNT RTCOUT (ROAP = 0)
Page 404: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Map The following table shows the RTC registers and reset values. Note all the registers in this unit are located at the V power domain. Table 45. RTC Register Map Register...
Page 405: Rtc Compare Register - Rtccmp
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 RTC Compare Register – RTCCMP This register defines a specific value to be compared with the RTC counter value. Address: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset RTCCMPV Type/Reset 0 RW 0 RW...
Page 406: Rtc Control Register - Rtccr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 RTC Control Register – RTCCR This register specifies a range of RTC circuitry control bits. Address: 0x008 Reset value: 0x0000_0F00 Reserved Type/Reset Reserved ROLF ROAP ROWM ROES ROEN Type/Reset 0 RW 0 RW...
Page 407 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [11:8] RPRE RTC Clock Prescaler Select CK_SECOND = CK_RTC / 2 RPRE 0000: CK_SECOND = CK_RTC / 2 0001: CK_SECOND = CK_RTC / 2 0010: CK_SECOND = CK_RTC / 2 …...
Page 408: Rtc Status Register - Rtcsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 RTC Status Register – RTCSR This register stores the counter flags. Address: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved OVFLAG CMFLAG CSECFLAG Type/Reset 0 RC 0 RC Bits...
Page 409: Rtc Interrupt And Wakeup Enable Register - Rtciwen
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 RTC Interrupt and Wakeup Enable Register – RTCIWEN This register contains the interrupt and wakeup enable bits. Address: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved OVWEN CMWEN CSECWEN Type/Reset 0 RW...
Page 410: Watchdog Timer (Wdt)
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Watchdog Timer (WDT) Introduction The Watchdog Timer is a hardware timing circuitry that can be used to detect a system lock-up due to software trapped in a deadlock. The Watchdog Timer can be operated in a reset mode. The Watchdog Timer will generate a reset when the counter counts down to a zero value.
Page 411: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Features Clock source from either the internal 32 kHz RC oscillator (LSI) or the external 32,768 Hz ▆ oscillator (LSE) Can be independently setup to keep running or to stop when entering the Sleep or Deep-Sleep1 ▆...
Page 412: Figure 139. Watchdog Timer Behavior
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 When the system enters the Sleep mode or Deep-Sleep1 mode, the Watchdog Timer counter will either continue to count or stop depending on the WDTSHLT field setup in the WDTMR0 register. However, the Watchdog Timer will always stop when the system is in the Deep-Sleep2 mode.
Page 413: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Map The following table shows the Watchdog Timer registers and reset values. Table 46. Watchdog Timer Register Map Register Offset Description Reset Value WDTCR 0x000 Watchdog Timer Control Register 0x0000_0000 WDTMR0...
Page 414: Watchdog Timer Mode Register 0 - Wdtmr0
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Watchdog Timer Mode Register 0 – WDTMR0 This register specifies the Watchdog timer Counter-Reload value and reset enable control. Offset: 0x004 Reset value: 0x0000_0FFF Reserved Type/Reset Reserved WDTEN Type/Reset WDTSHLT WDTRSTEN Reserved...
Page 415: Watchdog Timer Mode Register 1 - Wdtmr1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Watchdog Timer Mode Register 1 – WDTMR1 This register specifies the Watchdog delta value and the prescaler selection. Offset: 0x008 Reset value: 0x0000_7FFF Reserved Type/Reset Reserved Type/Reset Reserved WPSC WDTD Type/Reset 1 RW...
Page 416: Watchdog Timer Status Register - Wdtsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Watchdog Timer Status Register – WDTSR This register specifies the Watchdog timer status. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved WDTERR WDTUF Type/Reset 0 WC Bits Field...
Page 417: Watchdog Timer Protection Register - Wdtpr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Watchdog Timer Protection Register – WDTPR This register specifies the Watchdog timer protect key configuration. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PROTECT Type/Reset 0 RW 0 RW 0 RW...
Page 418: Watchdog Timer Clock Selection Register - Wdtcsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Watchdog Timer Clock Selection Register – WDTCSR This register specifies the Watchdog timer clock source selection and lock configuration. Offset: 0x018 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved WDTLOCK...
Page 419: Inter-Integrated Circuit (I C)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Inter-Integrated Circuit (I Introduction The I C Module is an internal circuit allowing communication with an external I C interface which is an industry standard two-line serial interface used for connection to external hardware. These two serial lines are known as a serial data line, SDA, and a serial clock line, SCL.
Page 420: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Features Two-wire I C serial interface ▆ ● Serial data line (SDA) and serial clock (SCL) Multiple speed modes ▆ ● Standard mode – 100 kHz ● Fast mode – 400 kHz ●...
Page 421: Data Validity
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 START Condition STOP Condition Figure 141. START and STOP Condition Data Validity The data on the SDA line must be stable during the high period of the SCL clock. The SDA data state can only be changed when the clock signal on the SCL line is in a low state.
Page 422: Figure 143. 7-Bit Addressing Mode
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Sent by master Slave address Sent by slave S = START condition R/W = 1: Read direction = 0: Write direction ACK = Acknowledge bit Figure 143. 7-bit Addressing Mode 10-bit Address Format In order to prevent address clashes, due to the limited range of the 7-bit addresses, a new 10-bit address scheme has been introduced.
Page 423: Data Transfer And Acknowledge
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Data Transfer and Acknowledge Once the slave device address has been matched, the data can be transmitted to or received from the slave device according to the transfer direction specified by the R/W bit. Each byte is followed by an acknowledge bit on the 9 SCL clock.
Page 424: Arbitration
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Arbitration A master may start a transfer only if the I C bus line is in the free or idle mode. If two or more masters generate a START signal at approximately the same time, an arbitration procedure will occur.
Page 425: Address Mask Enable
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Address Mask Enable The I C module provides an address mask function for users to decide which address bit can be ignored during the comparison with the address frame sent from the master. The ADRS flag will be asserted when the unmasked address bits and the address frame sent from the master are matched.
Page 426: Figure 149. Master Transmitter Timing Diagram
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Close / Continue Transmission After transmitting the last data byte, the STOP bit in the I2CCR register can be set to terminate the transmission or re-assign another slave device by configuring the I2CTAR register to restart a new transfer.
Page 427: Figure 150. Master Receiver Timing Diagram
® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 to 1, the RXBF bit in the I2CSR register will be set to 1 and the SCL line will be held at a logic low state. When this situation occurs, data from the I2CDR register should be read to continue the data transfer process.
Page 428: Figure 151. Slave Transmitter Timing Diagram
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Receive Not-Acknowledge When the slave device receives a Not-Acknowledge signal, the RXNACK bit in the I2CSR Register is set but it will not hold the SCL line. Writing “1” to RXNACK will clear the RXNACK flag.
Page 429: Conditions Of Holding Scl Line
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 STOP Condition When the slave device detects a STOP condition, the STO flag bit in the I2CSR register is set to indicate that the I C interface transmission is terminated. Reading the I2CSR register can clear the STO flag bit.
Page 430: C Timeout Function
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Type Condition Description Eliminating Condition No matter in address or data frame, once Set TAR Master receives NACK received an NACK signal will hold SCL line in Set STOP master mode. Event...
Page 431: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Map The following table shows the I C registers and reset values. The PDMA related describes are only available for the HT32F54243/HT32F54253 devices. Table 48. I C Register Map Register Offset...
Page 432 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [13] COMBFILTEREN SDA or SCL Input Combinational Filter Enable Bit 0: Combinational filter is disabled 1: Combinational filter is enabled [12] ENTOUT C Timeout Function Enable Control 0: Timeout Function is disabled...
Page 433: I 2 C Interrupt Enable Register - I2Cier
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 C Interrupt Enable Register – I2CIER This register specifies the corresponding I C interrupt enable bits. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved RXBFIE TXDEIE RXDNEIE Type/Reset 0 RW 0 RW...
Page 434: I 2 C Address Register - I2Caddr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions STOIE STOP Condition Detected Interrupt Enable Bit 0: Interrupt is disabled 1: Interrupt is enabled The bit is used for the I C slave mode only. STAIE START Condition Transmit Interrupt Enable Bit...
Page 435: I 2 C Status Register - I2Csr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 C Status Register – I2CSR This register contains the I C operation status. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved TXNRX MASTER BUSBUSY RXBF TXDE RXDNE Type/Reset 0 RO 0 RO...
Page 436 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [17] TXDE Data Register Empty in Transmitter Mode 0: Data register I2CDR is not empty 1: Data register I2CDR is empty This bit is set when the I2CDR register is empty in the Transmitter mode. Note that the TXDE bit will be set after the address frame is being transmitted to inform that the data to be transmitted should be loaded into the I2CDR register.
Page 437 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions ADRS Address Transmit (master mode) / Address Receive (slave mode) Flag Address Sent in Master Mode: 0: Address frame has not been transmitted 1: Address frame has been transmitted For the 7-bit addressing mode, this bit is set after the master device receives the address frame acknowledge bit sent from the slave device.
Page 438: C Scl High Period Generation Register - I2Cshpgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 C SCL High Period Generation Register – I2CSHPGR This register specifies the I C SCL clock high period interval. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset SHPG Type/Reset 0 RW...
Page 439: I 2 C Scl Low Period Generation Register - I2Cslpgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 C SCL Low Period Generation Register – I2CSLPGR This register specifies the I C SCL clock low period interval. Offset: 0x014 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset SLPG Type/Reset 0 RW...
Page 440: C Data Register - I2Cdr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 C Data Register – I2CDR This register specifies the data to be transmitted or received by the I C module. Offset: 0x018 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset DATA...
Page 441: I 2 C Target Register - I2Ctar
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 C Target Register – I2CTAR This register specifies the target device address to be communicated. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset 0 RW 0 RW Type/Reset 0 RW...
Page 442: I 2 C Address Mask Register - I2Caddmr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 C Address Mask Register – I2CADDMR This register specifies which bit of the I C address is masked and not compared with corresponding bit of the received address frame. Offset: 0x020 Reset value: 0x0000_0000...
Page 443: I 2 C Address Snoop Register - I2Caddsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 C Address Snoop Register – I2CADDSR This register is used to indicate the address frame value appeared on the I C bus. Offset: 0x024 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved...
Page 444: I 2 C Timeout Register - I2Ctout
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 C Timeout Register – I2CTOUT This register specifies the I C timeout counter preload value and clock prescaler ratio. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset 0 RW 0 RW...
Page 445: Serial Peripheral Interface (Spi)
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Serial Peripheral Interface (SPI) Introduction The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive functions in both master or slave mode. The SPI interface uses 4 pins, among which are the serial data input and output lines SPI_MISO and SPI_MOSI, the clock line SPI_SCK, and the slave select line SPI_SEL.
Page 446: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Features Master or slave mode ▆ Master mode speed up to f ▆ PCLK Slave mode speed up to f ▆ PCLK Programmable data frame length up to 16 bits ▆ FIFO Depth: 8 levels ▆...
Page 447: Spi Serial Frame Format
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 SPI Serial Frame Format The SPI interface format is based on the Clock Polarity, CPOL, and the Clock Phase, CPHA, configurations. Clock Polarity Bit – CPOL ▆ When the Clock Polarity bit is cleared to 0, the SCK line idle state is low. When the Clock Polarity bit is set to 1, the SCK line idle state is high.
Page 448: Figure 156. Spi Continuous Data Transfer Timing Diagram - Cpol = 0, Cpha = 0
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 The accompanying figure shows the continuous data transfer timing diagram of this format. Note that the SEL signal must change to an inactive level between each data frame. SEL (SELAP=0) SEL (SELAP=1)
Page 449: Figure 159. Spi Single Byte Transfer Timing Diagram - Cpol = 1, Cpha = 0
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 CPOL = 1, CPHA = 0 In this format, the received data is sampled on the SCK line falling edge while the transmitted data is changed on the SCK line rising edge. In the master mode, the first bit is driven when data is written into the SPIDR register.
Page 450: Figure 161. Spi Single Byte Transfer Timing Diagram - Cpol = 1, Cpha = 1
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 CPOL = 1, CPHA = 1 In this format, the received data is sampled on the SCK line rising edge while the transmitted data is changed on the SCK line falling edge. In the master mode, the first bit is driven when data is written into the SPIDR register.
Page 451: Spi Dual Mode
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 SPI Dual Mode When in the Master mode, the SPI interface operation can be configured to Dual mode. A more efficient data transfer can then be implemented by using this Dual mode together with the four formats described above.
Page 452: Figure 165. Spi Dual Mode Bit Sequence - Cpol = 1, Cpha = 0, Dfl = 0X8 (16-Bit), Msb Transmitted
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 DUALEN SEL (SELAP=0) SEL (SELAP=1) ½ MOSI RX[6] RX[4] RX[2] RX[0] RX[14] RX[12] RX[10] RX[8] MISO RX[7] RX[5] RX[3] RX[1] RX[15] RX[13] RX[11] RX[9] Data sampled Figure 165. SPI Dual Mode Bit Sequence – CPOL = 1, CPHA = 0, DFL = 0x8 (16-bit), MSB...
Page 453: Status Flags
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 The accompanying figure shows the bit sequence of the SPI Dual mode reading data from an external serial SPI Flash. DUALEN Command Address Dummy Data ∙∙∙∙ ∙∙∙∙ ∙∙∙∙ ∙∙∙∙ MOSI ∙∙∙∙ ∙∙∙∙...
Page 454: Figure 168. Spi Multi-Master Slave Environment
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Mode Fault – MF The mode fault flag can be used to detect SPI bus usage in the SPI multi-master mode. For the multi-master mode, the SPI module is configured as a master device and the SEL signal is set as an input signal.
Page 455: Table 51. Spi Mode Fault Trigger Conditions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Table 51. SPI Mode Fault Trigger Conditions Mode Fault Descriptions 1. SPI Master mode. 2. SELOEN = 0 in the SPICR0 register – SPI_SEL pin is configured to be the Trigger Condition input mode.
Page 456: Pdma Interface (Ht32F54243/Ht32F54253 Only)
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 PDMA Interface (HT32F54243/HT32F54253 only) The PDMA interface is integrated in the SPI module. The PDMA function can be enabled by setting the TXDMAE or RXDMAE bit to 1 in the transmitter or receiver mode respectively. When...
Page 457: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Descriptions SPI Control Register 0 – SPICR0 This register specifies the SEL control and the SPI enable bits. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset SELHT GUADT Type/Reset 0 RW...
Page 458 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions SSELC Software Slave Select Control 0: Set the SEL output to an inactive state 1: Set the SEL output to an active state The application software can set the SEL output to an active or inactive state by configuring the SSELC bit.
Page 459: Spi Control Register 1 - Spicr1
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 SPI Control Register 1 – SPICR1 This register specifies the SPI parameters including the data length, the transfer format, the SEL active polarity/ mode, the LSB/MSB control and the master/slave mode. Offset:...
Page 460 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [10:8] FORMAT SPI Data Transfer Format These three bits are used to determine the data transfer format of the SPI interface. FORMAT [2:0] CPOL CPHA Others Reserved CPOL: Clock Polarity...
Page 461: Spi Interrupt Enable Register - Spiier
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 SPI Interrupt Enable Register – SPIIER This register contains the corresponding SPI interrupt enable control bit. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset TOIEN SAIEN MFIEN ROIEN WCIEN...
Page 462: Spi Clock Prescaler Register - Spicpr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 SPI Clock Prescaler Register – SPICPR This register specifies the SPI clock prescaler ratio. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Type/Reset 0 RW 0 RW 0 RW 0 RW...
Page 463: Spi Data Register - Spidr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 SPI Data Register – SPIDR This register stores the SPI received or transmitted Data. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Type/Reset 0 RW 0 RW 0 RW 0 RW...
Page 464: Spi Status Register - Spisr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 SPI Status Register – SPISR This register contains the relevant SPI status. Offset: 0x014 Reset value: 0x0000_0003 Reserved Type/Reset Reserved Type/Reset Reserved BUSY Type/Reset RXBNE TXBE Type/Reset 0 WC 0 WC 0 WC...
Page 465: Spi Fifo Control Register - Spifcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions RXBNE RX Buffer Not Empty flag 0: RX buffer is empty 1: RX buffer is not empty This bit indicates the RX buffer status in the non-FIFO mode. It is also used to indicate if the RX FIFO trigger level has been reached in the FIFO mode.
Page 466: Spi Fifo Status Register - Spifsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [7:4] RXFTLS RX FIFO Trigger Level Select 0000: Trigger level is 0 0001: Trigger level is 1 1000: Trigger level is 8 Others: Reserved The RXFTLS field is used to specify the RX FIFO trigger level. When the number of...
Page 467: Spi Fifo Time Out Counter Register - Spiftocr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [3:0] TXFS TX FIFO Status 0000: TX FIFO empty 0001: TX FIFO contains 1 data … 1000: TX FIFO contains 8 data Others: Reserved SPI FIFO Time Out Counter Register – SPIFTOCR This register stores the SPI RX FIFO time out counter value.
Page 468: Universal Synchronous Asynchronous Receiver Transmitter (Usart)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Universal Synchronous Asynchronous Receiver Transmitter (USART) Introduction The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. The USART is used to translate data between parallel and serial interfaces, and is also commonly used for RS232 standard communication.
Page 469: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Features Supports both asynchronous and clocked synchronous serial communication modes ▆ Full Duplex Communication Capability ▆ Programmable baud rate clock frequency up to (f /16) MHz for asynchronous mode and ▆ PLCK...
Page 470: Baud Rate Generation
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 7-Bit Data Format (WLS[1:0]=b00,PBE=0) Next Start Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Stop Bit 8-Bit Data Format (WLS[1:0]=b01,PBE=0) Next Start Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6...
Page 471: Table 54. Baud Rate Deviation Error Calculation - Ck_Usart = 40 Mhz
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Table 54. Baud Rate Deviation Error Calculation – CK_USART = 40 MHz Baud Rate CK_USART = 40 MHz Deviation Kbps Actual Error Rate 16667 0.00% 4167 -0.01% 19.2 19.2 2083 0.02% 57.6 57.6...
Page 472: Hardware Flow Control
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Hardware Flow Control The USART supports the hardware flow control function which is enabled by setting the HFCEN bit in the USRCR register to 1. It is possible to control the serial data flow between two USART devices by using the CTS input and the RTS output.
Page 473: Irda
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 When the USART CTS pin is forced to a logic high state during a data transmission period, the current data transmission will be continued until the stop bit is completed. The following figure shows an example of communication with CTS flow control.
Page 474 Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 IrDA Normal Mode For the IrDA normal mode, the width of each transmitted pulse generated by the transmitter modulator is specified as 3/16 of the baud rate clock period. The receiver pulse width for the IrDA receiver demodulator is based on the IrDA receive debounce filter which is implement using an 8-bit down-counting counter.
Page 475: Rs485 Mode
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 TX_Data Transmitter Modulation TXSEL RX_Data Receiver Demodulation IrDAEN Figure 176. USART I/O and IrDA Block Diagram RS485 Mode The RS485 mode of USART provides the data transmission on interface transmitted over a 2-wire twisted pair bus.
Page 476: Figure 177. Rs485 Interface And Waveform
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 RS-485 Transceiver Differential USART TG = 4 Reference Divisor Clock Stop D6 D7 Parity Start D1 D2 D3 D4 D5 TXENP = 0 TXENP = 1 Figure 177. RS485 Interface and Waveform RS485 Normal Multi-Drop Operation Mode –...
Page 477: Synchronous Master Mode
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 RS485 Auto Address Detection Operation Mode – AAD Except in the Normal Multi-drop Operation Mode, the RS485 mode can operate in the Auto Address Detection Operation Mode, AAD, when it is configured as an addressable slave. This mode is enabled by setting the RSAAD field to 1 in the RS485CR register.
Page 478: Figure 179. 8-Bit Format Usart Synchronous Waveform
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 (CPS=1, WLS[1:0]=b01, PBE=0) Clock (CPO=0) Clock (CPO=1) USART TX Start Stop (From Master to Slave) USART RX (From Slave to Master) (CPS=1, WLS[1:0]=b00, PBE=1) Clock (CPO=0) Clock (CPO=1) USART TX Start Parity...
Page 479: Interrupts And Status
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Interrupts and Status The USART can generate interrupts when the following events occur and the corresponding interrupt enable bits are set: Receive FIFO time-out interrupt: An interrupt is generated when the USART receive FIFO is not ▆...
Page 480: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Descriptions USART Data Register – USRDR The register is used to access the USART transmitted and received FIFO data. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Type/Reset...
Page 481: Usart Control Register - Usrcr
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 USART Control Register – USRCR The register specifies the serial parameters such as data length, parity and stop bit for the USART. It also contains the USART enable control bits together with the USART mode and data transfer mode selection.
Page 482 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [10] Number of STOP bit 0: One STOP bit is generated in the transmitted data 1: Two STOP bits are generated when 8-bit or 9-bit word length is selected...
Page 483: Usart Fifo Control Register - Usrfcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 USART FIFO Control Register – USRFCR This register specifies the USART FIFO control and configurations including threshold level and reset function together with the USART FIFO status. Offset: 0x008 Reset value: 0x0000_0000...
Page 484: Usart Interrupt Enable Register - Usrier
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions TX FIFO Reset Setting this bit will generate a reset pulse to reset the TX FIFO which will empty the TX FIFO, i.e., the TX pointer will be reset to 0 after a reset signal. This bit returns to 0 automatically after the reset pulse is generated.
Page 485 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions FEIE Framing Error Interrupt Enable 0: Disable 1: Enable If this bit is set, an interrupt will be generated when the FEI bit in the USRSIFR register is set.
Page 486: Usart Status & Interrupt Flag Register - Usrsifr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 USART Status & Interrupt Flag Register – USRSIFR This register contains the corresponding USART status. Offset: 0x010 Reset value: 0x0000_0980 Reserved Type/Reset Reserved Type/Reset Reserved CTSS CTSC RSADD Type/Reset 1 WC 0 WC...
Page 487 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions RXTOF Receive FIFO Time-Out Flag 0: RX FIFO Time-Out does not occur 1: RX FIFO Time-Out occurs The RXTOF bit will be set if the RX FIFO is not empty and no activities have occurred in the RX FIFO during the time-out duration specified by the RXTOC field.
Page 488: Usart Timing Parameter Register - Usrtpr
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 USART Timing Parameter Register – USRTPR This register contains the USART timing parameters including the transmitter time guard parameters and the receive FIFO time-out value together with the RX FIFO time-out interrupt enable control.
Page 489: Usart Irda Control Register - Irdacr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 USART IrDA Control Register – IrDACR This register is used to control the IrDA mode of USART. Offset: 0x018 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset IrDAPSC Type/Reset 0 RW 0 RW...
Page 490: Usart Rs485 Control Register - Rs485Cr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions IrDAEN IrDA Enable control 0: Disable IrDA mode 1: Enable IrDA mode USART RS485 Control Register – RS485CR This register is used to control the RS485 mode of USART.
Page 491: Usart Synchronous Control Register - Syncr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 USART Synchronous Control Register – SYNCR This register is used to control the USART synchronous mode. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Reserved CLKEN Type/Reset 0 RW...
Page 492: Usart Divider Latch Register - Usrdlr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 USART Divider Latch Register – USRDLR The register is used to determine the USART clock divided ratio to generate the appropriate baud rate. Offset: 0x024 Reset value: 0x0000_0010 Reserved Type/Reset Reserved Type/Reset...
Page 493: Usart Test Register - Usrtstr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 USART Test Register – USRTSTR This register controls the USART debug mode. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset 0 RW Bits Field Descriptions [1:0] Loopback Test Mode Select...
Page 494: Universal Asynchronous Receiver Transmitter (Uart)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Universal Asynchronous Receiver Transmitter (UART) Introduction The Universal Asynchronous Receiver Transceiver, UART, provides a flexible full duplex data exchange using asynchronous transfer. The UART is used to translate data between parallel and serial interfaces, and is also commonly used for RS232 standard communication.
Page 495: Features
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Features Supports asynchronous serial communication modes ▆ Full Duplex Communication Capability ▆ Programming baud rate clock frequency up to (f /16) MHz ▆ PCLK Fully programmable serial communication functions including: ▆ ●...
Page 496: Baud Rate Generation
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Baud Rate Generation The baud rate for the UART receiver and transmitter are both set with the same values. The baud rate divisor, BRD, has the following relationship with the UART clock which is known as CK_UART.
Page 497: Interrupts And Status
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Table 59. Baud Rate Deviation Error Calculation – CK_UART = 48 MHz Baud Rate CK_UART = 48 MHz Kbps Actual Deviation Error Rate 20000 0.00% 5000 0.00% 19.2 19.2 2500 0.00% 57.6 57.6...
Page 498: Pdma Interface (Ht32F54243/Ht32F54253 Only)
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 PDMA Interface (HT32F54243/HT32F54253 only) The PDMA interface is integrated in the UART. The PDMA function can be enabled by setting the TXDMAEN or RXDMAEN bit in the URCR register to 1 in the transmit or receive mode respectively.
Page 499: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Descriptions UART Data Register – URDR The register is used to access the UART transmitted and received data. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Type/Reset 0 RW...
Page 500: Uart Control Register - Urcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 UART Control Register – URCR The register specifies the serial parameters such as data length, parity and stop bit for the UART. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved...
Page 501: Uart Interrupt Enable Register - Urier
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions RXDMAEN UART RX DMA Enable 0: Disable 1: Enable TXDMAEN UART TX DMA Enable 0: Disable 1: Enable URRXEN UART RX Enable 0: Disable 1: Enable URTXEN UART TX Enable...
Page 502 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions PEIE Parity Error Interrupt Enable 0: Disable 1: Enable If this bit is set, an interrupt will be generated when the PEI bit in the URSIFR register is set.
Page 503: Uart Status & Interrupt Flag Register - Ursifr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 UART Status & Interrupt Flag Register – URSIFR This register contains the corresponding UART status. Offset: 0x010 Reset value: 0x0000_0180 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset TXDE Reserved RXDR Reserved Type/Reset 0 WC...
Page 504: Uart Divider Latch Register - Urdlr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions Overrun Error Indicator An overrun error will occur only after the receive data register is full and when the next character has been completely received in the receive shift register. The...
Page 505: Uart Test Register - Urtstr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 UART Test Register – URTSTR This register controls the UART debug mode. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset 0 RW Bits Field Descriptions [1:0] Loopback Test Mode Select...
Page 506: Peripheral Direct Memory Access (Pdma)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Peripheral Direct Memory Access (PDMA) Introduction The Peripheral Direct Memory Access circuitry, PDMA, provides 6 unidirectional channels for dedicated peripherals to implement the peripheral-to-memory and memory-to-peripheral data transfer. The memory-to-memory data transfer such as the Flash-to-SRAM or SRAM-to- SRAM type is also supported and requested by the application program.
Page 507: Functional Description
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Functional Description AHB Master The PDMA is an AHB master connected to other AHB peripherals such as the Flash Memory, the SRAM memory and the AHB-to-APB bridge through the bus-matrix. The CPU and PDMA can access different AHB slaves at the same time via the bus-matrix.
Page 508: Channel Transfer
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Table 62. PDMA Channel Assignments PDMA Channel Number (x = 0, 1) (y = 0, 1, 2, 3) (z = 0, 1, 2) SPIx SPI0_RX SPI0_TX SPI1_RX SPI1_TX USARTx USR0_RX USR0_TX USR1_RX...
Page 509: Transfer Request
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Channel 0: priority=very high, block count=2, block length=2 Channel 1: priority=high, block count=3, block length=4 Channel 2: priority=low, block count=3, block length=6 Priority: CH0 > CH1 > CH2 Priority: CH1 > CH2 Priority: CH1 >...
Page 510: Auto-Reload
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Linear Address Mode After data is transferred, the current address will be increased or decreased by 1, 2 or 4 depending upon the data bit width setting. Circular Address Mode After data is transferred, the current address will be increased or decreased by 1, 2 or 4 depending upon the data bit width setting.
Page 511: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Map The following table shows the PDMA registers and reset values. Table 64. PDMA Register Map Register Offset Description Reset Value PDMA Channel 0 Registers PDMACH0CR 0x000 PDMA Channel 0 Control Register...
Page 512: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Descriptions PDMA Channel n Control Register – PDMACHnCR (n = 0 ~ 5) This register is used to specify the PDMA channel n data transfer configuration. Offset: 0x000 (0), 0x018 (1), 0x030 (2), 0x048 (3), 0x060 (4), 0x078 (5)
Page 513 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions SRCAMODn Channel n Source Address Mode selection 0: Linear address mode 1: Circular address mode In the linear address mode, the current source address value can be increased or decreased, determined by the SRCAINCn bit value during a complete transfer.
Page 514: Pdma Channel N Source Address Register - Pdmachnsadr (N = 0 ~ 5)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions CHnEN Channel n Enable control 0: Disable the PDMA channel n 1: Enable the PDMA channel n Setting this bit will enable a software or hardware transfer request on the PDMA channel n.
Page 515: Pdma Channel N Destination Address Register - Pdmachndadr (N = 0 ~ 5)
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 PDMA Channel n Destination Address Register – PDMACHnDADR (n = 0 ~ 5) This register specifies the destination address of the PDMA channel n. Offset: 0x008 (0), 0x020 (1), 0x038 (2), 0x050 (3), 0x068 (4), 0x080 (5)
Page 516: Pdma Channel N Transfer Size Register - Pdmachntsr (N = 0 ~ 5)
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 PDMA Channel n Transfer Size Register – PDMACHnTSR (n = 0 ~ 5) This register is used to specify the block transaction count and block transaction length. Offset: 0x010 (0), 0x028 (1), 0x040 (2), 0x058 (3), 0x070 (4), 0x088 (5)
Page 517: Pdma Channel N Current Transfer Size Register - Pdmachnctsr (N = 0 ~ 5)
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 PDMA Channel n Current Transfer Size Register – PDMACHnCTSR (n = 0 ~ 5) This register is used to indicate the current block transaction count. Offset: 0x014 (0), 0x02C (1), 0x044 (2), 0x05C (3), 0x074 (4), 0x08C (5)
Page 518: Pdma Interrupt Status Register - Pdmaisr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 PDMA Interrupt Status Register – PDMAISR This register is used to indicate the corresponding interrupt status of the PDMA channel 0 ~ 5. Offset: 0x120 Reset value: 0x0000_0000 Reserved TEISTA5 TCISTA5 HTISTA5...
Page 519: Pdma Interrupt Status Clear Register - Pdmaiscr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [25], [20], GEISTAn Channel n Global Transfer Interrupt Status (n = 0 ~ 5) [15], [10], 0: No TE, TC, HT or BE event occurs 1: TE, TC, HT, or BE event occurs [5], [0] This bit is set by hardware and is cleared by writing a “1”...
Page 520: Pdma Interrupt Enable Register - Pdmaier
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [26], [21], BEICLRn Channel n Block Transaction End Interrupt Status Clear (n = 0 ~ 5) [16], [11], 0: No Operation 1: Clear the corresponding BEISTAn bit in the PDMAISR register [6], [1] Writing a “1”...
Page 521 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [26], [21], BEIEn Channel n Block Transaction End Interrupt Enable control (n = 0 ~ 5) [16], [11], 0: Block Transaction End interrupt is disabled 1: Block Transaction End interrupt is enabled [6], [1] This bit is set and cleared by software.
Page 522: Divider (Div)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Divider (DIV) Introduction In order to enhance MCU performance, a divider is implemented within the device. Features Signed/unsigned 32-bit divider ▆ Operation in 8 clock cycles, Load in 1 clock cycle ▆...
Page 523: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Map The following table shows the DIV registers and reset values. Table 65. DIV Register Map Register Offset Description Reset Value 0x000 Divider Control Register 0x0000_0008 0x004 Dividend Data Register 0x0000_0000...
Page 524: Dividend Data Register - Ddr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Dividend Data Register – DDR The register contains the dividend of the divider. Offset: 0x004 Reset value: 0x0000_0000 Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW...
Page 525: Quotient Data Register - Qtr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Quotient Data Register – QTR The register contains the quotient of the divider calculation result. Offset: 0x00C Reset value: 0x0000_0000 Type/Reset 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO...
Page 526: Cyclic Redundancy Check (Crc)
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Cyclic Redundancy Check (CRC) Introduction The CRC (Cyclic Redundancy Check) calculation unit is an error detection technique test algorithm and is used to verify data transmission or storage data correctness. A CRC calculation takes a data stream or a block of data as input and generates a 16-bit or 32-bit output remainder.
Page 527: Functional Descriptions
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Functional Descriptions This unit only enables the calculation in the CRC16, CCITT CRC16 and IEEE-802.3 CRC32 polynomials. In this unit, the generator polynomial is fixed to the numeric values for those modes; therefore, the CRC value based on other generator polynomials cannot be calculated.
Page 528: Crc With Pdma
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 CRC with PDMA A PDMA channel with software trigger may be used to transfer data into the CRC unit. If a huge block data needs to be calculated, the recommended PDMA model is to use the PDMA to transfer all available words of data and use software writes to transfer the other remaining bytes.
Page 529: Crc Seed Register - Crcsd
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions SUMBIRV Bit Reverse operation on Checksum Output 0: Disable 1: Enable DATCMPL 1’s Complement operation on Data 0: Disable 1: Enable DATBYRV Byte Reverse operation on Data 0: Disable...
Page 530: Crc Checksum Register - Crccsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 CRC Checksum Register – CRCCSR This register contains the CRC checksum output. Offset: 0x008 Reset value: 0x0000_0000 CHKSUM Type/Reset 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO...
Page 531: Led Controller (Ledc)
LED Controller (LEDC) Introduction The LED controller is used to drive 8-segment digital displays. For the HT32F54231/HT32F54241 devices, the LED controller can drive up to eight 8-segment digital displays. For the HT32F54243/ HT32F54253 devices, the LED controller can drive up to twelve 8-segment digital displays. Users have the flexibility to configure the pin position and number of the COMs according to the digital displays in their application.
Page 532: Features
▆ Functional Description The position of each pixel point is represented by SEGx and COMy. The HT32F54231/HT32F54241 devices can drive up to eight 8-segment digital displays, x = 0 ~ 7, y = 0 ~ 7. The HT32F54243/ HT32F54253 devices can drive up to twelve 8-segment digital displays, x = 0 ~ 7, y = 0 ~ 11. The number of COMs to be enabled is N.
Page 533: Figure 190. Common Cathode 8-Segment Digital Display Connection
® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Each digital display scanning cycle can be subdivided into a dead time duty and a COM duty. The LED will not be illuminated during the dead time. The dead time clock number is selected by the DEADNUM[5:0] bit field.
Page 534: Figure 191. Common Cathode 8-Segment Digital Display Timing
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 1 Frame 1/N frame = 64 clocks (DTYNUM = 3), N = 4 CK_LED Scanning Frequency SEGx SEGxPOL = 0 C0Sx C5Sx C7Sx (x = 0, 1, …, 7) COM Duty = 59 clocks...
Page 535: Figure 193. Common Anode 8-Segment Digital Display+ Npn Bjt Timing
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 1 Frame 1/N frame = 64 clocks (DTYNUM = 3), N = 4 CK_LED Scanning Frequency SEGx ~C0Sx ~C5Sx ~C7Sx SEGxPOL = 1 (x = 0, 1, …, 7) COM Duty = 59 clocks...
Page 536: Figure 195. Common Cathode 8-Segment Digital Display + Npn Transistor Timing
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 1 Frame 1/N frame = 64 clocks (DTYNUM = 3), N = 4 CK_LED Scanning Frequency SEGx SEGxPOL = 0 C0Sx C5Sx C7Sx (x = 0, 1, …, 7) COM Duty = 59 clocks...
Page 537: Ledc Frame Interrupt
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 1 Frame 1/N frame = 64 clocks (DTYNUM = 3) CK_LED Scanning Frequency SEGx ~C0Sx ~C5Sx ~C7Sx SEGxPOL = 1 (x = 0, 1, …, 7) Deadtime Duty COM Duty = 59 clocks...
Page 538: Ledc D Ata Update Method
CK_LED Where N is the number of COMs selected. For the HT32F54231/HT32F54241, the maximum value of N is 8. For the HT32F54243/HT32F54253, the maximum value of N is 12. The duty clock number can be configured as 8, 16, 32 or 64 by the DTYNUM[1:0] bit field in the LEDDTCR register.
Page 539: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Map The following table shows the LEDC registers and their reset values. Table 68. LEDC Register Map Register Offset Description Reset Value LEDCR 0x000 LED Control Register 0x0000_0000 LEDCER 0x004 LED COM Enable Register...
Page 540: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Descriptions LED Control Register – LEDCR This register is used to control the LEDC clock source, prescaler, duty clock number and LEDC function enable. Offset: 0x000 Reset value: 0x0000_0000 Reserved LEDPS...
Page 541: Led Com Enable Register - Ledcer
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions LEDEN LEDC Enable Bit 0: Disable 1: Enable The LEDC state machine will be enabled when this bit is set to 1. If this bit is set to 0, the state machine will continue to output until the current frame operation is completed, then the state of the state machine will be cleared and finally the LEDEN bit will be cleared to zero by the hardware.
Page 542: Led Polarity Control Register - Ledpcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 LED Polarity Control Register – LEDPCR This register controls the polarity of the COMy and SEGx. (x = 0 ~ 7, y = 0 ~ 11) Offset: 0x008 Reset value: 0x0000_0000 Reserved...
Page 543: Led Interrupt Enable Register - Ledier
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 LED Interrupt Enable Register – LEDIER This register is used to control the frame interrupt enable. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved FIEN Type/Reset Bits Field...
Page 544: Led Status Register - Ledsr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 LED Status Register – LEDSR This register specifies the frame interrupt flag. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Bits Field Descriptions Frame interrupt flag 0: No frame interrupt occurs 1: Frame interrupt occurs Set by hardware and reset by software writing 1.
Page 545: Led Dead Time Control Register - Leddtcr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 LED Dead Time Control Register – LEDDTCR This register specifies the dead time duty. Offset: 0x014 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved DEADNUM Type/Reset 0 RW 0 RW...
Page 546: Led Data Register N - Leddrn (N = 0 ~ 11)
Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 LED Data Register n – LEDDRn (n = 0 ~ 11) This register specifies that the LCD pixel points that are represented by SEGx and COMy are to be illuminated. (x = 0 ~ 7, y = n = 0 ~ 11)
Page 547: Touch Key
Keys are organised into several groups, with each group known as a module Mn. For the HT32F54231/HT32F54241 devices contain touch key up to 24, having a module number M0 to M5. For the HT32F54243/ HT32F54253 contain touch key up to 28.
Page 548: Manual Mode
® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Manual Mode In the manual scan mode, the reference oscillator capacitor value should be properly configured before the scan operation begins and the touch key module 16-bit C/F counter value should be read by application program after the scan operation finishes. In the Manual mode, at the end of the fixed reference clock time interval a Touch key interrupt signal will be generated.
Page 549: Auto Scan Mode
® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 When the time slot counter in all the touch key modules or in the touch key module 0 overflows, an actual touch key TKRCOV interrupt will take place. The touch keys mentioned here are the keys which are enabled.
Page 550: Touch Key Interrupts
® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 mode. When any key C/F counter value is less than the lower threshold if MnKmTHS = 0, or larger than the upper threshold if MnKmTHS = 1, this indicates that the touch key state changes, then the MnKmTHF flag will be set high by the hardware, and an interrupt signal will be generated.
Page 551: Touch Key Scan Operation Flowchart
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Touch Key MnK0THF MnK0THS Interrupt Controller MnK1THF MnK1THS TKTHINT MnK2THF TKTHE MnK2THS TKTHE MnK3THF MnK3THS TKINT TKRCOV TKRCOVE TKRCOVE Figure 200. Touch Key Interrupts Touch Key Scan Operation Flowchart Start Write Ref. OSC Capacitor...
Page 552 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Start Write Ref. OSC internal Capacitor value to the TKMnRO_Km bit field Touch Key Auto Scan Operation Start Set Start bit TKST 0 → 1  Busy flag TKBUSY = 1 Load Ref. OSC internal...
Page 553 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Start Write Ref. OSC internal Capacitor value to the TKMn16D_Km bit filed Touch Key Auto Scan Operation Start Set Start bit TKST 0 → 1 → Busy flag TKBUSY = 1 MCU Hold (Optional) Load Ref.
Page 554: Register Map
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Map The following table shows the touch key registers and reset values. Table 69. Touch key module Register Map Register Offset Description Reset Value Touch Key Global Registers TKCR 0x000 Touch Key Control Register...
Page 555: Register Descriptions
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Register Descriptions Touch Key Control Register – TKCR This register specifies the corresponding Touch Key function enable control. Offset: 0x000 Reset value: 0x0000_091A TKCLKSEL Reserved Type/Reset Reserved Type/Reset RODLY ASMTO ASMP Type/Reset...
Page 556 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [9:8] ASMP Periodic Auto Scan Mode Period, T , Selection 00: T ASMTO 01: T / 4 (default) ASMTO 10: T ASMTO 11: T / 16 ASMTO These bits are used to determine the touch key scan period and only available when the touch key function is configured to operate in the periodic auto scan mode.
Page 557 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [2:1] TKMOD Touch Key Scan Mode Selection 00: Auto scan mode 01: Manual mode (default) 10: Periodic auto scan mode 11: Periodic auto scan mode In the manual scan mode, the reference oscillator capacitor value should be properly configured before the scan operation begins and the touch key module 16-bit C/F counter value should be read by application program after the scan operation finishes.
Page 558: Touch Key Counter Register - Tkcntr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Touch Key Counter Register – TKCNTR This register is used to store the touch key function 16-bit counter value. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset TK16D Type/Reset 0 RO...
Page 559: Touch Key Time Slot Counter Reload Register - Tktscrr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Touch Key Time Slot Counter Reload Register – TKTSCRR This register specifies the 8-bit time slot counter reload value. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset TKTMR Type/Reset...
Page 560: Touch Key Interrupt Enable Register - Tkier
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Touch Key Interrupt Enable Register – TKIER This register contains the corresponding Touch Key interrupt enable control bits. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved TKRCOVWUEN TKTHWUEN TKRCOVE...
Page 561: Touch Key Status Register - Tksr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Touch Key Status Register – TKSR This register contains the relevant Touch Key status. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved PCKRDY TKBUSY TKCFOV TK16OV TKRCOVF TKTHF...
Page 562 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions TKRCOVF 8-bit Time Slot Counter Overflow Flag 0: No overflow occurs 1: Overflow occurs Set by hardware when 8-bit Time slot overflows. Reset by software writing 1. In the manual scan mode, if all module time slot counters are overflow, the TKRCOV bit and the Touch Key TKRCOV Interrupt request flag, TKRCOVF, will be set and all modules’...
Page 563: Touch Key Module N Control Register - Tkmncr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Touch Key Module n Control Register – TKMnCR This register specifies the corresponding Module n function enable bit. Offset: 0x100 × (n + 1) + 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved...
Page 564 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions MnKOEN Touch Key Module n Key Oscillator Control 0: Disable 1: Enable In the manual scan mode, this bit is used to enable/disable the module n key oscillator. When the module n key oscillator is enabled, if the relevant key is enabled to be scanned and will be disabled automatically when the TKBUSY bit is changed from high to low.
Page 565: Tkmn Key Configuration Register - Tkmnkcfgr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 TKMn Key Configuration Register – TKMnKCFGR This register specifies the corresponding Key 0 to Key 3 function enable control. Offset: 0x100 × (n + 1)+0x004 Reset value: 0x00E4_0000 Reserved Type/Reset MnSK3 MnSK2...
Page 566 32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Bits Field Descriptions [17:16] MnSK0 Touch Key Module n Time Slot 0 Key Scan Selection (TKMOD = 01) 00: Key 0 01: Key 1 10: Key 2 11: Key 3 These bits are used to select the desired scan key in time slot 0 in the auto scan mode or the periodic auto scan mode or used as the multiplexer for scan key selection in the manual mode.
Page 567: Touch Key Module N Status Register - Tkmnsr (N = 0 ~ 3)
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Touch Key Module n Status Register – TKMnSR (n = 0 ~ 3) This register contains the relevant Key 0 to Key 3 status. Offset: 0x100 × (n + 1) + 0x008...
Page 568: Touch Key Module N Reference Oscillator Capacitor Register - Tkmnrocpr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Touch Key Module n Reference Oscillator Capacitor Register – TKMnROCPR This register is used to store the touch key module n reference oscillator capacitor value. Offset: 0x100 × (n + 1) + 0x00C...
Page 569: Touch Key Module N Key 3 Capacitor Register - Tkmnk3Cpr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Touch Key Module n Key 3 Capacitor Register – TKMnK3CPR This register specifies the module n Key 3 reference oscillator capacitor value. Offset: 0x100 × (n + 1) + 0x010 Reset value: 0x0000_0000...
Page 570: Touch Key Module N Key 1 Capacitor Register - Tkmnk1Cpr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Touch Key Module n Key 1 Capacitor Register – TKMnK1CPR This register specifies the module n Key 1 reference oscillator capacitor value. Offset: 0x100 × (n + 1) + 0x018 Reset value: 0x0000_0000...
Page 571: Touch Key Module N C/F Counter Register - Tkmncfcntr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Touch Key Module n C/F Counter Register – TKMnCFCNTR This register contains the touch key module n 16-bit C/F counter value. Offset: 0x100 × (n + 1) + 0x020 Reset value: 0x0000_0000...
Page 572: Touch Key Module N Key 3 Counter Register - Tkmnk3Cntr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Touch Key Module n Key 3 Counter Register – TKMnK3CNTR This register contains the touch key module n Key 3 16-bit C/F counter value. Offset: 0x100 × (n + 1) + 0x024...
Page 573: Touch Key Module N Key 1 Counter Register - Tkmnk1Cntr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Touch Key Module n Key 1 Counter Register – TKMnK1CNTR This register contains the touch key module n Key 1 16-bit C/F counter value. Offset: 0x100 × (n + 1) + 0x02C...
Page 574: Touch Key Module N Key 3 Threshold Register - Tkmnk3Thr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Touch Key Module n Key 3 Threshold Register – TKMnK3THR This register specifies the touch key module n Key 3 threshold value. Offset: 0x100 × (n + 1) + 0x034 Reset value: 0x0000_0000...
Page 575: Touch Key Module N Key 1 Threshold Register - Tkmnk1Thr
32-Bit Arm ® Cortex ® -M0+ MCU HT32F54231/HT32F54241/HT32F54243/HT32F54253 Touch Key Module n Key 1 Threshold Register – TKMnK1THR This register specifies the touch key module n Key 1 threshold value. Offset: 0x100 × (n + 1) + 0x03C Reset value: 0x0000_0000...
Page 576 Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.

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