Function Descriptions; Adc Clock Setup; Channel Selection; Conversion Mode - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241

Function Descriptions

ADC Clock Setup

The ADC clock, CK_ADC is provided by the Clock Controller which is synchronous and divided
by with the AHB clock known as HCLK. Refer to the Clock Control Unit chapter for more details.
Notes that ADC peripheral needs keeping at least two ADC clock cycles to switch between power-
on and power off stage (ADEN bit = '0').

Channel Selection

The A/D converter supports 14 multiplexed channels and converts the conversion results into ADC
conversion data register. A conversion group can organize a sequence which can be implemented
arranged in a specific conversion sequence length from 1 to 8. For example, conversion can be
carried out with the following channel sequence: CH2, CH4, CH7, CH5, CH6, CH3, CH0 and CH1
one after another.
A group is composed of up to 8 conversions. The selected channels of the group conversion can be
specified in the ADCLST0 ~ ADCLST1 registers. The total conversion sequence length is setup
using the ADSEQL[2:0] bits in the ADCCR register.
Modifying the ADCCR or ADCLSTn register during a conversion process will reset the current
conversion, after which a new start pulse is required to restart a new conversion.

Conversion Mode

The A/D has three operating conversion modes. The conversion modes are One Shot Conversion
Mode, Continuous Conversion Mode and Discontinuous Conversion mode. Details are provided
later.
One Shot Conversion Mode
In one shot conversion mode, the ADC will perform conversion cycles on the channels specified in
the A/D conversion list registers ADCLSTn with a specific sequence when an A/D converter event
trigger occurs. When the A/D conversion mode field ADMODE [1:0] in the ADCCR register is set
to 0x0, the A/D converter will operate in the One Shot Conversion Mode. This mode can be started
by a software trigger, an external EXTI event or a Timer event determined by the Trigger Control
Register ADCTCR and the Trigger Source Register ADCTSR.
After Conversion
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The converted data will be stored in the 16-bit ADCDRy (y = 0 ~ 7) registers.
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The ADC regular single sample end of conversion event raw status flag, ADIRAWS, in the
ADCIRAW register will be set when the single sample conversion is finished.
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An interrupt will be generated after a single sample end of conversion if the ADIES bit in the
ADCIER register is enabled.
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An interrupt will be generated after a regular group cycle end of conversion if the ADIEC bit in
the ADCIER register is enabled.
Rev. 1.00 163 of 486 July 31, 2018