Channel 0 Output Configuration Register - Ch0Ocfr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Channel 0 Output Configuration Register – CH0OCFR
This register specifies the channel 0 output mode configuration.
Offset: 0x040
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Reserved
Type/Reset
Bits Field
[5] CH0IMAE
[4] CH0PRE
Rev. 1.00
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
CH0IMAE CH0PRE
RW 0 RW
Descriptions
Channel 0 Immediate Active Enable
0: No action
1: Single pulse Immediate Active Mode is enabled
The CH0OREF will be forced to the compare matched level immediately after
an available trigger event occurs irrespective of the result of the comparison
between the CNTR and the CH0CCR values.
The effective duration ends automatically at the next overflow or underflow
event.
Note: The CH0IMAE bit is available only if channel 0 is configured operate in PWM
mode 1 or PWM mode 2.
Channel 0 Capture/Compare Register (CH0CCR) Preload Enable
0: CH0CCR preload function is disabled
The CH0CCR register can be immediately assigned a new value when
the CH0PRE bit is cleared to 0 and the updated CH0CCR value is used
immediately.
1: CH0CCR preload function is enabled
The new CH0CCR value will not be transferred to its shadow register until an
update event 1 occurs.
345 of 486
27 26
Reserved
19 18
Reserved
11 10
3 2
Reserved CH0OM[2:0]
0 RW 0 RW
25 24
17 16
9 8
CH0OM[3]
RW 0
1 0
0 RW 0
July 31, 2018