Functional Descriptions; Power On Reset; System Reset; Ahb And Apb Unit Reset - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241

Functional Descriptions

Power On Reset

The Power on reset, POR, is generated by either an external reset or the internal reset generator.
Both types have an internal filter to prevent glitches from causing erroneous reset operations. By
referring to Figure 18, the POR15 active low signal will be de-asserted when the internal LDO
voltage regulator is ready to provide a 1.5 V power. In addition to the POR15 signal, the Power
Control Unit, PWRCU, will assert the BODF signal as a Power Down Reset, PDR, when the
BODEN bit in the LVDCSR register is set and the brown-out event occurs. For more details about
the PWRCU function, refer to the PWRCU chapter.
PORRESETn
SYSRESETn

Figure 18. Power On Reset Sequence

System Reset

A system reset is generated by a power on reset (PORRESETn), a Watchdog Timer reset (WDT_RSTn),
nRST pin or a software reset (SYSRESETREQ) event. For more information about SYSRESETREQ
event, refer to the related chapter in the Cortex

AHB and APB Unit Reset

The AHB and APB unit reset can be divided into hardware and software resets. A hardware
reset can be generated by either power on reset or system reset for all AHB and APB units.
Each functional IP connected to the AHB and APB buses can be reset individually through the
associated software reset bits in the RSTCU. For example, the application software can generate a
USART reset via the USRRST bit in the APBPRSTR0 register.
Rev. 1.00
V
DD
V
DD15
t
1
t
2
* This timing is dependent on the internal LDO regulator output capacitor value.
® -M0+ reference manual.
99 of 486
t = 25 μs *Typical.
1
t = 100 μs
2
t
t = 150 μs
3
3
July 31, 2018