Holtek HT32F50231 User Manual page 19

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Figure 121. Channel 3 Output with a Break Event Occurrence ............................................................ 317
Figure 122. Channel 0 ~2 Complementary Outputs with a Break Event Occurrence........................... 318
Figure 123. Channel 0 ~2 Only One Output Enabled when Break Event Occurs ................................ 319
Figure 124. Hardware Protection When Both CHxO and CHxNO are in Active Condition ................... 320
Figure 125. Update Event 1 Setup Diagram ......................................................................................... 322
Figure 126. CHxE, CHxNE and CHxOM Updated by Update Event 2 ................................................. 323
Figure 127. Update Event 2 Setup Diagram ......................................................................................... 323
Figure 128. Single Pulse Mode ............................................................................................................. 324
Figure 129. Immediate Active Mode Minimum Delay ........................................................................... 325
Figure 130. Asymmetric PWM Mode versus Center-aligned Counting Mode ....................................... 326
Figure 131. Pausing GPTM using the MCTM CH0OREF Signal .......................................................... 327
Figure 132. Triggering GPTM with MCTM Update Event 1 .................................................................. 328
Figure 133. Figure 41 Trigger MCTM and GPTM with the MCTM CH0 Input ....................................... 329
Figure 134. CH1XOR Input as Hall Sensor Interface ........................................................................... 330
Figure 135. RTC Block Diagram ........................................................................................................... 373
Figure 136. Watchdog Timer Block Diagram ....................................................................................... 382
Figure 137. Watchdog Timer Behavior ................................................................................................. 384
Figure 138. I 2 C Module Block Diagram ................................................................................................. 391
Figure 139. START and STOP Condition ............................................................................................. 393
Figure 140. Data Validity ....................................................................................................................... 393
Figure 141. 7-bit Addressing Mode ....................................................................................................... 394
Figure 142. 10-bit Addressing Write Transmit Mode ............................................................................ 395
Figure 143. 10-bits Addressing Read Receive Mode .......................................................................... 395
Figure 144. I 2 C Bus Acknowledge ........................................................................................................ 396
Figure 145. Clock Synchronization during Arbitration ........................................................................... 397
Figure 146. Two Master Arbitration Procedure ..................................................................................... 397
Figure 147. Master Transmitter Timing Diagram .................................................................................. 399
Figure 148. Master Receiver Timing Diagram ...................................................................................... 401
Figure 149. Slave Transmitter Timing Diagram .................................................................................... 402
Figure 150. Slave Receiver Timing Diagram ........................................................................................ 403
Figure 151. SCL Timing Diagram .......................................................................................................... 414
Figure 152. SPI Block Diagram ............................................................................................................ 420
Figure 153. SPI Single Byte Transfer Timing Diagram - CPOL = 0, CPHA = 0 .................................... 422
Figure 154. SPI Continuous Data Transfer Timing Diagram - CPOL = 0, CPHA = 0 ........................... 423
Figure 155. SPI Single Byte Transfer Timing Diagram - CPOL = 0, CPHA = 1 .................................... 423
Figure 156. SPI Continuous Transfer Timing Diagram - CPOL = 0, CPHA = 1 .................................... 424
Figure 157. SPI Single Byte Transfer Timing Diagram - CPOL = 1, CPHA = 0 .................................... 424
Figure 158. SPI Continuous Transfer Timing Diagram - CPOL = 1, CPHA = 0 .................................... 425
Figure 159. SPI Single Byte Transfer Timing Diagram - CPOL = 1, CPHA = 1 .................................... 425
Figure 160. SPI Continuous Transfer Timing Diagram - CPOL = 1, CPHA = 1 .................................... 425
Figure 161. SPI Multi-Master Slave Environment ................................................................................. 427
Rev. 1.00 19 of 486 July 31, 2018