Spi Control Register 1 - Spicr1 - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
SPI Control Register 1 – SPICR1
This register specifies the SPI parameters including the data length, the transfer format, the SEL active polarity /
mode, the LSB / MSB control and the master / slave mode.
Offset: 0x004
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Reserved
Type/Reset RW
7
Type/Reset
Bits Field
[14] MODE
[13] SELM
[12] FIRSTBIT
[11] SELAP
[10:8] FORMAT
Rev. 1.00
30 29 28
22 21 20
14 13 12
MODE SELM FIRSTBIT
0 RW 0 RW
6 5
Reserved
Descriptions
Master or Slave Mode
0: Slave mode
1: Master mode
Slave Select Mode
0: SEL signal is controlled by software – asserted or de-asserted by the SSELC bit
1: SEL signal is controlled by hardware – generated automatically by the SPI
hardware
Note that the SELM bit is available for master mode only – MODE = 1.
LSB or MSB Transmitted First
0: MSB is transmitted first
1: LSB is transmitted first
Slave Select Active Polarity
0: SEL signal is active low
1: SEL signal is active high
SPI Data Transfer Format
These three bits are used to determine the data transfer format of the SPI interface.
FORMAT [2:0]
001
010
110
101
Others
CPOL: Clock Polarity
0: SCK Idle state is low
1: SCK Idle state is high
CPHA: Clock Phase
0: Data is captured on the first SCK clock edge
1: Data is captured on the second SCK clock edge
431 of 486
27 26
Reserved
19 18
Reserved
11 10
SELAP
0 RW 0 RW
4 3 2
RW 0 RW
CPOL CPHA
0 0
0 1
1 0
1 1
Reserved
25 24
17 16
9 8
FORMAT
0 RW 0 RW 0
1 0
DFL
0 RW 0 RW 0
July 31, 2018