HOLTEK HT32F52243 Manuals

Manuals and User Guides for HOLTEK HT32F52243. We have 1 HOLTEK HT32F52243 manual available for free PDF download: User Manual

HOLTEK HT32F52243 User Manual (501 pages)

32-Bit Microcontroller with Arm Cortex-M0+ Core

Brand: HOLTEK | Category: Microcontrollers | Size: 5 MB

Table of Contents
2
1 Introduction

22
- Overview
  22
- Features
  23
- Device Information
  27
- Table 1. Features and Peripheral List
  27
- Block Diagram
  28
- Figure 1. Block Diagram
  28
2 Document Conventions

29
- Table 2. Document Conventions
  29
3 System Architecture

30
- Arm ® Cortex ® -M0+ Processor
  30
- Bus Architecture
  31
- Figure 2. Cortex ® -M0+ Block Diagram
  31
- Memory Organization
  32
  - Figure 3. Bus Architecture
    32
  - Figure 4. Memory Map
    33
  - Memory Map
    33
  - Table 3. Register Map
    34
  - AHB Peripherals
    35
  - APB Peripherals
    35
  - Embedded Flash Memory
    35
  - Embedded SRAM Memory
    35
4 Flash Memory Controller (FMC)

36
5 Power Control Unit (PWRCU)

61
6 Clock Control Unit (CKCU)

72
7 Reset Control Unit (RSTCU)

104
- Introduction
  104
- Figure 18. RSTCU Block Diagram
  104
- Functional Descriptions
  105
  - Power on Reset
    105
  - System Reset
    105
  - AHB and APB Unit Reset
    105
  - Figure 19. Power on Reset Sequence
    105
- Register Map
  106
- Table 19. RSTCU Register Map
  106
- Register Descriptions
  107
8 General Purpose I/O (GPIO)

112
9 Alternate Function Input/Output Control Unit (AFIO)

153
- Introduction
  153
- Figure 22. AFIO Block Diagram
  153
- Features
  154
- Functional Descriptions
  154
  - External Interrupt Pin Selection
    154
  - Figure 23. EXTI Channel Input Selection
    154
  - Alternate Function
    155
  - Lock Mechanism
    155
- Register Map
  155
- Table 22. AFIO Selection for Peripheral Map Example
  155
- Table 23. AFIO Register Map
  155
- Register Descriptions
  156
  - EXTI Source Selection Register 0 - ESSR0
    156
    
    EXTI Source Selection Register 1 - ESSR1
    157
    
    GPIO Port X Configuration Low Register - Gpxcfglr, X = A, B, C, D
    158
    
    GPIO Port X Configuration High Register - Gpxcfghr, X = A, B, C, D
    159
10 Nested Vectored Interrupt Controller (NVIC)

160
- Introduction
  160
- Table 24. Exception Types
  160
- Features
  161
- Function Descriptions
  162
  - Systick Calibration
    162
- Register Map
  162
- Table 25. NVIC Register Map
  162
11 External Interrupt / Event Controller (EXTI)

163
12 Analog to Digital Converter (ADC)

173
- Introduction
  173
- Figure 27. ADC Block Diagram
  173
- Features
  174
- Function Descriptions
  175
  - ADC Clock Setup
    175
  - Channel Selection
    175
  - Conversion Mode
    175
  - Figure 28. One Shot Conversion Mode
    176
  - Figure 29. Continuous Conversion Mode
    176
  - Start Conversion on External Event
    178
  - Figure 30. Discontinuous Conversion Mode
    178
  - Sampling Time Setting
    179
  - Data Format
    179
  - Analog Watchdog
    179
  - Table 27. Data Format in ADCDR [15:0]
    179
  - Interrupts
    180
- Register Map
  181
- Table 28. A/D Converter Register Map
  181
- Register Descriptions
  182
13 General-Purpose Timer (GPTM)

195
14 Basic Function Timer (BFTM)

257
- Introduction
  257
- Features
  257
- Figure 65. BFTM Block Diagram
  257
- Functional Description
  258
  - Repetitive Mode
    258
  - Figure 66. BFTM - Repetitive Mode
    258
  - One Shot Mode
    259
  - Figure 67. BFTM - One Shot Mode
    259
  - Figure 68. BFTM - One Shot Mode Counter Updating
    259
  - Trigger ADC Start
    260
- Register Map
  260
- Table 33. BFTM Register Map
  260
- Register Descriptions
  261
15 Motor Control Timer (MCTM)

264
16 Single-Channel Timer (SCTM)

342
- Introduction
  342
- Features
  342
- Figure 112. SCTM Block Diagram
  342
- Functional Descriptions
  343
  - Counter Mode
    343
  - Clock Controller
    343
  - Figure 113. Up-Counting Example
    343
  - Trigger Controller
    344
  - Figure 114. SCTM Clock Selection Source
    344
  - Figure 115. Trigger Control Block
    345
  - Slave Controller
    346
  - Figure 116. Slave Controller Diagram
    346
  - Figure 117. SCTM in Restart Mode
    346
  - Figure 118. SCTM in Pause Mode
    347
  - Figure 119. SCTM in Trigger Mode
    347
  - Channel Controller
    348
  - Figure 120. Capture/Compare Block Diagram
    348
  - Input Stage
    349
  - Figure 121. Input Capture Mode
    349
  - Figure 122. Channel Input Stages
    349
  - Output Stage
    350
  - Figure 123. TI Digital Filter Diagram with N = 2
    350
  - Figure 124. Output Stage Block Diagram
    350
  - Table 39. Compare Match Output Setup
    351
  - Figure 125. Toggle Mode Channel Output Reference Signal (CHPRE = 0)
    351
  - Figure 126. Toggle Mode Channel Output Reference Signal (CHPRE = 1)
    352
  - Figure 127. PWM Mode Channel Output Reference Signal
    352
  - Update Management
    353
  - Figure 128. Update Event Setting Diagram
    353
- Register Map
  354
- Table 40. SCTM Register Map
  354
- Register Descriptions
  355
17 Real Time Clock (RTC)

370
- Introduction
  370
- Features
  370
- Figure 129. RTC Block Diagram
  370
- Functional Descriptions
  371
- Register Map
  374
- Register Descriptions
  374
  - RTC Counter Register - RTCCNT
    374
  - Table 43. RTC Register Map
    374
  - RTC Compare Register - RTCCMP
    375
  - RTC Control Register - RTCCR
    376
  - RTC Status Register - RTCSR
    378
  - RTC Interrupt and Wakeup Enable Register - RTCIWEN
    379
18 Watchdog Timer (WDT)

380
- Introduction
  380
- Features
  380
- Figure 130. Watchdog Timer Block Diagram
  380
- Functional Description
  381
- Register Map
  382
- Table 44. Watchdog Timer Register Map
  382
- Figure 131. Watchdog Timer Behavior
  382
- Register Descriptions
  383
19 Inter-Integrated Circuit - I C

389
- Introduction
  389
- Figure 132. I C Module Block Diagram
  389
- Features
  390
- Functional Descriptions
  390
  - Two Wire Serial Interface
    390
  - START and STOP Conditions
    390
  - Data Validity
    391
  - Figure 133. START and STOP Condition
    391
  - Figure 134. Data Validity
    391
  - Addressing Format
    392
  - Figure 135. 7-Bit Addressing Mode
    392
  - Data Transfer and Acknowledge
    393
  - Figure 136. 10-Bit Addressing Write Transmit Mode
    393
  - Figure 137. 10-Bits Addressing Read Receive Mode
    393
  - Clock Synchronization
    394
  - Figure 138. I 2 C Bus Acknowledge
    394
  - Figure 139. Clock Synchronization During Arbitration
    394
  - Arbitration
    395
  - General Call Address
    395
  - Bus Error
    395
  - Figure 140. Two Master Arbitration Procedure
    395
  - Address Mask Enable
    396
  - Address Snoop
    396
  - Operation Mode
    396
  - Master Transmitter Mode
    396
  - Master Receiver Mode
    397
  - Figure 141. Master Transmitter Timing Diagram
    397
  - Figure 142. Master Receiver Timing Diagram
    398
  - Slave Transmitter Mode
    399
  - Figure 143. Slave Transmitter Timing Diagram
    399
  - Slave Receiver Mode
    400
  - Figure 144. Slave Receiver Timing Diagram
    400
  - Conditions of Holding SCL Line
    401
  - Table 45. Conditions of Holding SCL Line
    401
  - I 2 C Timeout Function
    402
  - PDMA Interface
    402
- Register Map
  403
- Table 46. I 2 C Register Map
  403
- Register Descriptions
  404
  - I 2 C Control Register - I2CCR
    404
  - I 2 C Interrupt Enable Register - I2CIER
    406
    
    I 2 C Address Register - I2CADDR
    407
    
    I 2 C Status Register - I2CSR
    408
    
    I 2 C SCL High Period Generation Register - I2CSHPGR
    411
    
    I 2 C SCL Low Period Generation Register - I2CSLPGR
    412
    
    Table 47. I 2 C Clock Setting Example
    412
    
    Figure 145. SCL Timing Diagram
    412
    
    C Data Register - I2CDR
    413
    
    I 2 C Target Register - I2CTAR
    414
    
    I 2 C Address Mask Register - I2CADDMR
    415
    
    I 2 C Address Snoop Register - I2CADDSR
    416
    
    I 2 C Timeout Register - I2CTOUT
    417
20 Serial Peripheral Interface (SPI)

418
21 Universal Synchronous Asynchronous Receiver Transmitter (USART)

439
- Introduction
  439
  - Figure 156. USART Block Diagram
    439
  - Features
    440
- Function Descriptions
  441
- Register Map
  452
- Table 54. USART Register Map
  452
- Register Descriptions
  453
22 Universal Asynchronous Receiver Transmitter (UART)

466
- Introduction
  466
  - Figure 167. UART Block Diagram
    466
  - Features
    467
- Function Descriptions
  467
- Register Map
  470
- Register Descriptions
  470
  - UART Data Register - URDR
    470
  - Table 57. UART Register Map
    470
  - UART Control Register - URCR
    471
  - UART Interrupt Enable Register - URIER
    473
  - UART Status & Interrupt Flag Register - URSIFR
    474
  - UART Divider Latch Register - URDLR
    475
  - UART Test Register - URTSTR
    476
23 Peripheral Direct Memory Access (PDMA)

477
- Introduction
  477
- Features
  477
- Figure 170. PDMA Block Diagram
  477
- Functional Description
  478
  - AHB Master
    478
  - PDMA Channel
    478
  - PDMA Request Mapping
    478
  - Figure 171. PDMA Request Mapping Architecture
    478
  - Channel Transfer
    479
  - Channel Priority
    479
  - Table 58. PDMA Channel Assignments
    479
  - Transfer Request
    480
  - Address Mode
    480
  - Table 59. PDMA Address Modes
    480
  - Figure 172. PDMA Channel Arbitration and Scheduling Example
    480
  - Auto-Reload
    481
  - Transfer Interrupt
    481
- Register Map
  482
- Table 60. PDMA Register Map
  482
- Register Descriptions
  483
24 Cyclic Redundancy Check (CRC)

491
- Introduction
  491
- Features
  491
- Figure 173. CRC Block Diagram
  491
- Function Descriptions
  492
  - CRC Computation
    492
  - Byte and Bit Reversal for CRC Computation
    492
  - Figure 174. CRC Data Bit and Byte Reversal Example
    492
  - CRC with PDMA
    493
- Register Map
  493
- Table 61. CRC Register Map
  493
- Register Descriptions
  494
  - CRC Control Register - CRCCR
    494
  - CRC Seed Register - CRCSDR
    495
  - CRC Checksum Register - CRCCSR
    495
  - CRC Data Register - CRCDR
    496
25 Divider (DIV)

497
- Introduction
  497
- Features
  497
- Functional Descriptions
  497
- Figure 175. Divider Functional Diagram
  497
- Register Map
  498
- Register Descriptions
  498
  - Divider Control Register - CR
    498
  - Table 62. DIV Register Map
    498
  - Dividend Data Register - DDR
    499
  - Divisor Data Register - DSR
    499
  - Quotient Data Register - QTR
    500
  - Remainder Data Register - RMR
    500

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Microcontrollers

Storage Computer Hardware Control Unit Controller

More HOLTEK Manuals

HOLTEK HT32F52243 Manuals

HOLTEK HT32F52243 User Manual (501 pages)

Table of Contents

1 Introduction

2 Document Conventions

3 System Architecture

4 Flash Memory Controller (FMC)

5 Power Control Unit (PWRCU)

6 Clock Control Unit (CKCU)

7 Reset Control Unit (RSTCU)

8 General Purpose I/O (GPIO)

9 Alternate Function Input/Output Control Unit (AFIO)

10 Nested Vectored Interrupt Controller (NVIC)

11 External Interrupt / Event Controller (EXTI)

12 Analog to Digital Converter (ADC)

13 General-Purpose Timer (GPTM)

14 Basic Function Timer (BFTM)

15 Motor Control Timer (MCTM)

16 Single-Channel Timer (SCTM)

17 Real Time Clock (RTC)

18 Watchdog Timer (WDT)

19 Inter-Integrated Circuit - I C

20 Serial Peripheral Interface (SPI)

21 Universal Synchronous Asynchronous Receiver Transmitter (USART)

22 Universal Asynchronous Receiver Transmitter (UART)

23 Peripheral Direct Memory Access (PDMA)

24 Cyclic Redundancy Check (CRC)

25 Divider (DIV)

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