32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F50231/HT32F50241
Starting two timers synchronously with the master enable MTO signal trigger
▄
Configure PWM0 to operate in the master mode to send its enable signal as a trigger output
(MMSEL = 0x1).
▄
Enable the PWM0 master timer synchronization function by setting the TSE bit in the MDCFR
register to 1 to synchronize the slave timer.
▄
Configure PWM1 to receive its input trigger source from the PWM0 trigger output (TRSEL = 0x9).
▄
Configure PWM1 to be in the slave trigger mode (SMSEL = 0x6).
▄
Set "1" to the PWM1 TME bit.
▄
Start PWM0 by writing '1' to the TME bit.
Master PWM0
f
=f
DTS
PWM0 (TME bit)
PWM0 CK_PSC
PWM0 CNTR
Slave PWM1
PWM1 (TME bit)
PWM1 (TEVIF)
PWM1 CK_PSC
PWM1 CNTR
Figure 88. Trigger PWM0 and PWM1 with the PWM0 Timer Enable Signal
Trigger Peripherals Start
To interconnect to the peripherals, such as ADC, Timer and so on, the PWM could output the MTO
signal or the channel compare match output signal CHxOREF (x = 0 ~ 3) to be used as peripherals
input trigger signal, depending on the MCU specification.
Rev. 1.00
CLKIN
34
Write UEVG bit
11
265 of 486
TSE=1
Delay
0
1
2
ITI
0
1
2
Write UEVG bit
3
4
5
3
4
5
July 31, 2018
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