Timer Control Register - Ctr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Timer Control Register – CTR
This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE) and Capture/compare control bit.
Offset: 0x010
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[9] COMUS
[8] COMPRE
[1] CRBE
[0] TME
Rev. 1.00
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
Reserved
Descriptions
Capture/Compare Control Update Selection
0: Updated by setting the UEV2G bit only
1: Updated by setting the UEV2G bit or when a STI signal rising edge occurs
This bit is only available when the capture/compare preload function is enabled by
setting the COMPRE bit to 1.
Capture/Compare Preloaded Enable Control
0: CHxE, CHxNE and CHxOM bits are not preloaded
1: CHxE, CHxNE and CHxOM bits are preloaded
If this bit is set to 1, the corresponding capture/compare control bits including the
CHxE, CHxNE and CHxOM bits will be updated when the update event 2 occurs.
Counter Reload register Buffer Enable
0: Counter reload register can be updated immediately
1: Counter reload register can not be updated until the update event occurs
Timer Enable bit
0: MCTM off
1: MCTM on – MCTM functions normally
When the TME bit is cleared to 0, the counter is stopped and the MCTM consumes
no power in any operational mode except for the single pulse mode and the slave
trigger mode. In these two modes the TME bit can automatically be set to 1 by
hardware which permits all the MCTM registers to function normally.
338 of 486
27 26
Reserved
19 18
Reserved
11 10
COMUS
RW
3 2
CRBE
RW
25 24
17 16
9 8
COMPRE
0 RW 0
1 0
TME
0 RW 0
July 31, 2018