Baud Rate Generation; Figure 163. Usart Serial Data Format; Figure 164. Usart Clock Ck_Usart And Data Frame Timing - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Start Bit Bit0
Start Bit Bit0
Start Bit Bit0
Start Bit Bit0
Start Bit Bit0

Figure 163. USART Serial Data Format

Baud Rate Generation

The baud rate for the USART receiver and transmitter are both set with the same values. The baud
rate divisor, BRD, has the following relationship with the USART clock which is known as CK_
USART.
Where CK_USART clock is the APB clock connected to the USART while the BRD range is from
16 to 65535 for asynchronous mode and 8 to 65535 for synchronous mode.
CK_USART
Reference
Divisor Clock

Figure 164. USART Clock CK_USART and Data Frame Timing

Rev. 1.00
7-Bit Data Format
(WLS[1:0]=b00, PBE=0)
Bit1 Bit2 Bit3 Bit4
8-Bit Data Format
(WLS[1:0]=b01, PBE=0)
Bit1 Bit2 Bit3 Bit4
(WLS[1:0]=b00, PBE=1)
Bit1 Bit2 Bit3 Bit4
9-Bit Data Format
(WLS[1:0]=b10, PBE=0)
Bit1 Bit2 Bit3 Bit4
(WLS[1:0]=b01, PBE=1)
Bit1 Bit2 Bit3 Bit4
Baud Rate Clock = CK_USART / BRD
BRD =18
Start Bit Bit0 Bit1 Bit2
442 of 486
Next Start
Bit5 Bit6
Stop Bit
Bit
Next Start
Bit5 Bit6 Bit7 Stop Bit
Next Start
Bit5 Bit6 Parity Bit Stop Bit
Bit5 Bit6 Bit7 Bit8
Bit5 Bit6 Bit7 Parity Bit
Parity Bit
Bit3 Bit4 Bitn
n = 6 ~ 8
Bit
Bit
Next Start
Stop Bit
Bit
Next Start
Stop Bit
Bit
Next Start
Stop Bit
Bit
July 31, 2018