Uart Control Register - Urcr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
UART Control Register – URCR
The register specifies the serial parameters such as data length, parity and stop bit for the UART.
Offset: 0x004
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Reserved
Type/Reset RW
7
Reserved
Type/Reset
Bits Field
[14] BCB
[13] SPE
[12] EPE
[11] PBE
[10] NSB
[9:8] WLS
Rev. 1.00
30 29 28
22 21 20
14 13 12
BCB SPE EPE
0 RW 0 RW
6 5 4
URRXEN URTXEN
RW 0 RW
Descriptions
Break Control Bit
When this bit is set to 1, the serial data output on the UART TX pin will be forced to
the Spacing State (logic 0). This bit acts only on the UART TX output pin and has no
effect on the transmitter logic.
Stick Parity Enable
0: Disable stick parity
1: Stick Parity bit is transmitted
This bit is only available when the PBE bit is set to 1. If both the PBE and SPE bits
are set to 1 and the EPE bit is cleared to 0, the transmitted parity bit will be stuck to
1. However, when the PBE and SPE bits are set to 1 and also the EPE bit is set to
1, the transmitted parity bit will be stuck to 0.
Even Parity Enable
0: Odd number of logic 1's are transmitted or checked in the data word and parity bits
1: Even number of logic 1's are transmitted or checked in the data word and
parity bits
This bit is only available when PBE is set to 1.
Parity Bit Enable
0: Parity bit is not generated (transmitted data) and checked (receive data) during
transfer
1: Parity bit is generated and checked during transfer
Note: When the WLS field is set to "10" to select the 9-bit data format, writing to the
PBE bit has no effect.
Number of "STOP bit"
0: One "STOP bit" is generated in the transmitted data
1: Two "STOP bit" is generated when 8- and 9-bit word length is selected
Word Length Select
00: 7 bits
01: 8 bits
10: 9 bits
11: Reserved
470 of 486
27 26
Reserved
19 18
Reserved
11 10
PBE NSB
0 RW 0 RW 0 RW
3 2
Reserved TRSM
0 RW 0
25 24
17 16
9 8
WLS
0 RW 0
1 0
Reserved
July 31, 2018