Watchdog Timer (Wdt); Introduction; Features; Figure 136. Watchdog Timer Block Diagram - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
18

Watchdog Timer (WDT)

Introduction

The Watchdog timer is a hardware timing circuitry that can be used to detect a system lock-up
due to software trapped in a deadlock. The Watchdog timer can be operated in a reset mode. The
Watchdog timer will generate a reset when the counter counts down to a zero value. Therefore, the
software should reload the counter value before a Watchdog timer underflow occurs. In addition, a
reset is also generated if the software reloads the counter before it reaches a delta value. That means
that the Watchdog timer prevents a software deadlock that continuously triggers the Watchdog, the
reload must occur when the Watchdog timer value has a value within a limited window of 0 and
WDTD. The Watchdog timer counter can be stopped when the processor is in the debug or sleep
mode. The register write protection function can be enabled to prevent an unexpected change in the
Watchdog timer configuration.
RSKEY[15:0]
LSI RC
0
32 kHz
CK_WDT
LSE OSC
1
32.768 kHz
WDTEN
WDTSRC

Figure 136. Watchdog Timer Block Diagram

Features

▄
Clock source from either internal 32 kHz RC oscillator (LSI) or external 32,768 Hz oscillator (LSE)
▄
Can be independently setup to keep running or to stop when entering the Sleep mode or Deep-Sleep1
mode
▄
12-bit down-counter with 3-bit prescaler structure
▄
Provides reset to the system
▄
Limited reload window setup function for custom Watchdog timer reload times
▄
Watchdog Timer may be stopped when the processor is in the debug
▄
Reload lock key to prevent unexpected operation
▄
Configuration register write protection function for counter value, reset enable, delta value and
prescaler value
Rev. 1.00
WDTRS WDTV
Reload
Clear
Prescaler
12-bit Down
1 / 2 / 4 / 8
Counter
... / 128
WPSC[2:0]
WDTD
382 of 486
Underflow
WDTUF
WDTRSTEN
WDTERR
Read WDTSR Register
WDT Error
WDT_RSTn
July 31, 2018