Figure 148. Master Receiver Timing Diagram - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Close / Continue Transmission
The master device needs to reset the AA bit in the I2CCR register to send a NACK signal to the
slave device before the last data byte transfer has been completed. After the last data byte has
been received from the slave device, the master device will hold the SCL line at a logic low state
following after a NACK signal sent by the master device to the slave device. The STOP bit can be
set to terminate the data transfer process or re-assign the I2CTAR register to restart a new transfer.
7-bit Master Receiver
S Address A
STA ADRS
BEH1 BEH1
10-bit Master Receiver
S Header A Address
STA
BEH1
Sr
STA
BEH1
BEH1 : cleared by reading I2CSR register
BEH2 : cleared by reading I2CDR register
BEH3 : cleared by reading I2CDR register, set AA=0 to send NACK signal
BEH4 : cleared by reading I2CDR register, set STOP=1 to send STOP signal

Figure 148. Master Receiver Timing Diagram

Rev. 1.00
Data1 A Data2 A
RXDNE
BEH2
A
ADRS #1
BEH1
Header A Data1 A
ADRS #2
BEH1
401 of 486
DataN NA
...
RXDNE RXDNE
BEH2 BEH3
Data2 A
...
RXDNE RXDNE
BEH2 BEH2
P
RXDNE
BEH4
DataN NA P
RXDNE RXDNE
BEH3 BEH4
July 31, 2018