Figure 170. Rs485 Interface And Waveform - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Reference
Divisor Clock
TX
RTS
TXENP = 0
RTS
TXENP = 1

Figure 170. RS485 Interface and Waveform

RS485 Normal Multi-drop Operation Mode – NMM
When the RS485 mode is configured as an addressable slave, it will operate in the Normal Multi-
drop Operation Mode, NMM. This mode is enabled when the RSNMM field is set in the RS485CR
register. Regardless of the URRXEN value in the USRCR register, all the received data with a
parity bit "0" will be ignored until the first address byte is detected with a parity bit "1" and then
the received address byte will be stored in the RX FIFO. Once the first address data is detected
and stored in the RX FIFO, the RSADD flag in the USRSIFR register will be set and generate
an interrupt if the RSADDIE bit in the USRIER register is set to 1. Application software can
determine whether the receiver is enabled or disabled to accept the following data by configuring
the URRXEN bit. When the receiver is enabled by setting the URRXEN bit to 1, all received
data will be stored in the RX FIFO. Otherwise, all received data will be ignored if the receiver is
disabled by clearing the URRXEN bit to 0.
Rev. 1.00
RX
USART
TX
RTS
D6 D7 Parity
Start D0 D1 D2 D3 D4 D5
447 of 486
RS485 Transceiver
TG = 4
Stop
Bit
Bit
Differential
Bus
July 31, 2018