32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F50231/HT32F50241
(New value 2)
(New value 3)
(New value 1)
CHxCCR value
(Update Event)
Figure 51. Toggle Mode Channel Output Reference Signal – CHxPRE = 0
Counter Value
CRR
CHxCCR
(New value 2)
CHxCCR
(New value 3)
CHxCCR
(New value 1)
CHxCCR
Update
CHxCCR value
TME
CHxOREF
UEV
(Update Event)
Figure 52. Toggle Mode Channel Output Reference Signal – CHxPRE = 1
Rev. 1.00
Counter Value
(Output toggle, preload disable)
CRR
CHxCCR
CHxCCR
CHxCCR
CHxCCR
Update
(1)
TME
CHxOREF
UEV
CHxOM=0x3, CHxPRE=1
(Output toggle, preload enable)
(1)
(2)
202 of 486
CHxOM=0x3, CHxPRE=0
Time
(2)
(3)
(3)
Time
July 31, 2018
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