Holtek HT32F50231 User Manual page 5

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Port B Pull-Down Selection Register - PBPDR ............................................................................ 122
Port B Open-Drain Selection Register - PBODR ......................................................................... 123
Port B Output Drive Current Selection Register - PBDRVR ........................................................ 124
Port B Lock Register - PBLOCKR ................................................................................................ 125
Port B Data Input Register - PBDINR .......................................................................................... 126
Port B Output Data Register - PBDOUTR ................................................................................... 126
Port B Output Set / Reset Control Register - PBSRR .................................................................. 127
Port B Output Reset Register - PBRR ......................................................................................... 128
Port B Sink Current Enhanced Selection Register - PBSCER ..................................................... 128
Port C Data Direction Control Register - PCDIRCR .................................................................... 129
Port C Input Function Enable Control Register - PCINER ........................................................... 130
Port C Pull-Up Selection Register - PCPUR ................................................................................ 131
Port C Pull-Down Selection Register - PCPDR ........................................................................... 132
Port C Open Drain Selection Register - PCODR ......................................................................... 133
Port C Output Current Drive Selection Register - PCDRVR ........................................................ 134
Port C Lock Register - PCLOCKR ............................................................................................... 135
Port C Data Input Register - PCDINR .......................................................................................... 136
Port C Output Data Register - PCDOUTR ................................................................................... 136
Port C Output Set / Reset Control Register - PCSRR ................................................................. 137
Port C Output Reset Register - PCRR ......................................................................................... 138
Port C Sink Current Enhanced Selection Register - PCSCER .................................................... 138
9 Alternate Function Input / Output Control Unit (AFIO) .................................... 139
Introduction ........................................................................................................................ 139
Features ............................................................................................................................. 140
Functional Descriptions ..................................................................................................... 140
External Interrupt Pin Selection .................................................................................................... 140
Alternate Function ......................................................................................................................... 141
Lock Mechanism .......................................................................................................................... 141
Register Map ..................................................................................................................... 141
Register Descriptions ......................................................................................................... 142
EXTI Source Selection Register 0 - ESSR0 ................................................................................ 142
EXTI Source Selection Register 1 - ESSR1 ................................................................................ 143
GPIO x Configuration Low Register - GPxCFGLR, x = A, B, C ................................................... 144
GPIO x Configuration High Register - GPxCFGHR, x = A, B, C .................................................. 145
10 Nested Vectored Interrupt Controller (NVIC) .................................................. 146
Introduction ........................................................................................................................ 146
Features ............................................................................................................................. 147
Function Descriptions ........................................................................................................ 148
SysTick Calibration ....................................................................................................................... 148
Register Map ..................................................................................................................... 148
Rev. 1.00 5 of 486 July 31, 2018