Functional Description - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241

Functional Description

The Watchdog timer is formed from a 12-bit count-down counter and a fixed 3-bit prescaler. The
largest time-out period is 16 seconds, using the LSE or LSI clock and a 1/128 maximum prescaler
value.
The Watchdog timer configuration setup includes programmable counter reload value, reset
enable, window value and prescaler value. These configurations are set using the WDTMR0
and WDTMR1 registers which must be properly programmed before the Watchdog timer starts
counting. In order to prevent unexpected write operations to those configurations, a register write
protection function can be enabled by writing any value, other than 0x35CA to PROTECT[15:0],
in the WDTPR register. A value of 0x35CA can be written to PROTECT[15:0] to disable the
register write protection function before accessing any configuration register. A read operation on
PROTECT[0] can obtain the enable / disable status of the register write protection function.
During normal operation, the Watchdog timer counter should be reloaded before it underflows to
prevent the generation of a Watchdog reset. The 12-bit count-down counter can be reloaded with
the required Watchdog Timer Counter Value (WDTV) by first setting the WDTRS bit to 1 with the
correct key, which is 0x5FA0 in the WDTCR register.
If a software deadlock occurs during a Watchdog timer reload routine, the reload operation will
still go ahead and therefore the software deadlock cannot be detected. To prevent this situation
from occurring, the reload operation must be executed in such a way that the value of the Watchdog
timer counter is limited within a delta value (WDTD). If the Watchdog timer counter value is
greater than the delta value and a reload operation is executed, a Watchdog Timer error will
occur. The Watchdog timer error will generate a Watchdog reset if the related functional control is
enabled. Additionally, the above features can be disabled by programming a WDTD value greater
than or equal to the WDTV value.
The WDTERR and WDTUF f lags in the WDTSR register will be set respectively when the
Watchdog timer underflows or when a Watchdog timer error occurs. A system reset or write-one
operation on the WDTSR register clears the WDTERR and WDTUF flags.
The watchdog timer uses two clocks: PCLK and CK_WDT. The PCLK clock is used for APB
access to the watchdog registers. The CK_WDT clock is used for the Watchdog timer functionality
and counting. There is some synchronization logic between these two clock domains.
When the system enters the Sleep mode or Deep-Sleep1 mode, the Watchdog timer counter will
either continue to count or stop depending on the WDTSHLT bits in the WDTMR0 register.
However, the Watchdog Timer will always stop when the system is in the Deep-Sleep2 mode.
When the Watchdog stops counting, the count value is retained so that it continues counting after
the system is woken up from these three Sleep modes. A Watchdog reset will occur any time when
the Watchdog timer is running and when it has an operating clock source. When the system enters
the debug mode, the Watchdog timer counter will either continue to count or stop depending on the
DBWDT bit (in the MCUDBGCR register) in the Clock Control Unit.
Rev. 1.00 383 of 486 July 31, 2018