Embedded Flash Memory; Embedded Sram Memory; Ahb Peripherals; Apb Peripherals - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241

Embedded Flash Memory

The HT32F50231/50241 series provide up to 64 KB on-chip Flash memory which is located at
address 0x0000_0000. It supports byte, half-word and word access operations. Note that the
Flash memory only supports read operations for the bus access. Any write operations to the Flash
memory will cause a bus fault exception. The Flash memory has up to capacity of 64 pages. Each
page has a memory capacity of 1 KB and can be erased independently. A 32-bit programming
interface provides the capability of changing bits from 1 to 0. A data storage or firmware upgrade
can be implemented using several methods such as In System Programming (ISP), In Application
Programming (IAP) or In Circuit Programming (ICP). For more information, refer to the Flash
Memory Controller section.

Embedded SRAM Memory

The HT32F50231/50241 series contain up to 8 KB on-chip SRAM which is located at address
0x2000_0000. It support byte, half-word and word access operations.

AHB Peripherals

The address of the AHB peripherals ranges from 0x4008_0000 to 0x400F_FFFF. Some peripherals
such as Clock Control Unit, Reset Control Unit and Flash Memory Controller are connected to the
AHB bus directly. The AHB peripherals clocks are always enabled after a system reset. Access to
registers for these peripherals can be achieved directly via the AHB bus. Note that all peripheral
registers in the AHB bus support only word access.

APB Peripherals

The address of APB peripherals ranges from 0x4000_0000 to 0x4007_FFFF. An APB to AHB
Bridge provides access capability between the CPU and the APB peripherals. Additionally, the
APB peripheral clocks are disabled after a system reset. Software must enable the peripheral clock
by setting up the APBCCRn register in the Clock Control Unit before accessing the corresponding
peripheral register. Note that the APB to AHB Bridge will duplicate the half-word or byte data to
word width when a half-word or byte access is performed on the APB peripheral registers. In other
words, the access result of a half-word or byte access on the APB peripheral register will vary
depending on the data bit width of the access operation on the peripheral registers.
Rev. 1.00 33 of 486 July 31, 2018