Memory Organization; Figure 3. Bus Architecture - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
®
Cortex -M0+
Processor
NVIC

Figure 3. Bus Architecture

Memory Organization

The Arm ® Cortex
interface to external AHB peripheral. The processor accesses take priority over debug accesses.
The maximum address range of the Cortex
Additionally, a pre-defined memory map is provided by the Cortex
the software complexity of repeated implementation of different device vendors. However, some
regions are used by the Arm
Technical Reference Manual for more information. The following figure shows the memory map
of HT32F50231/50241 series of devices, including Code, SRAM, peripheral and other pre-defined
regions.
Rev. 1.00
GPIO
® -M0+ processor accesses and debug accesses share the single external
® -M0+ is 4 GB since it has 32-bit bus address width.
Cortex -M0+ system peripherals. Refer to the Arm
® ®
30 of 486
Flash Memory
Flash Memory
Interface
FMC
Control Registers
CKCU/RSTCU
Control Registers
AHB Peripherals
SRAM
SRAM Controller
AHB to APB
APB IPs
Bridge
® -M0+ processor to reduce
Cortex -M0+
® ®
July 31, 2018