Interrupts - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241

Interrupts

When an A/D conversion is completed, an End of Conversion EOC event will occur. There are
three kinds of EOC events which are known as single sample EOC, subgroup EOC and cycle EOC
for A/D conversion. A single sample EOC event will occur and the single sample EOC interrupt
raw flag, ADIRAWS bits in the ADCIRAW register, will be asserted when a single channel
conversion has completed. A subgroup EOC event will occur and the subgroup EOC interrupt
raw flag, ADIRAWG in the ADCIRAW register, will be asserted when a subgroup conversion has
completed. A cycle EOC event will occur and the cycle EOC interrupt raw flag, ADIRAWC bits in
the ADCIRAW register, will be asserted when a cycle conversion is finished. When a single sample
EOC, a subgroup EOC or a cycle EOC raw flag is asserted and the corresponding interrupt enable
bit, ADIES, ADIEG or ADIEC bit in the ADCIER register, is set to 1, the associated interrupt will
be generated.
After a conversion has completed, the 12-bit digital data will be stored in the associated ADCDRn
registers and the value of the data valid flag named as ADVLDn will be changed from low to high.
The converted data should be read by the application program, after which the data valid flag
ADVLDn will be automatically changed from high to low. Otherwise, a data overwrite event will
occur and the data overwrite interrupt raw flag ADIRAWO bit in the ADCIRAW register will be
asserted. When the related data overwrite raw flag is asserted, the data overwrite interrupt will be
generated if the interrupt enable bit ADIEO in the ADCIER register is set to 1.
If the A/D watchdog monitor function is enabled and the data after a channel conversion is less
than the lower threshold or higher than the upper threshold, the watchdog lower or upper threshold
interrupt raw flag ADIRAWL or ADIRAWU in the ADCIRAW register will be asserted. When
the ADIRAWL or ADIRAWU flag is asserted and the corresponding interrupt enable bit, ADIEL
or ADIEU in the ADCIER register, is set a watchdog lower or upper threshold interrupt will be
generated.
The A/D Converter interrupt clear bits are used to clear the associated A/D converter interrupt raw
and interrupt status bits. Writing a 1 into the specific A/D converter interrupt clear bit in the A/D
converter interrupt clear register ADCICLR will clear the corresponding A/D converter interrupt
raw status and interrupt status bits. These bits are automatically cleared to 0 by hardware after
being set to 1.
Rev. 1.00 168 of 486 July 31, 2018