Spi Fifo Time Out Counter Register - Spiftocr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
SPI FIFO Time Out Counter Register – SPIFTOCR
This register stores the SPI RX FIFO timeout counter value.
Offset: 0x020
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset RW 0 RW
7
Type/Reset RW 0 RW
Bits Field
[15:0] TOC
Rev. 1.00
30 29 28
22 21 20
14 13 12
0 RW 0 RW
6 5 4
0 RW 0 RW
Descriptions
Time Out Counter
The timeout counter starts to count from 0 after the SPI RX FIFO receives a data,
and reset the counter value once the data is read from the SPIDR register by
software or another new data is received. If the FIFO does not receive new data or
the software does not read data from the SPIDR register the timeout counter value
will continuously increase. When the timeout counter value is equal to the TOC
setting value, the TO flag in the SPISR register will be set and an interrupt will be
generated if the TOIEN bit in the SPIIEN register is set. The timeout counter will be
stopped when the RX FIFO is empty. The SPI FIFO timeout function can be disabled
by setting the TOC field to zero. The timeout counter is driven by the system APB
clock, named f .
PCLK
439 of 486
27 26
Reserved
19 18
Reserved
11 10
TOC
0 RW 0 RW 0 RW
3 2
TOC
0 RW 0 RW 0 RW
25 24
17 16
9 8
0 RW 0
1 0
0 RW 0
July 31, 2018