Spi Status Register - Spisr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
SPI Status Register – SPISR
This register contains the relevant SPI status.
Offset: 0x014
Reset value: 0x0000_0003
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
TO
Type/Reset WC 0 WC
Bits Field
[8] BUSY
[7] TO
[6] SA
[5] MF
[4] RO
Rev. 1.00
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
SA MF RO
0 WC 0 WC
Descriptions
SPI Busy flag
0: SPI not busy
1: SPI busy
In the master mode, this flag is reset when the TX buffer and TX shift register are
both empty and is set when the TX buffer or the TX shift register are not empty.
In the slave mode, this flag is set when SEL changes to an active level and is reset
when SEL changes to an inactive level.
Time Out flag
0: No RX FIFO time out
1: RX FIFO time out has occurred
Write 1 to clear it.
Once the timeout counter value is equal to the TOC field setting in the SPIFTOCR
register, the time out flag will be set and an interrupt will be generated if the TOIEN
bit in the SPIIER register is enabled. This bit is cleared by writing 1.
Note: This Time Out flag function is only available in the SPI FIFO mode.
Slave Abort flag
0: No slave abort
1: Slave abort has occurred
This bit is set by hardware and cleared by writing 1.
Mode Fault flag
0: No mode fault
1: Mode fault has occurred
This bit is set by hardware and cleared by writing 1.
Read Overrun flag
0: No read overrun
1: Read overrun has occurred
This bit is set by hardware and cleared by writing 1.
435 of 486
27 26
Reserved
19 18
Reserved
11 10
3 2
WC RXBNE
0 WC 0 RO 0 RO
25 24
17 16
9 8
BUSY
RO 0
1 0
TXE TXBE
1 RO 1
July 31, 2018