32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F50231/HT32F50241
Register Map
The following table shows the CRC registers and reset values.
Table 57. CRC Register Map
Register
CRCCR
0x000
CRCSDR
0x004
CRCCSR
0x008
CRCDR
0x00C
Register Descriptions
CRC Control Register – CRCCR
This register specifies the corresponding CRC function enable control.
Offset:
0x000
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
SUMCMPL SUMBYRV SUMBIRV DATCMPL DATBYRV
Type/Reset
RW
0 RW
Bits
Field
[7]
SUMCMPL
[6]
SUMBYRV
[5]
SUMBIRV
[4]
DATCMPL
[3]
DATBYRV
Rev. 1.00
Offset
CRC Control Register
CRC Seed Register
CRC Checksum Register
CRC Data Register
30
29
28
22
21
20
14
13
12
6
5
4
0 RW
0 RW
Descriptions
1's Complement operation on Checksum Output
0: Disable
1: Enable
Byte Reverse operation on Checksum Output
0: Disable
1: Enable
Bit Reverse operation on Checksum Output
0: Disable
1: Enable
1's Complement operation on Data
0: Disable
1: Enable
Byte Reverse operation on Data
0: Disable
1: Enable
482 of 486
Description
27
26
Reserved
19
18
Reserved
11
10
Reserved
3
2
DATBIRV
0 RW
0 RW
0 RW
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
25
24
17
16
9
8
1
0
POLY
0 RW
0
July 31, 2018
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