32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F50231/HT32F50241
Bits
Field
[11:8]
SMSEL
[0]
TSE
Rev. 1.00
Descriptions
Slave Mode Selection
SMSEL [2:0]
Mode
000
Disable mode The prescaler is clocked directly by the internal clock.
001
—
010
—
011
—
100
Restart Mode
101
Pause Mode
110
Trigger Mode
111
STIED
Timer Synchronization Enable
0: No action
1: Master timer (current timer) will generate a delay to synchronize its slave timer
through the MTO signal
270 of 486
Descriptions
Reserved
Reserved
Reserved
The counter value restarts from 0 or the CRR shadow
register value depending upon the counter mode on
the rising edge of the STI signal. The registers will
also be updated.
The counter starts to count when the selected trigger
input STI is high. The counter stops counting on the
instant, not being reset, when the STI signal changes
its state to a low level. Both the counter start and stop
control are determined by the STI signal.
The counter starts to count from the original value in
the counter on the rising edge of the selected trigger
input STI. Only the counter start control is determined
by the STI signal.
The rising edge of the selected trigger signal STI will
clock the counter.
July 31, 2018
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