32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F50231/HT32F50241
Channel 3 Capture/Compare Register – CH3CCR
This register specifies the timer channel 3 capture/compare value.
Offset:
0x09C
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
RW
0 RW
7
Type/Reset
RW
0 RW
Bits
Field
[15:0]
CH3CCV
Rev. 1.00
30
29
28
22
21
20
14
13
12
0 RW
0 RW
6
5
4
0 RW
0 RW
Descriptions
Channel 3 Capture/Compare Value
- When Channel 3 is configured as an output
The CH3CCR value is compared with the counter value and the comparison result
is used to trigger the CH3OREF output signal.
- When Channel 3 is configured as an input
The CH3CCR register stores the counter value captured by the last channel 3
capture event.
370 of 486
27
26
Reserved
19
18
Reserved
11
10
CH3CCV
0 RW
0 RW
0 RW
3
2
CH3CCV
0 RW
0 RW
0 RW
25
24
17
16
9
8
0 RW
0
1
0
0 RW
0
July 31, 2018
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