Page 1: Pe�Iodic Tm Ope�Ation
A/D Flash MCU with EEPROM HT66F488/ HT66F489 Revision: V1.21 Date: �ove��e� �� 2�1� �ove��e� �� 2�1�...
Page 2: Table Of Contents
HT66F488/HT66F489 A/D Flash MCU with EEPROM Table of Contents Features ......................7 CPU Featu�es ......................... � Pe�iphe�al Featu�es ......................... � General Description ..................8 Selection Table ....................8 Block Diagram ....................9 Pin Assignment ....................9 Pin Descriptions .................... 10 Absolute Maximum Ratings ................
Page 3 HT66F488/HT66F489 A/D Flash MCU with EEPROM EEPROM Data Memory .................. 31 EEPROM Data Me�o�y St�uctu�e ..................31 EEPROM Registe�s ......................31 Reading Data f�o� the EEPROM ..................33 W�iting Data to the EEPROM ....................33 W�ite P�otection ........................33 EEPROM Inte��upt ........................ 33 P�og�a��ing Conside�ations ....................
Page 4 HT66F488/HT66F489 A/D Flash MCU with EEPROM Timer Modules – TM ..................59 Int�oduction ........................... 5� TM Ope�ation ........................6� TM Clock Sou�ce ........................6� TM Inte��upts ......................... 6� TM Exte�nal Pins ........................6� TM Input/Output Pin Cont�ol Registe� ................... 61 P�og�a��ing Conside�ations ....................
Page 5: Pe�Iodic Type Tm Ope�Ating Modes
HT66F488/HT66F489 A/D Flash MCU with EEPROM UART Module Serial Interface ..............131 UART Exte�nal Inte�face ..................... 131 UART Data T�ansfe� Sche�e....................132 UART Status and Cont�ol Registe�s..................132 Baud Rate Gene�ato� ......................138 Calculating the �egiste� and e��o� values ................138 UART Setup and Cont�ol.....................
Page 6: Standa�D Type Tm Registe� Desc�Iption
HT66F488/HT66F489 A/D Flash MCU with EEPROM Instruction Set Summary ................172 Ta�le Conventions ....................... 1�2 Extended Inst�uction Set ..................... 1�4 Instruction Definition ................... 176 Extended Instruction Definition ................... 185 Package Information ................... 192 28-pin SOP (3��il) Outline Di�ensions ................1�3 28-pin SSOP (15��il) Outline Di�ensions .................
Page 7: Features
• Internal High Frequency RC -- HIRC • Internal 32kHz -- LIRC • Fully intergrated internal 8MHz oscillator requires no external components • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • All instructions executed in one to three instruction cycles • Table read instructions • 115 powerful instructions • 8-level subroutine nesting • Bit manipulation instruction Peripheral Features • Flash Program Memory: 8K×16 (HT66F489)/4K×16 (HT66F488) • RAM Data Memory: 384×8 • True EEPROM Memory: 64×8 • Watchdog Timer function • 30 bidirectional I/O lines • LED driver • 1/3 Bias Software LCD • Serial Interface Module – SIM for SPI or I • UART Function • Six pin-shared external interrupts • Multiple Timer Module for time measure, input capture, compare match output, PWM output...
Page 8: General Description
HT66F488/HT66F489 A/D Flash MCU with EEPROM General Description The devices are 8-bit high performance RISC architecture microcontroller, designed especially for applications that interface directly to analog signals, such as those from sensor. Offering users the convenience of Flash Memory multi-programming features, this device also includes a wide range of functions and features. Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile data such as serial numbers, calibration data etc. Analog features include a multi-channel 12-bit A/D converter. Multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM generation functions. Communication with the outside world catered for by including fully integrated SPI, I C and UART interface functions, three popular interfaces which provide designers with a means of easy communication with external peripheral hardware. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A full choice of HXT, LXT, HIRC and LIRC oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimize power consumption.
Page 9: Block Diagram
HT66F488/HT66F489 A/D Flash MCU with EEPROM Block Diagram HXT/ LXT Watchdog Internal RC Oscillators Timer Oscillators 8-bit RISC Reset Flash/EEPROM Programming Circuitry Circuit (ICP)/OCDS Core Voltage Voltage Interrupt Detect Reset Controller EEPROM Flash RAM Data Time 12-bit A/D Data Program...
Page 10: Pin Descriptions
HT66F488/HT66F489 A/D Flash MCU with EEPROM Pin Descriptions Pin Name Function Description PAWU PA� CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up and wake-up PAPU PA�/OCDSDA/ SSEG6 OCDSDA — CMOS OCDS Data/Add�ess pin� fo� EV chip only SSEG6 SLCDC2 — CMOS Softwa�e LCD SEG output PAWU CMOS Gene�al pu�pose I/O.
Page 11 HT66F488/HT66F489 A/D Flash MCU with EEPROM Pin Name Function Description PBPU CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up. OSC2 — HXT pin PB3/OSC2/XT2/ SSEG15 — LXT pin SSEG15 SLCDC3 — CMOS Softwa�e LCD SEG output PBPU CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.
Page 12 HT66F488/HT66F489 A/D Flash MCU with EEPROM Pin Name Function Description PD� PDPU CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up. ICPDA — CMOS ICP Data/Add�ess pin PD�/ICPDA/ SLCDC� SCOM� — CMOS Softwa�e LCD COM output SCOM�/SSEG� SLCDC1 SLCDC� SSEG� — CMOS Softwa�e LCD SEG output...
Page 13: Absolute Maximum Ratings
HT66F488/HT66F489 A/D Flash MCU with EEPROM Absolute Maximum Ratings Supply Voltage ....................V −0.3V to V +6.0V Input Voltage ....................V −0.3V to V +0.3V Storage Temperature .....................-50˚C to 125˚C Operating Temperature ....................-40˚C to 85˚C Total ........................... -150mA Total ............................ 100mA Total Power Dissipation ......................500mW Note: T hese are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to these devices. Functional operation of...
Page 14 HT66F488/HT66F489 A/D Flash MCU with EEPROM Test Conditons Symbol Parameter Min. Typ. Max. Unit Conditons — μA �o load� ADC off� WDT ena�le� LXTLP=� — 3� 5� μA Ope�ating Cu��ent� Slow Mode � — 1� 2� μA �o load� ADC off�...
Page 15: A.c. Characteristics
HT66F488/HT66F489 A/D Flash MCU with EEPROM A.C. Characteristics Ta=25°C Test Conditons Symbol Parameter Min. Typ. Max. Unit Conditions 2.2V~5.5V �.4 — 2.�V~5.5V �.4 — 1� Syste� clock (HXT) — 3.3V~5.5V �.4 — 4.5V~5.5V �.4 — Syste� clock (HIRC) Ta=�°C~��°C Syste� clock (LXT) —...
Page 16: Lvr & Lvd Characteristics
HT66F488/HT66F489 A/D Flash MCU with EEPROM LVR & LVD Characteristics Ta=25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions LVR Ena�le� 2.1�V option 2.1� LVR Ena�le� 2.55V option 2.55 Low Voltage Reset Voltage — LVR Ena�le� 3.15V option 3.15 LVR Ena�le�...
Page 17: A/D Converter Electrical Characteristics
HT66F488/HT66F489 A/D Flash MCU with EEPROM A/D Converter Electrical Characteristics Ta=25°C Test Conditons Symbol Parameter Min. Typ. Max. Unit Conditons A/D Conve�te� Ope�ating Voltage — — — ADC Input Voltage — — � — ADC Refe�ence Voltage — — —...
Page 18: System Architecture
HT66F488/HT66F489 A/D Flash MCU with EEPROM System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The device takes advantage of the usual features found within RISC microcontrollers providing increased speed of operation and Periodic performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume production for controller applications.
Page 19 HT66F488/HT66F489 A/D Flash MCU with EEPROM For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. F e t c h I n s t . 1 E x e c u t e I n s t . 1 M O V A , [ 1 2 H ] F e t c h I n s t .
Page 20: Stack
HT66F488/HT66F489 A/D Flash MCU with EEPROM Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P r o g r a m C o u n t e r T o p o f S t a c k...
Page 21: Flash Program Memory
HT66F488/HT66F489 A/D Flash MCU with EEPROM Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, this Flash device offers users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating.
Page 22: Look-Up Ta�Le
HT66F488/HT66F489 A/D Flash MCU with EEPROM Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the “TABRD [m]” or “TABRDL [m]” instructions respectively when the memory [m] is located in sector 0. If the memory [m] is located in other sectors, the table data can be retrieved from the Program Memory using the “LTABRD [m]” or “LTABRDL [m]” instructions respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as 0. The accompanying diagram illustrates the addressing data flow of the look-up table. P r o g r a m M e m o r y L a s t p a g e o r...
Page 23: In Ci�Cuit P�Og�A
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh In Circuit Programming The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. The Holtek Flash MCU to Writer Programming Pin correspondence table is as follows: Holtek Write Pins MCU Programming Pins Function ICPDA PD� P�og�a��ing Se�ial Data ICPCK P�og�a��ing Se�ial Clock Powe� Supply G�ound The Program Memory and EEPROM data memory can both be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional...
Page 24: On-Chip De�Ug Suppo�T - Ocds
On-Chip Debug Support – OCDS There is an EV chip, HT66V488/489, which is used to emulate the HT66F488/HT66F489 device. This EV chip device also provides an “On-Chip Debug” function to debug the device during the development process. The EV chip and the actual MCU devices are almost functionally compatible except for the “On-Chip Debug” function. Users can use the EV chip device to emulate the real chip device behavior by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip for debugging, other functions which are shared with the OCDSDA and OCDSCK pins in the actual MCU device will have no effect in the EV chip. For a more detailed OCDS description, refer to the corresponding document named “Holtek e-Link for 8-bit MCU OCDS User’s Guide”. Holtek e-Link Pins EV Chip Pins Pin Description OCDSDA OCDSDA OCDS Data/Add�ess input/output OCDSCK OCDSCK OCDS Clock input Powe� Supply G�D G�ound Rev. 1.21...
Page 25: Ram Data Memory
HT66F488/HT66F489 A/D Flash MCU with EEPROM RAM Data Memory The Data Memory is an 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two types, the first of Data Memory is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. Structure The Data Memory is divided into several sectors, all of which are implemented in 8-bit wide Memory. Each of the Data Memory sectors is categorized into two types, the Special Purpose Data...
Page 26: Special Pu�Pose Data Me�O�Y
HT66F488/HT66F489 A/D Flash MCU with EEPROM Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. They are overlapped in any sector. Most of the registers are both readable and writable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused before...
Page 27: Special Function Register Description
HT66F488/HT66F489 A/D Flash MCU with EEPROM Special Function Register Description Most of the Special Function Register details will be described in the relevant functional sections, however several registers require a separate description in this section. Indirect Addressing Register – IAR0, IAR1, IAR2 The Indirect Addressing Registers, IAR0, IAR1 and IAR2, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0, IAR1 and IAR2 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0, MP1L/MP1H or MP2L/MP2H. Acting as a pair, IAR0 and MP0 can together access data only from Sector 0 while the IAR1 register together with MP1L/MP1H register pair and IAR2 register together with MP2L/MP2H register pair can access data from any Data Memory sector. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of “00H” and writing to the registers indirectly will result in no operation.
Page 28 HT66F488/HT66F489 A/D Flash MCU with EEPROM Indirect Addressing Program Example 1 data .section ‘data’ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a, 04h ;...
Page 29 HT66F488/HT66F489 A/D Flash MCU with EEPROM Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user-defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted.
Page 30 HT66F488/HT66F489 A/D Flash MCU with EEPROM • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by executing the “HALT” instruction. • TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. STATUS Register �a�e � � “x” unknown Bit 7 SC: The result of the “XOR” operation which is performed by the OV flag and the MSB of the instruction operation result. Bit 6 CZ: The the operational result of different flags for different instructions. For SUB/SUBM/LSUB/LSUBM instructions, the CZ flag is equal to the Z flag. For SBC/SBCM/LSBC/LSBCM instructions, the CZ flag is the “AND” operation result which is performed by the previous operation CZ flag and current operation zero flag.
Page 31: Eeprom Data Memory
HT66F488/HT66F489 A/D Flash MCU with EEPROM EEPROM Data Memory One of the special features in the device is its internal EEPROM Data Memory. EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form of memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. EEPROM Data Memory Structure The EEPROM Data Memory capacity is 64×8 bits for the device. Unlike the Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. Read and Write operations to the EEPROM are carried out in single byte operations using an address and data register in Sector 0 and a single control register in Sector 1. EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory. These are the address register, EEA, the data register, EED and a single control register, EEC. As both the EEA and EED registers are located in all sectors, they can be directly accessed in the same was as any other Special Function Register. The EEC register however, being located in Sector 1, cannot be directly addressed directly and can only be read from or written to indirectly using the MP1L/MP1H or MP2L/MP2H Memory Pointer and Indirect Addressing Register, IAR1 or IAR2. Because the EEC control register is located at address 40H in Sector 1, the MP1L or MP2L Memory Pointer low byte must first be set to the value 40H and the MP1H or MP2H Memory Pointer high byte set to the value 01H before any operations on the EEC register are executed. Register Name —...
Page 32 HT66F488/HT66F489 A/D Flash MCU with EEPROM EED Register �a�e D� D� � � � � � � � � D7~D0: Data EEPROM data Bit 7~0 Data EEPROM data bit 7 ~ bit 0 EEC Register �a�e — — — — WRE� RDE� — — — — — — — — �...
Page 33: Reading Data F�O� The Eeprom
HT66F488/HT66F489 A/D Flash MCU with EEPROM Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Writing Data to the EEPROM The EEPROM address of the data to be written must first be placed in the EEA register and the data placed in the EED register. To write data to the EEPROM, the write enable bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the EEC register must be immediately set high to initiate a write cycle. These two instructions must be executed consecutively. The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered-on the Write Enable bit in the control register will be cleared preventing any write operations. Also at power-on MP1L/MP1H and MP2L/MP2H will be reset to zero, which means...
Page 34: P�Og�A
HT66F488/HT66F489 A/D Flash MCU with EEPROM Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be Periodic by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Bank Pointer could be normally cleared to zero as this would inhibit access to Bank 1where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally complete. Otherwise, the EEPROM read or write operation will fail. Programming Examples Reading data from the EEPROM - polling method MOV A, EEPROM_ADRES ;...
Page 35: Oscillator
HT66F488/HT66F489 A/D Flash MCU with EEPROM Oscillator Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. The external oscillators requiring some external components as well as fully integrated internal oscillators requiring no external components are provided to form a wide range of both fast and slow system oscillators. All oscillator options...
Page 36: Exte�Nal C�Ystal/Ce�A�Ic Oscillato� - Hxt
HT66F488/HT66F489 A/D Flash MCU with EEPROM High Speed Oscillators 6-stage Prescaler HIRC High Speed Oscillator Configuration Option Low Speed Oscillators LIRC HLCLK, CKS2~CKS0 bits Low Speed Oscillator Configuration Option Fast Wake-up from SLEEP Mode or IDLE Mode Control (for HXT only) Note: The OSC1/XT1 and OSC2/XT2 share the same pins, so the HXT oscillator and the LXT oscillator can not be selected at the same time.
Page 37 HT66F488/HT66F489 A/D Flash MCU with EEPROM Crystal Oscillator C1 and C2 Values Crystal Frequency 12MHz �pF �pF 8MHz �pF �pF 4MHz �pF �pF 1MHz 1��pF 1��pF �ote: C1 and C2 values a�e fo� guidance only. Crystal Recommended Capacitor Values Internal RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components.
Page 38: Inte�Nal 32Khz Oscillato� - Lirc
HT66F488/HT66F489 A/D Flash MCU with EEPROM I n t e r n a l X T 1 O s c i l l a t o r C i r c u i t I n t e r n a l R C 3 2 .
Page 39: Operating Modes And System Clocks
HT66F488/HT66F489 A/D Flash MCU with EEPROM Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided this device with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The device has many different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock options using configuration options and register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency, f , or a low frequency, f , and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from either an HXT or HIRC oscillator, selected via a configuration option.
Page 40: Syste� Ope�Ation Modes
HT66F488/HT66F489 A/D Flash MCU with EEPROM System Operation Modes There are 6 different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are three modes allowing normal operation of the microcontroller, the NORMAL, SLOW0 and SLOW1 Mode. The remaining three modes, the SLEEP, IDLE0 and IDLE1 Modes are used when the microcontroller CPU is switched off to conserve power.
Page 41: Cont�Ol Registe
HT66F488/HT66F489 A/D Flash MCU with EEPROM IDLE1 Mode The IDLE1 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational such as the Watchdog Timer and TMs. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. In the IDLE1 Mode the Watchdog Timer clock, f , will be on. Control Register A single register, SMOD, is used for overall control of the internal clocks within the device. SMOD Register �a�e CKS2 CKS1 CKS� FSTE� IDLE� HLCLK � � � � � � CKS2 ~ CKS0: The system clock selection bits when HLCLK=0 Bit 7 ~ 5 000: f (LIRC or LXT)
Page 42: Fast Wake-Up
HT66F488/HT66F489 A/D Flash MCU with EEPROM IDLEN: IDLE Mode Control Bit 1 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. Bit 0 HLCLK: System Clock Selection 0: f /2 ~ f /64 or f 1: f This bit is used to select if the f clock or the f /2 ~ f /64 or f clock is used as the system clock. When the bit is high the f clock will be selected and if low the f /2 ~ /64 or f clock will be selected. When system clock switches from the f clock to the clock and the f clock will be automatically switched off to conserve power. CTRL Register �a�e FSYSO�...
Page 43: Ope�Ating Mode Switching
HT66F488/HT66F489 A/D Flash MCU with EEPROM If the HIRC oscillators or LIRC oscillator is used as the system oscillator then it will take 15~16 clock cycles or 1~2 cycles to wake up the system from the SLEEP or IDLE0 Mode. The Fast Wake-up bit, FSTEN will have no effect in these cases. System Wake-up Time Wake-up Time Wake-up Time FSTEN Bit Oscillator (SLEEP Mode) (IDLE0 Mode) (IDLE1 Mode) � 128 HXT cycles 1~2 HXT cycles 1~2 f cycles (Syste� �uns with f first for 128 HXT cycles and 1~2 HXT cycles then switches ove�...
Page 44 HT66F488/HT66F489 A/D Flash MCU with EEPROM NORMAL Mode to SLOW1 Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW1 Mode by setting the HLCLK bit to “0” and setting the CKS2~CKS0 bits to “010”, “011”, “100”, “101”, “110” or “111” in the SMOD register.This will then use a divided clock of the high speed system oscillator which can reduce the operating current. The SLOW1 Mode is still sourced from the HIRC or HXT oscillator and therefore requires less time for full mode switching. SLOW0 Mode to NORMAL Mode Switching In SLOW0 Mode the system uses LIRC or LXT low speed system oscillator. To switch back to the...
Page 45: Stand�Y Cu
HT66F488/HT66F489 A/D Flash MCU with EEPROM Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the FSYSON bit in CTRL register equal to “1”. When this instruction is executed under the conditions described above, the following will occur: • The system clock and Time Base clock and f will be on and the application program will stop SUB at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected...
Page 46: P�Og�A
HT66F488/HT66F489 A/D Flash MCU with EEPROM Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the “HALT” instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the “HALT” instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Programming Considerations The high speed and low speed oscillators both use the same SST counter. For example, if the system is woken up from the SLEEP Mode and the HIRC oscillators need to start-up from an off state. • If the device is woken up from the SLEEP Mode to NORMAL Mode, and the system clock source is from HXT oscillator and FSTEN is “1”, the system clock can be switched to the LIRC or LXT oscillator after wake up. • There are peripheral functions, such as TMs, for which the f is used. If the system clock source is switched from f to f , the clock source to the peripheral functions mentioned above will change accordingly.
Page 47 HT66F488/HT66F489 A/D Flash MCU with EEPROM WDTC Register �a�e WE� WS� � � � � WE4 ~ WE0: WDT function software control Bit 7~ 3 10101/01010: WDT enable Other values: Reset MCU When these bits are changed to any other values by the environmental noise to reset the microcontroller, the reset operation will be activated after 2~3 t clock cycles and the WRF bit in the CTRL register will be set to 1to indicate the reset source. Bit 2~ 0 WS2 ~ WS0: WDT Time-out period selection 000: 2 001: 2 SUB 010: 2 011: 2 100: 2 101: 2 110: 2 111: 2 These three bits determine the division ratio of the Watchdog Timer sourece clock, which in turn determines the timeout period.
Page 48: Watchdog Ti�E� Ope�Ation
HT66F488/HT66F489 A/D Flash MCU with EEPROM Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, the clear WDT instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. With regard to the Watchdog Timer enable/reset function, there are five bits, WE4~WE0, in the WDTC register to additional enable and reset control of the Watchdog Timer. WE4 ~ WE0 Bits WDT Function 1�1�1B/�1�1�B Ena�le Any othe� value Reset MCU Watchdog Timer Enable/Reset Control Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is a WDT reset, which means a value other than 01010B and 10101B is written into the WE4~WE0 bit locations, the second is using the Watchdog Timer software clear instructions and the third is via a HALT instruction. There is only one method of using software instruction to clear the...
Page 49: Reset And Initialisation
HT66F488/HT66F489 A/D Flash MCU with EEPROM Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are several ways in which a microcontroller reset can occur, through events occurring both internally and externally: Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that...
Page 50 HT66F488/HT66F489 A/D Flash MCU with EEPROM • LVRC Register �a�e LVS� LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS� � � � � Bit 7 ~ 0 LVS7 ~ LVS0: LVR Voltage Select control 01010101: 2.1V 00110011: 2.55V 10011001: 3.15V 10101010: 3.8V Other values: MCU reset – register is reset to POR value When an actual low voltage condition occurs, as specified by one of the four defined LVR voltage values above, an MCU reset will be generated. The reset operation will be activated after 2~3 LIRC/LXT clock cycles. In this situation this register contents will remain the same after such a reset occurs. • CTRL Register �a�e FSYSO�...
Page 51: Reset Initial Conditions
HT66F488/HT66F489 A/D Flash MCU with EEPROM Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to “0” and the TO flag will be set to “1”. Refer to the A.C. Characteristics for details. W D T T i m e - o u t S S T I n t e r n a l R e s e t Note: The t is 15~16 clock cycles if the system clock source is provided by the HIRC.
Page 52 HT66F488/HT66F489 A/D Flash MCU with EEPROM Reset WDT Time-out WDT Time-out Register LVR Reset (Power On) (Normal Operation) (HALT) IAR� x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u MP�...
Page 53 HT66F488/HT66F489 A/D Flash MCU with EEPROM Reset WDT Time-out WDT Time-out Register LVR Reset (Power On) (Normal Operation) (HALT) ADRH(ADRFS=1) - - - - x x x x - - - - x x x x - - - - x x x x - - - - u u u u ADCR�...
Page 54: Input/Output Ports
HT66F488/HT66F489 A/D Flash MCU with EEPROM Reset WDT Time-out WDT Time-out Register LVR Reset (Power On) (Normal Operation) (HALT) TXR/RXR x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u SLCDC�...
Page 55: Pull-High Resisto�S
HT66F488/HT66F489 A/D Flash MCU with EEPROM Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU~PDPU, and are implemented using weak PMOS transistors. Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. I/O Port Control Registers Each I/O port has its own control register known as PAC~PDC, to control the input/output configuration. With this control register, each CMOS output or input can be reconfigured...
Page 56 HT66F488/HT66F489 A/D Flash MCU with EEPROM P u l l - H i g h C o n t r o l B i t O p t i o n W e a k D a t a B u s...
Page 57 HT66F488/HT66F489 A/D Flash MCU with EEPROM I/O Port source current selection The PA~PD input/output ports have programmable source current functions. Four levels of source current can be selected by the registers. IOHR0 Register �a�e IOHS31 IOHS3� IOHS21 IOHS2� IOHS11 IOHS1� IOHS�1 IOHS�� Bit 7~6 IOHS31~IOHS30: PA3 source current output selection bit 00: Full source current output 01: 10/22 full source current output 10: 7/22 full source current output 11: 4/22 full source current output Bit 5~4 IOHS21~IOHS20: PA2 source current output selection bit...
Page 58 HT66F488/HT66F489 A/D Flash MCU with EEPROM IOHS41~IOHS40: PA4 source current output selection bit Bit 1~0 00: Full source current output 01: 10/22 full source current output 10: 7/22 full source current output 11: 4/22 full source current output IOHR2 Register �a�e IOHSB1 IOHSB� IOHSA1 IOHSA� IOHS�1 IOHS�� IOHS81 IOHS8� � � � � � � � � IOHSB1~IOHSB0: PC4~PC7 source current output selection bit Bit 7~6 00: Full source current output 01: 10/22 full source current output 10: 7/22 full source current output 11: 4/22 full source current output IOHSA1~IOHSA0: PC0~PC3 source current output selection bit Bit 5~4 00: Full source current output...
Page 59: Timer Modules - Tm
HT66F488/HT66F489 A/D Flash MCU with EEPROM Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers, PAC~PDC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA~PD, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the “SET [m].i” and “CLR [m].i” instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions the device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two...
Page 60: Tm Ope�Ation
HT66F488/HT66F489 A/D Flash MCU with EEPROM TM Operation The three different types of TMs offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. When the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the xTnCK2~xTnCK0 bits in the TM control registers. The clock source can be a ratio of either the system clock f or the internal high clock f , the f clock source or the external xTCKn pin. The xTCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting. TM Interrupts The Compact, Standard and Periodic type TMs each has two internal interrupts, the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated, it can be used to clear the counter and also to change the...
Page 61: Tm Input/Output Pin Cont�Ol Registe
HT66F488/HT66F489 A/D Flash MCU with EEPROM TM Input/Output Pin Control Register Selecting to have a TM input/output or whether to retain its other shared function is implemented using one register, with a single bit in the register corresponding to a TM input/output pin. Setting the bit high will setup the corresponding pin as a TM input/output, if reset to zero the pin will retain its original other function. TMPC0 Register �a�e — PTP1CP� — PTP�CP� — STPCP� — CTPCP� — — — — — � — � — � — � Bit 7 Unimplemented, read as...
Page 62 HT66F488/HT66F489 A/D Flash MCU with EEPROM PB7 data bit STPCP0 STPCP0 STM Mode Controller (STM) STM Function Pin Control Block Diagram PB0 data bit PTP0 PTP0CP0 PTP0CP0 PTM Mode Controller (PTM0) PTP0 PTP0 PA5 data bit PTP1 PTP1CP0 PTP1CP0 PTM Mode Controller...
Page 63: P�Og�A
HT66F488/HT66F489 A/D Flash MCU with EEPROM Programming Considerations The TM Counter Registers and the Capture/Compare CCRA or CCRP register, being either 10-bit or 16-bit, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA and CCRP registers are implemented in the way shown in the following diagram and accessing this register is carried out in a specific way described above, it is recommended to use the “MOV” instruction to access the CCRA or CCRP low byte register, named xTMnAL or PTMnRPL, in the following access procedures. Accessing the CCRA or CCRP low byte register without following these access procedures will result in unpredictable values. TM Counte� Registe� (Read only) xTMnDL xTMnDH 8-�it Buffe�...
Page 64: Compact Type Tm - Ctm
HT66F488/HT66F489 A/D Flash MCU with EEPROM Compact Type TM – CTM Although the simplest form of the three TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive one external output pin. C C R P C o m p a r a t o r P M a t c h...
Page 65: Co�Pact Type Tm Registe� Desc�Iption
HT66F488/HT66F489 A/D Flash MCU with EEPROM Compact Type TM Register Description Overall operation of each Compact TM is controlled using several registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Register Name CTMC� CTPAU CTCK2 CTCK1 CTCK� CTO� CTRP2 CTRP1 CTRP� CTMC1 CTM1 CTM� CTIO1 CTIO� CTOC CTPOL CTDPX CTCCLR CTMDL D� D� CTMDH —...
Page 66 HT66F488/HT66F489 A/D Flash MCU with EEPROM If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the CTOC bit, when the CTON bit changes from low to high. CTRP2~CTRP0: CTM CCRP 3-bit register, compared with the CTM Counter bit9~bit7 Bit 2 ~ 0 Comparator P Match Period 000: 1024 CTM clocks 001: 128 CTM clocks 010: 256 CTM clocks 011: 384 CTM clocks 100: 512 CTM clocks 101: 640 CTM clocks 110: 768 CTM clocks 111: 896 CTM clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter's highest three bits. The result of this comparison can be selected to clear the internal counter if the CTCCLR bit is set to zero. Setting the CTCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value.
Page 67 HT66F488/HT66F489 A/D Flash MCU with EEPROM In the Compare Match Output Mode, the CTIO1~CTIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the CTIO1~CTIO0 bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the CTOC bit. Note that the output level requested by the CTIO1~CTIO0 bits must be different from the initial value setup using the CTOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the CTON bit from low to high. In the PWM Mode, the CTIO1 and CTIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values...
Page 68 HT66F488/HT66F489 A/D Flash MCU with EEPROM CTMDL Register �a�e D� D� � � � � � � � � D7~D0: CTM Counter Low Byte Register bit 7 ~ bit 0 Bit 7 ~ 0 CTM 10-bit Counter bit 7 ~ bit 0 CTMDH Register �a�e — — — — — — D� — — — — — — — —...
Page 69 HT66F488/HT66F489 A/D Flash MCU with EEPROM Compact Type TM Operating Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Output Mode or Timer/Counter Mode. The operating mode is selected using the CTM1 and CTM0 bits in the CTMC1 register. Compare Match Output Mode To select this mode, bits CTM1 and CTM0 in the CTMC1 register, should be set to 00 or 01 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match...
Page 70 HT66F488/HT66F489 A/D Flash MCU with EEPROM Counte� CTCCLR = �; CTM[1:�] = �� / �1 Counte� Value ove�flow CCRP > � Counte� clea�ed �y CCRP value CCRP = � �x3FF Counte� Resu�e Reset CCRP > � CCRP Pause Stop CCRA Ti�e...
Page 71 HT66F488/HT66F489 A/D Flash MCU with EEPROM CTCCLR = 1; CTM[1:�] = �� / �1 Counte� Value CCRA > � Counte� clea�ed �y CCRA value CCRA = � Counte� ove�flow �x3FF Resu�e CCRA = � CCRA Counte� Reset Pause Stop CCRP Ti�e...
Page 72 HT66F488/HT66F489 A/D Flash MCU with EEPROM Timer/Counter Mode To select this mode, bits CTM1 and CTM0 in the CTMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits CTM1 and CTM0 in the CTMC1 register should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the CTCCLR bit has no effect as the PWM...
Page 73 HT66F488/HT66F489 A/D Flash MCU with EEPROM Counter CTDPX=0;CTM[1:0]=10 Value Counter Cleared by CCRP Counter reset when CTON returns high CCRP Counter stop if Pause Resume CTON bit low CCRA Time CTON CTPAU CTPOL CCRA Int. Flag CTMAF CCRP Int. Flag CTMPF...
Page 74 HT66F488/HT66F489 A/D Flash MCU with EEPROM Counte� Value CTDPX=1;CTM[1:�]=1� Counte� Clea�ed �y CCRA Counte� �eset when CTO� �etu�ns high CCRA Counte� stop if CTO� �it low Pause Resu�e CCRP Ti�e CTO� CTPAU CTPOL CCRP Int. Flag CTMPF CCRA Int. Flag CTMAF...
Page 75: Standard Type Tm - Stm
HT66F488/HT66F489 A/D Flash MCU with EEPROM Standard Type TM – STM The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can drive one external output pin. C C R P C o m p a r a t o r P M a t c h 8 - b i t C o m p a r a t o r P...
Page 76 HT66F488/HT66F489 A/D Flash MCU with EEPROM Standard Type TM Register Description Overall operation of the Standard TM is controlled using series of registers. A read only register pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as eight CCRP bits. Register Name STMC� STPAU STCK2 STCK1 STCK� STO� — — — STMC1 STM1 STM� STIO1 STIO� STOC STPOL STDPX STCCLR STMDL D� D� STMDH D1�...
Page 77 HT66F488/HT66F489 A/D Flash MCU with EEPROM If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the STOC bit, when the STON bit changes from low to high. Bit 2 ~ 0 Unimplemented, read as “0” STMC1 Register �a�e STM1 STM� STIO1 STIO� STOC STPOL STDPX STCCLR � � � � � � � � Bit 7 ~ 6 STM1~STM0: Select STM Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the bits. In the Timer/ Counter Mode, the TM output pin control must be disabled. STIO1~STIO0: Select STM output function...
Page 78 HT66F488/HT66F489 A/D Flash MCU with EEPROM In the PWM Mode, the STIO1 and STIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the STIO1 and STIO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the STIO1 and STIO0 bits are changed when the TM is running. Bit 3 STOC: STM Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In...
Page 79 HT66F488/HT66F489 A/D Flash MCU with EEPROM STMDL Register �a�e D� D� � � � � � � � � D7~D0: STM Counter Low Byte Register bit 7 ~ bit 0 Bit 7 ~ 0 STM 16-bit Counter bit 7 ~ bit 0 STMDH Register �a�e D1� D� � � � � � � � � D15~D8: STM Counter High Byte Register bit 7 ~ bit 0 Bit 7 ~ 0 STM 16-bit Counter bit 15 ~ bit 8 STMAL Register �a�e...
Page 80: Standa�D Type Tm Ope�Ating Modes
HT66F488/HT66F489 A/D Flash MCU with EEPROM Standard Type TM Operating Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the STM1 and STM0 bits in the STMC1 register. Compare Match Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the STCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both STMAF and STMPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the STCCLR bit in the STMC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the STMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when STCCLR is high no STMPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to “0”. As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when a STMAF interrupt request flag is generated after a compare match occurs from Comparator A. The STMPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the STIO1 and STIO0 bits in the STMC1 register. The TM output pin can be selected using the STIO1 and STIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the STON bit changes from low to high, is setup using the STOC bit. Note that if the STIO1 and STIO0 bits are zero then no pin change will take place.
Page 81 HT66F488/HT66F489 A/D Flash MCU with EEPROM Counte� STCCLR = �; STM[1:�] = �� Counte� Value ove�flow CCRP > � Counte� clea�ed �y CCRP value CCRP = � �xFFFF Counte� Resu�e Reset CCRP > � CCRP Pause Stop CCRA Ti�e STO�...
Page 82 HT66F488/HT66F489 A/D Flash MCU with EEPROM STCCLR = 1; STM[1:�] = �� Counte� Value CCRA > � Counte� clea�ed �y CCRA value CCRA = � Counte� ove�flow �xFFFF Resu�e CCRA = � CCRA Counte� Reset Pause Stop CCRP Ti�e STO�...
Page 83 HT66F488/HT66F489 A/D Flash MCU with EEPROM Timer/Counter Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively and also the STIO1 and STIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the STCCLR bit has no effect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle...
Page 84 HT66F488/HT66F489 A/D Flash MCU with EEPROM Counter STDPX=0;STM[1:0]=10 Value Counter Cleared by CCRP Counter reset when STON returns high CCRP Counter Stop If Pause Resume STON bit low CCRA Time STON STPAU STPOL CCRA Int. Flag STMAF CCRP Int. Flag STMPF...
Page 85 HT66F488/HT66F489 A/D Flash MCU with EEPROM Counter STDPX=1;STM[1:0]=10 Value Counter Cleared by CCRA Counter reset when STON returns high CCRA Counter Stop If Pause Resume STON bit low CCRP Time STON STPAU STPOL CCRP Int. Flag STMPF CCRA Int. Flag STMAF...
Page 86 HT66F488/HT66F489 A/D Flash MCU with EEPROM Single Pulse Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively and also the STIO1 and STIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse output leading edge is a low to high transition of the STON bit, which can be implemented using the application program. However in the Single Pulse Mode, the STON bit can also be made to automatically change from low to high using the external STCK pin, which will in turn initiate the Single Pulse output. When the STON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The STON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the STON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. L e a d i n g E d g e T r a i l i n g E d g e...
Page 87 HT66F488/HT66F489 A/D Flash MCU with EEPROM Counte� Value STM [1:�] = 1� ; STIO [1:�] = 11 Counte� stopped �y CCRA Counte� Reset when STO� �etu�ns high CCRA Counte� Stops Resu�e Pause �y softwa�e CCRP Ti�e STO� Auto. set �y STCK pin Softwa�e...
Page 88 HT66F488/HT66F489 A/D Flash MCU with EEPROM However a compare match from Comparator A will also automatically clear the STON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter can only be reset back to zero when the STON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The STCCLR and STDPX bits are not used in this Mode. Capture Input Mode To select this mode bits STM1 and STM0 in the STMC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the STP pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the STIO1 and STIO0 bits in the STMC1 register. The counter is started when the STON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the STP pin the present value in the counter will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what events occur on the STP pin the counter will continue to free run until the STON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The STIO1 and STIO0 bits can select the active trigger edge on the STP pin to be a rising edge, falling edge or both edge types. If the STIO1 and STIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the STP pin, however it must be noted that the counter will continue to run. As the STP pin is pin shared with other functions, care must be taken if the TM is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The STCCLR and STDPX bits are not used in this Mode. Rev. 1.21 �ove��e� �� 2�1�...
Page 89 HT66F488/HT66F489 A/D Flash MCU with EEPROM Counte� Value STM [1:0] = 01 Counte� clea�ed �y CCRP Counte� Counte� Stop Reset CCRP Resu�e Pause Ti�e STO� STPAU Active Active Active edge edge edge STM captu�e pin STP CCRA Int. Flag STMAF CCRP Int.
Page 90: Periodic Type Tm - Ptm0, Ptm1
HT66F488/HT66F489 A/D Flash MCU with EEPROM Periodic Type TM – PTM0, PTM1 The PTM contains five operating modes, which are Compare Match Output, Timer/Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The P-type TM can also be controlled with an external input pin and can drive one output pins. Periodic TM Operation There are two P-type TMs, both are 10-bit wide. At the core is a 10 count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP comparator is 10-bits wide. The only way of changing the value of the 10 counter using the application program, is to clear the counter by changing the PTnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Periodic Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. C C R P...
Page 91 HT66F488/HT66F489 A/D Flash MCU with EEPROM PTM register description Overall operation of the P-type TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA/CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Register Name PTMnC� PTnPAU PTnCK2 PTnCK1 PTnCK� PTnO� — — — PTMnC1 PTnM1 PTnM� PTnIO1 PTnIO� PTnOC PTnPOL PTnCKS PTnCCLR PTMnDL D� D� PTMnDH — — —...
Page 92 HT66F488/HT66F489 A/D Flash MCU with EEPROM PTnON: PTMn Counter On/Off Control Bit 3 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the PTnOC bit, when the PTnON bit changes from low to high. Bit 2~0 Unimplemented, read as“0” PTMnC1 Register �a�e PTnM1 PTnM� PTnIO1 PTnIO� PTnOC PTnPOL PTnCKS PTnCCLR � � � � � � � � Bit 7~6...
Page 93 HT66F488/HT66F489 A/D Flash MCU with EEPROM different from the initial value setup using the PTnOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the PTnON bit from low to high. Bit 3 PTnOC: PTPn Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 PTnPOL: PTPn Output polarity control 0: Non-invert 1: Invert This bit controls the polarity of the PTPn output pin. When the bit is set high the TM...
Page 94 HT66F488/HT66F489 A/D Flash MCU with EEPROM PTMnDL Register �a�e D� D� � � � � � � � � D7~D0: PTMn Counter Low Byte Register Bit 7~Bit 0 Bit 7~0 PTMn 10-bit Counter bit 7 ~ bit 0 PTMnDH Register �a�e — — — — — — D� — — — — — — — —...
Page 95 HT66F488/HT66F489 A/D Flash MCU with EEPROM PTMnRPH Register �a�e — — — — — — D� — — — — — — — — — — — — � � Bit 7~2 Unimplemented, read as“0” D9~D8: PTMn CCRP Register bit 1 ~ bit 0 Bit 1~0 PTMn 10-bit CCRP bit 9 ~ bit 8 Periodic Type TM Operating Modes The P-type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The...
Page 96 HT66F488/HT66F489 A/D Flash MCU with EEPROM Counte� Value Counte� ove�flow PTnCCLR = �; PTnM [1:�] = �� CCRP > � CCRP=� Counte� clea�ed �y CCRP value �x3FF CCRP > � Counte� Resu�e Resta�t CCRP Pause Stop CCRA Ti�e PTnO� PTnPAU PTnPOL CCRP Int.
Page 97 HT66F488/HT66F489 A/D Flash MCU with EEPROM Counte� Value PTnCCLR = 1; PTnM [1:�] = �� CCRA = � CCRA > � Counte� clea�ed �y CCRA value Counte� ove�flow �x3FF CCRA=� Resu�e CCRA Pause Stop Counte� Resta�t CCRP Ti�e PTnO� PTnPAU PTnPOL �o PTMnAF flag...
Page 98 HT66F488/HT66F489 A/D Flash MCU with EEPROM Timer/Counter Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10 respectively and also the PTnIO1 and PTnIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the PTnCCLR bit has no effect as the PWM...
Page 99 HT66F488/HT66F489 A/D Flash MCU with EEPROM Counte� Value PTnM [1:�] = 1� ; PTnIO [1:�]=1� Counte� clea�ed �y CCRP Counte� Reset when PTnO� �etu�ns high CCRP Counte� Stop if Pause Resu�e PTnO� �it low CCRA Ti�e PTnO� PTnPAU PTnPOL CCRA Int. Flag PTMnAF CCRP Int.
Page 100 HT66F488/HT66F489 A/D Flash MCU with EEPROM Single Pulse Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10 respectively and also the PTnIO1 and PTnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse output leading edge is a low to high transition of the PTnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the PTnON bit can also be made to automatically change from low to high using the external PTCKn pin, which will in turn initiate the Single Pulse output. When the PTnON bit transitions to a high level,...
Page 101 HT66F488/HT66F489 A/D Flash MCU with EEPROM Counte� Value PTnM [1:�] = 1� ; PTnIO [1:�] = 11 Counte� stopped �y CCRA Counte� Reset when PTnO� �etu�ns high CCRA Counte� Stops Resu�e Pause �y softwa�e CCRP Ti�e PTnO� Auto. set �y PTCKn pin Softwa�e...
Page 102 HT66F488/HT66F489 A/D Flash MCU with EEPROM Capture Input Mode To select this mode bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the PTPn or PTCKn pin, selected by the PTnCKS bit in the PTMnC1 register. The input pin active edge can be a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the PTnIO1 and PTnIO0 bits in the PTMnC1 register. The counter is started when the PTnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the PTPn or PTCKn pin the present value in the counter will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what events occur on the PTPn or PTCKn pin the counter will continue to free run until the PTnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The PTnIO1 and PTnIO0 bits can select the active trigger edge on the PTPn or PTCKn pin to be a rising edge, falling edge or both edge types. If the PTnIO1 and PTnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the PTPn or PTCKn pin, however it must be noted that the counter will continue to run. As the PTPn pin is pin or PTCKn pin shared with other functions, care must be taken if the PTMn is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The PTnCCLR, PTnOC and PTnPOL bits are not used in this Mode. Rev. 1.21 1�2 �ove��e� �� 2�1�...
Page 103 HT66F488/HT66F489 A/D Flash MCU with EEPROM Counte� Value PTnM[1:0] = 01 Counte� clea�ed �y CCRP Counte� Counte� Stop Reset CCRP Resu�e Pause Ti�e PTnO� PTnPAU Active Active Active edge edge edge PTMn Captu�e Pin PTPn o� PTCKn CCRA Int. Flag PTMnAF CCRP Int.
Page 104: Analog To Digital Converter
HT66F488/HT66F489 A/D Flash MCU with EEPROM Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Overview The device contains a 8-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. The accompanying block diagram shows the overall internal structure of the A/D converter, together with its associated registers. S Y S ¸ 2...
Page 105: A/D Conve�Te� Data Registe�S - Adrl� Adrh
HT66F488/HT66F489 A/D Flash MCU with EEPROM A/D Converter Data Registers – ADRL, ADRH As the device contains an internal 12-bit A/D converter, it requires two data registers to store the converted value. These are a high byte register, known as ADRH, and a low byte register, known as ADRL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the ADRFS bit in the ADCR0 register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any unused bits will be read as zero. ADRH ADRL ADRFS � D11 D1� D�...
Page 106 HT66F488/HT66F489 A/D Flash MCU with EEPROM ADCR0 Register �a�e START EOCB ADOFF ADRFS — ACS2 ACS1 ACS� — � � — � � � START: Start the A/D conversion Bit 7 0→1→0: start 0→1: reset the A/D converter and set EOCB to "1" This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. When the bit is set high the A/D converter will be reset. Bit 6 EOCB: End of A/D conversion flag 0: A/D conversion ended 1: A/D conversion in progress This read only flag is used to indicate when an A/D conversion process has completed. When the conversion process is running the bit will be high. ADOFF : ADC module power on/off control bit Bit 5...
Page 107 HT66F488/HT66F489 A/D Flash MCU with EEPROM ADCR1 Register �a�e ACS4 V125E� — — VREFS ADCK2 ADCK1 ADCK� — — � � — — � � � � ACS4: Selecte Internal V Bit 7 as ADC input Control 0: Disable 1: Enable This bit enables V to be connected to the A/D converter. The V125EN bit must first have been set to enable the bandgap circuit V voltage to be used by the A/D converter. When the ACS4 bit is set high, the bandgap voltage will be routed to the A/ D converter and the other A/D input channels disconnected. V125EN: Internal V Bit 6...
Page 108 HT66F488/HT66F489 A/D Flash MCU with EEPROM ACERL Register �a�e ACE� ACE6 ACE5 ACE4 ACE3 ACE2 ACE1 ACE� ACE7: Define PB1 is A/D input or not Bit 7 0: Not A/D input 1: A/D input, AN7 ACE6: Define PC6 is A/D input or not Bit 6 0: Not A/D input 1: A/D input, AN6 ACE5: Define PC5 is A/D input or not Bit 5 0: Not A/D input 1: A/D input, AN5 ACE4: Define PC4 is A/D input or not Bit 4 0: Not A/D input 1: A/D input, AN4 ACE3: Define PC3 is A/D input or not Bit 3 0: Not A/D input 1: A/D input, AN3 ACE2: Define PC0 is A/D input or not Bit 2 0: Not A/D input...
Page 109 HT66F488/HT66F489 A/D Flash MCU with EEPROM Although the A/D clock source is determined by the system clock f , and by bits ADCK2~ADCK0, there are some limitations on the A/D clock source speed range that can be selected. As the recommended range of permissible A/D clock period, t , is from 0.5μs to 10μs, care must be taken for system clock frequencies. For example, if the system clock operates at a frequency of 4MHz, the ADCK2~ADCK0 bits should not be set to 000B or 110B. Doing so will give A/D clock periods that are less than the minimum A/D clock period or greater than the maximum A/D clock period which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum A/D Clock Period. A/D Clock Period (t ADCK2, ADCK2, ADCK2, ADCK2,...
Page 110: A/D Input Pins
HT66F488/HT66F489 A/D Flash MCU with EEPROM A/D Input Pins All of the A/D analog input pins are pin-shared with the I/O pins on Port C as well as other functions. The ACE7~ACE0 bits in the ACERL registers, determine whether the input pins are setup as A/D converter analog inputs or whether they have other functions. If the ACE7~ACE0 bits for its corresponding pin is set high then the pin will be setup to be an A/D converter input and the original pin functions disabled. In this way, pins can be changed under program control to change their function between A/D inputs and other functions. All pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as A/D inputs. Note that it is not necessary to first setup the A/D pin as an input in the PCC port control register to enable the A/D input as when the ACE7~ACE0 bits enable an A/D input, the status of the port control register will be overridden. The A/D converter has its own reference voltage pins, VREF, however the reference voltage can also be supplied from the power supply pin, a choice which is made through the VREFS bit in the ADCR1 register.
Page 111 HT66F488/HT66F489 A/D Flash MCU with EEPROM • Step 6 The analog to digital conversion process can now be initialised by setting the START bit in the ADCR0 register from low to high and then low again. Note that this bit should have been originally cleared to zero. • Step 7 To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR0 register can be polled. The conversion process is complete when this bit goes low. When this occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur. Note: When checking for the end of the conversion process, if the method of polling the EOCB bit in the ADCR0 register is used, the interrupt enable step above can be omitted. The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16tAD where tAD is equal to the A/D clock period. ADOFF ON2ST...
Page 112: P�Og�A
HT66F488/HT66F489 A/D Flash MCU with EEPROM Programming Considerations During microcontroller operations where the A/D converter is not being used, the A/D internal circuitry can be switched off to reduce power consumption, by setting bit ADOFF high in the ADCR0 register. When this happens, the internal A/D converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. A/D Transfer Function As the device contains a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the AV or V voltage, this gives a single bit analog input value of AV or V divided by 4096. 1 LSB= (AV or V...
Page 113: A/D P�Og�A
HT66F488/HT66F489 A/D Flash MCU with EEPROM A/D Programming Examples The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR0 register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using an EOCB polling method to detect the end of conversion clr ADE ; disable ADC interrupt mov a,03H mov ADCR1,a ; select f /8 as A/D clock and switch off V...
Page 114 HT66F488/HT66F489 A/D Flash MCU with EEPROM Example: using the interrupt method to detect the end of conversion clr ADE ; disable ADC interrupt mov a,03H mov ADCR1,a ; select f /8 as A/D clock and switch off V Clr ADOFF mov a,0Fh ;...
Page 115: Serial Interface Module - Sim
HT66F488/HT66F489 A/D Flash MCU with EEPROM Serial Interface Module – SIM The device contains a Serial Interface Module, which includes both the four-line SPI interface or two-line I C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I C based hardware such as sensors, Flash or EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins and therefore the SIM interface functional pins must first be selected using the corresponding pin-shared function selection bits. As both interface types share the same pins and registers, the choice of whether the SPI or I C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 register. These pull-high resistors of the SIM pin-shared I/O pins are selected using pull-high control registers when the SIM function is enabled and the corresponding pins are used as SIM input pins. SPI Interface The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash Memory or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the device can be either master or slave. Although the SPI interface specification can control multiple slave devices from a single master, but the device provides only one SCS pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pin to select the slave devices. SPI Interface Operation The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data...
Page 116: Spi Registe
HT66F488/HT66F489 A/D Flash MCU with EEPROM S P I M a s t e r S P I S l a v e S C K S C K S D O S D I S D I S D O...
Page 117 HT66F488/HT66F489 A/D Flash MCU with EEPROM SIMD Register �a�e D� D� × × × × × × × × "×": unknown There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2 register also has the name SIMA which is used by the I C function. The SIMC1 register is not used by the SPI function, only by the I C function. Register SIMC0 is used to control the enable/disable function and to set the data transmission clock frequency. Although not connected with the SPI function, the SIMC0 register is also used to control the Peripheral Clock Prescaler. Register SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag etc. SIMC0 Register �a�e SIM2 SIM1 SIM� — SIMDB�C1 SIMDB�C� SIME� SPIICF —...
Page 118 HT66F488/HT66F489 A/D Flash MCU with EEPROM SPIICF: SPI Incompleted Flag Bit 0 0: SPI incompleted is not occurred 1: SPI incompleted is occurred The SPIICF bit is determined by SCS pin. When SCS pin is set to “1”, it will clear the SPI counter. Meanwhile, the interrupt is occurred, if slave device didn’t complete data received, then the incompleted flag, SPIICF, is set to “1”. SIMC2 Register �a�e D� CKPOLB CKEG CSE� WCOL � � � � � � � � Bit 7 ~ 6 Undefined bits These bits can be read or written by user software program. Bit 5 CKPOLB: Determines the base condition of the clock line 0: The SCK line will be high when the clock is inactive 1: The SCK line will be low when the clock is inactive The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. Bit 4...
Page 119: Spi Co
HT66F488/HT66F489 A/D Flash MCU with EEPROM TRF: SPI Transmit/Receive Complete flag Bit 0 0: Data is being transferred 1: SPI data transmission is completed The TRF bit is the Transmit/Receive Complete flag and is set “1” automatically when an SPI data transmission is completed, but must set to “0” by the application program. It can be used to generate an interrupt. SPI Communication After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMD register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register. The master should output a SCS signal to enable the slave device before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. The SPI will continue to function even in the IDLE Mode.
Page 120 HT66F488/HT66F489 A/D Flash MCU with EEPROM S C S S C K ( C K P O L B = 1 ) S C K ( C K P O L B = 0 ) S D O D 7 / D 0...
Page 121: I 2 C Inte�Face
HT66F488/HT66F489 A/D Flash MCU with EEPROM C Interface The I C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. V D D S D A S C L D e v i c e...
Page 122: I 2 C Registe
HT66F488/HT66F489 A/D Flash MCU with EEPROM C Register There are four control registers associated with the I C bus, SIMC0, SIMC1, SIMA and SIMTOC and one data register, SIMD. The SIMD register, which is shown in the above SPI section, is used to store the data being transmitted and received on the I C bus. Before the microcontroller writes data to the I C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I C bus, the microcontroller can read it from the SIMD register. Any transmission or reception of data from the I C bus must be made via the SIMD register. Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN and bits SIM2~SIM0 in register SIMC0 are used by the I C interface. The SIMTOC register is used for I C time-out control function. Register Name SIMC� SIM2 SIM1 SIM� — SIMDEB1 SIMDEB� SIME� SPIICF SIMC1 HAAS TXAK RCI� RXAK SIMD D�...
Page 123 HT66F488/HT66F489 A/D Flash MCU with EEPROM SIMEN: SIM Control Bit 1 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I C function and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 SPIICF: SPI Incompleted Flag 0: SPI incompleted is not occurred 1: SPI incompleted is occurred The SPIICF bit is determined by SCS pin. When SCS pin is set to “1”, it will clear the SPI counter. Meanwhile, the interrupt is occurred, if slave device didn’t complete data received, then the incompleted flag, SPIICF, is set to”1”. SIMC1 Register �a�e HAAS TXAK IAMWU RXAK �...
Page 124 HT66F488/HT66F489 A/D Flash MCU with EEPROM TXAK: I Bit 3 C Bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave do not send acknowledge flag The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9 clock from the slave device. The slave device must always set TXAK bit to “0” before further data is received. Bit 2 SRW: I C Slave Read/Write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SRW flag is the I C Slave Read/Write flag. This flag determines whether the master device wishes to transmit or receive data from the I C bus. When the...
Page 125 HT66F488/HT66F489 A/D Flash MCU with EEPROM SIMD Register �a�e D� D� × × × × × × × × "×": unknown SIMA Register �a�e A� — — � � � � � � � — bit 7 ~ 1 A6~ A0: I C slave address A6~ A0 is the I C slave address bit 6 ~ bit 0.
Page 126: I 2 C Bus Co
HT66F488/HT66F489 A/D Flash MCU with EEPROM C Bus Communication Communication on the I C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the SIMC1 register will be set and an I C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the HAAS bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8 bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I C bus, the microcontroller must initialize the bus, the following are steps to achieve this: Step 1 Set the SIM2~SIM0 and SIMEN bits in the SIMC0 register to “110” and “1” to enable the I C bus. Step 2 Write the slave address of the device to the I C bus address register SIMA. Step 3 Set the SIME bit of the interrupt control register to enable the SIM interrupt. S t a r t...
Page 127 HT66F488/HT66F489 A/D Flash MCU with EEPROM C Bus Start Signal The START signal can only be generated by the master device connected to the I C bus and not by the slave device. This START signal will be detected by all devices connected to the I C bus. When detected, this indicates that the I C bus is busy and therefore the HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. Slave Address The transmission of a START signal by the master will be detected by all devices on the I C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I C bus interrupt signal will be generated. The next bit following the address, which is the 8 bit, defines the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will then transmit an acknowledge bit, which is a low level, as the 9 bit. The slave device will also set the status flag HAAS when the addresses match. As an I C bus interrupt can come from two sources, when the program enters the interrupt subroutine, the HAAS bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. When a slave address is...
Page 128: I 2 C Bus Data And Acknowledge Signal
HT66F488/HT66F489 A/D Flash MCU with EEPROM C Bus Data and Acknowledge Signal The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level “0”, before it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I C Bus. The corresponding data will be stored in the SIMD register. If setup as a transmitter, the slave device must first write the data to be transmitted into the SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD register. When the slave receiver receives the data byte, it must generate an acknowledge bit, known as TXAK, on the 9 clock. The slave device, which is setup as a transmitter will check the RXAK bit in the SIMC1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master. S t a r t S l a v e A d d r e s s...
Page 129 HT66F488/HT66F489 A/D Flash MCU with EEPROM S t a r t Y e s H A A S = 1 Y e s Y e s H T X = 1 S R W = 1 R e a d f r o m...
Page 130 HT66F488/HT66F489 A/D Flash MCU with EEPROM S t a r t S l a v e A d d r e s s S R W A C K S C L S D A I C t i m e - o u t...
Page 131: Uart Module Serial Interface
HT66F488/HT66F489 A/D Flash MCU with EEPROM UART Module Serial Interface The device contains an integrated full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. The UART function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. The integrated UART function contains the following features: • Full-duplex, Universal Asynchronous Receiver and Transmitter (UART) communication • 8 or 9 bits character length • Even, odd or no parity options • One or two stop bits...
Page 132: Uart Data T�Ansfe� Sche�E
HT66F488/HT66F489 A/D Flash MCU with EEPROM UART Data Transfer Scheme The block diagram shows the overall data transfer structure arrangement for the UART. The actual data to be transmitted from the MCU is first transferred to the TXR register by the application program. The data will then be transferred to the Transmit Shift Register from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only the TXR register is mapped onto the MCU Data Memory, the Transmit Shift Register is not mapped and is therefore inaccessible to the application program. Data to be received by the UART is accepted on the external RX pin, from where it is shifted in, LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the shift register is full, the data will then be transferred from the shift register to the internal RXR register, where it is buffered and can be manipulated by the application program. Only the RXR register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is therefore inaccessible to the application program. It should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate TXR and RXR registers, only exists as a single shared register in the Data Memory. This shared register known as the TXR/RXR register is used for both data transmission and data reception. T�ans�itte� Shift Registe� Receive� Shift Registe� TX Pin RX Pin ………………………… ………………………… Baud Rate RXR Registe�...
Page 133 HT66F488/HT66F489 A/D Flash MCU with EEPROM USR register The USR register is the status register for the UART, which can be read by the program to determine the present status of the UART. All flags within the USR register are read only. Further explanation on each of the flags is given below: �a�e PERR �F FERR OERR RIDLE RXIF TIDLE TXIF � � � � � PERR: Parity error flag Bit 7 0: No parity error is detected 1: Parity error is detected The PERR flag is the parity error flag. When this read only flag is “0”, it indicates a parity error has not been detected. When the flag is “1”, it indicates that the parity of the received word is incorrect. This error flag is applicable only if Parity mode (odd or even) is selected. The flag can also be cleared by a software sequence which involves a read to the status register USR followed by an access to the RXR data register. Bit 6 NF: Noise flag 0: No noise is detected 1: Noise is detected The NF flag is the noise flag. When this read only flag is "0", it indicates no noise condition. When the flag is "1", it indicates that the UART has detected noise on the receiver input. The NF flag is set during the same cycle as the RXIF flag but will not...
Page 134 HT66F488/HT66F489 A/D Flash MCU with EEPROM RXIF: Receive RXR data register status Bit 2 0: RXR data register is empty 1: RXR data register has available data The RXIF flag is the receive data register status flag. When this read only flag is “0”, it indicates that the RXR read data register is empty. When the flag is “1”, it indicates that the RXR read data register contains new data. When the contents of the shift register are transferred to the RXR register, an interrupt is generated if RIE=1 in the UCR2 register. If one or more errors are detected in the received word, the appropriate receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The RXIF flag is cleared when the USR register is read with RXIF set, followed by a read from the RXR register, and if the RXR register has no data available. Bit 1 TIDLE: Transmission idle 0: Data transmission is in progress (data being transmitted) 1: No data transmission is in progress (transmitter is idle) The TIDLE flag is known as the transmission complete flag. When this read only flag is “0”, it indicates that a transmission is in progress. This flag will be set to “1” when the TXIF flag is “1” and when there is no transmit data or break character being transmitted. When TIDLE is equal to “1”, the TX pin becomes idle with the pin state in logic high condition. The TIDLE flag is cleared by reading the USR register with TIDLE set and then writing to the TXR register. The flag is not generated when a data character or a break is queued and ready to be sent. Bit 0 TXIF: Transmit TXR data register status 0: Character is not transferred to the transmit shift register 1: Character has transferred to the transmit shift register (TXR data register is empty) The TXIF flag is the transmit data register empty flag. When this read only flag is “0”,...
Page 135 HT66F488/HT66F489 A/D Flash MCU with EEPROM When the UART is disabled, it will empty the buffer so any character remaining in the buffer will be discarded. In addition, the value of the baud rate counter will be reset. If the UART is disabled, all error and status flags will be reset. Also the TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF bits will be cleared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2 and BRG registers will remain unaffected. If the UART is active and the UARTEN bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. When the UART is re-enabled, it will restart in the same configuration. Bit 6 BNO: Number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer This bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. When this bit is equal to “1”, a 9-bit data length format will be selected. If the bit is equal to “0”, then an 8-bit data length format will be selected. If 9-bit data length format is selected, then bits RX8 and TX8 will be used to store the 9 bit of the received and transmitted data respectively. Bit 5 PREN: Parity function enable control 0: Parity function is disabled 1: Parity function is enabled This is the parity enable bit. When this bit is equal to “1”, the parity function will be enabled. If the bit is equal to “0”, then the parity function will be disabled. Replace the most significant bit position with a parity bit. PRT: Parity type selection bit Bit 4 0: Even parity for parity generator 1: Odd parity for parity generator This bit is the parity type selection bit. When this bit is equal to “1”, odd parity type will be selected. If the bit is equal to “0”, then even parity type will be selected. STOPS: Number of Stop bits selection Bit 3 0: One stop bit format is used 1: Two stop bits format is used This bit determines if one or two stop bits are to be used. When this bit is equal to “1”,...
Page 136 HT66F488/HT66F489 A/D Flash MCU with EEPROM UCR2 register The UCR2 register is the second of the two UART control registers and serves several purposes. One of its main functions is to control the basic enable/disable operation of the UART Transmitter and Receiver as well as enabling the various UART interrupt sources. The register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. Further explanation on each of the bits is given below: �a�e TXE� RXE� BRGH ADDE� WAKE TIIE TEIE � � � � � � � � Bit 7 TXEN: UART Transmitter enabled control 0: UART transmitter is disabled 1: UART transmitter is enabled The bit named TXEN is the Transmitter Enable Bit. When this bit is equal to “0”, the transmitter will be disabled with any pending data transmissions being aborted. In addition the buffers will be reset. In this situation the TX pin will be used as an I/O or other pin-shared functional pin. If the TXEN bit is equal to “1” and the UARTEN bit is also equal to “1”, the transmitter will be enabled and the TX pin will be controlled by the UART. Clearing...
Page 137 HT66F488/HT66F489 A/D Flash MCU with EEPROM WAKE: RX pin falling edge wake-up function enable control Bit 3 0: RX pin wake-up function is disabled 1: RX pin wake-up function is enabled This bit enables or disables the receiver wake-up function. If this bit is equal to “1” and the MCU is in IDLE or SLEEP mode, a falling edge on the RX input pin will wake-up the device. Please reference the UART RX pin wake-up functions in different operating mode for the detail. If this bit is equal to “0” and the MCU is in IDLE or SLEEP mode, any edge transitions on the RX pin will not wake-up the device. Bit 2 RIE: Receiver interrupt enable control 0: Receiver related interrupt is disabled 1: Receiver related interrupt is enabled This bit enables or disables the receiver interrupt. If this bit is equal to “1” and when the receiver overrun flag OERR or receive data available flag RXIF is set, the UART interrupt request flag will be set. If this bit is equal to “0”, the UART interrupt request flag will not be influenced by the condition of the OERR or RXIF flags. Bit 1 TIIE: Transmitter Idle interrupt enable control 0: Transmitter idle interrupt is disabled 1: Transmitter idle interrupt is enabled This bit enables or disables the transmitter idle interrupt. If this bit is equal to “1” and when the transmitter idle flag TIDLE is set, due to a transmitter idle condition, the UART interrupt request flag will be set. If this bit is equal to “0”, the UART interrupt request flag will not be influenced by the condition of the TIDLE flag. Bit 0 TEIE: Transmitter Empty interrupt enable control 0: Transmitter empty interrupt is disabled 1: Transmitter empty interrupt is enabled This bit enables or disables the transmitter empty interrupt. If this bit is equal to “1” and when the transmitter empty flag TXIF is set, due to a transmitter empty condition, the UART interrupt request flag will be set. If this bit is equal to “0”, the UART interrupt request flag will not be influenced by the condition of the TXIF flag.
Page 138: Baud Rate Gene�Ato
HT66F488/HT66F489 A/D Flash MCU with EEPROM Baud Rate Generator To setup the speed of the serial data communication, the UART function contains its own dedicated baud rate generator. The baud rate is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. The first of these is the value placed in the baud rate register BRG and the second is the value of the BRGH bit with the control register UCR2. The BRGH bit decides if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. The value N in the BRG register which is used in the following baud rate calculation formula determines the division factor. Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255. UCR2 BRGH Bit Baud Rate (BR) /[64 (�+1)] /[16 (�+1)] By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register, the required baud rate can be setup. Note that because the actual baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error associated between the actual and requested value. The following example shows how the BRG register value N and the error value can be calculated. Calculating the register and error values For a clock frequency of 4MHz, and with BRGH set to “0” determine the BRG register value N, the actual baud rate and the error value for a desired baud rate of 4800.
Page 139: Uart Setup And Cont�Ol
HT66F488/HT66F489 A/D Flash MCU with EEPROM Baud Rates for BRGH=1 Baud Rate = 16 MHz = 20 MHz K/BPS Kbaud Error (%) Kbaud Error (%) �.3 — — — — — — — — — — — — — —...
Page 140 HT66F488/HT66F489 A/D Flash MCU with EEPROM Data, parity and stop bit selection The format of the data to be transferred is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. These factors are determined by the setup of various bits within the UCR1 register. The BNO bit controls the number of data bits which can be set to either 8 or 9, the PRT bit controls the choice of odd or even parity, the PREN bit controls the parity on/off function and the STOPS bit decides whether one or two stop bits are to be used. The following table shows various formats for data transmission. The address bit identifies the frame as an address character. The number of stop bits, which can be either one or two, is independent of the data length. Start Bit Data Bits Address Bits Parity Bits Stop Bit Example of 8-bit Data Formats � � � � �...
Page 141 HT66F488/HT66F489 A/D Flash MCU with EEPROM Transmitting data When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with the least significant bit first. In the transmit mode, the TXR register forms a buffer between the internal bus and the transmitter shift register. It should be noted that if 9-bit data format has been selected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a data transfer can be summarized as follows: • Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits. • Setup the BRG register to select the desired baud rate. • Set the TXEN bit to ensure that the TX pin is used as a UART transmitter pin. • Access the USR register and write the data that is to be transmitted into the TXR register. Note that this step will clear the TXIF bit. • This sequence of events can now be repeated to send additional data. It should be noted that when TXIF=0, data will be inhibited from being written to the TXR register. Clearing the TXIF flag is always achieved using the following software sequence: 1. A USR register access 2. A TXR register write execution The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is empty and that other data can now be written into the TXR register without overwriting the previous data. If the TEIE bit is set then the TXIF flag will generate an interrupt. During a data transmission, a write instruction to the TXR register will place the data into the TXR register, which will be copied to the shift register at the end of the present transmission. When there is no data transmission in progress, a write instruction to the TXR register will place the data directly into the shift register, resulting in the commencement of data transmission, and the TXIF bit being immediately set. When a frame transmission is complete, which happens after stop bits are sent or after the break frame, the TIDLE bit will be set. To clear the TIDLE bit the following software sequence is used: 1. A USR register access 2. A TXR register write execution...
Page 142 HT66F488/HT66F489 A/D Flash MCU with EEPROM UART receiver The UART is capable of receiving word lengths of either 8 or 9 bits. If the BNO bit is set, the word length will be set to 9 bits with the MSB being stored in the RX8 bit of the UCR1 register. At the receiver core lies the Receive Serial Shift Register, commonly known as the RSR. The data which is received on the RX external input pin, is sent to the data recovery block. The data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the receive data register, if the register is empty. The data which is received on the external RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin. It should be noted that the RSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. Receiving data When the UART receiver is receiving data, the data is serially shifted in on the external RX input pin, LSB first. In the read mode, the RXR register forms a buffer between the internal bus and the receiver shift register. The RXR register is a two byte deep FIFO data buffer, where two bytes can be held in the FIFO while a third byte can continue to be received. Note that the application program must ensure that the data is read from RXR before the third byte has been completely shifted in, otherwise this third byte will be discarded and an overrun error OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized as follows:...
Page 143: Managing �Eceive� E
HT66F488/HT66F489 A/D Flash MCU with EEPROM Receive break Any break character received by the UART will be managed as a framing error. The receiver will count and expect a certain number of bit times as specified by the values programmed into the BNO and STOPS bits. If the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by BNO and STOPS. The RXIF bit is set, FERR is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the RIDLE bit is set. If a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a valid stop bit before looking for the next start bit. The receiver will not make the assumption that the break condition on the line is the next start bit. A break is regarded as a character that contains only zeros with the FERR flag set. The break character will be loaded into the buffer and no further data will be received until stop bits are received. It should be noted that the RIDLE read only flag will go high when the stop bits have not yet been received. The reception of a break character on the UART registers will result in the following: • The framing error flag, FERR, will be set. • The receive data register, RXR, will be cleared. • The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set. Idle status When the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of the next start bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition. Receiver interrupt The read only receive interrupt flag RXIF in the USR register is set by an edge generated by the receiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift Register, RSR, to the Receive Data Register, RXR. An overrun error can also generate an interrupt if RIE=1. Managing receiver errors Several types of reception errors can occur within the UART module, the following section describes the various types and how they are managed by the UART.
Page 144: Uart Module Inte
HT66F488/HT66F489 A/D Flash MCU with EEPROM Noise Error – NF Flag Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is detected within a frame the following will occur: • The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit. • Data will be transferred from the Shift register to the RXR register. • No interrupt will be generated. However this bit rises at the same time as the RXIF bit which itself generates an interrupt. Note that the NF flag is reset by a USR register read operation followed by an RXR register read operation. Framing Error – FERR Flag The read only framing error flag, FERR, in the USR register, is set if a zero is detected instead of stop bits. If two stop bits are selected, both stop bits must be high, otherwise the FERR flag will be...
Page 145: Add�Ess Detect �Ode
HT66F488/HT66F489 A/D Flash MCU with EEPROM USR Register UCR2 Register Transmitter Empty TEIE Flag TXIF UART Interrupt Transmitter Idle TIIE Request Flag To MCU Interrupt Flag TIDLE UARF Controller Receiver Overrun Flag OERR Receiver Data ADDEN Available RXIF RX Pin...
Page 146: Uart Module Powe� Down And Wake-Up
HT66F488/HT66F489 A/D Flash MCU with EEPROM UART Module Power Down and Wake-up When the f is off, the UART will cease to function. All clock sources to the module are shutdown. If the f is off while a transmission is still in progress, then the transmission will be paused until the UART clock source derived from the microcontroller is activated. In a similar way, if the MCU enters the Power Down Mode while receiving data, then the reception of data will likewise be paused. When the MCU enters the Power Down Mode, note that the USR, UCR1, UCR2, transmit and receive registers, as well as the BRG register will not be affected. It is recommended to make sure first that the UART data transmission or reception has been finished before the microcontroller enters the Power Down mode. The UART function contains a receiver RX pin wake-up function, which is enabled or disabled by the WAKE bit in the UCR2 register. If this bit, along with the UART enable bit, UARTEN, the receiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set before the MCU enters the Power Down Mode, then a falling edge on the RX pin will wake up the MCU from the Power Down Mode. Note that as it takes certain system clock cycles after a wake-up, before normal microcontroller operation resumes, any data received during this time on the RX pin will be ignored.
Page 147 HT66F488/HT66F489 A/D Flash MCU with EEPROM Function Enable Bit Request Flag Notes Glo�al — — I�Tn Pin I�TnE I�TnF n=�~5 UART UARE UARF — Ti�e Base TBnE TBnF n=� o� 1 A/D Conve�te� — Multi-function MFnE MFnF n=�~2 EEPROM —...
Page 148 HT66F488/HT66F489 A/D Flash MCU with EEPROM INT0S1, INT0S0: Defines INT0 interrupt active edge Bit 1 ~ 0 00: Disabled Interrupt 01: Rising Edge Interrupt 10: Falling Edge Interrupt 11: Dual Edge Interrupt INTEG1 Register �a�e — — — — I�T5S1 I�T5S� I�T4S1 I�T4S� — — — — — — — — � � � � Bit 7 ~ 4 Unimplemented, read as "0" INT5S1, INT5S0: Defines INT5 interrupt active edge...
Page 149 HT66F488/HT66F489 A/D Flash MCU with EEPROM INTC1 Register �a�e UARF I�T5F I�T4F I�T3F UARE I�T5E I�T4E I�T3E � � � � � � � � UARF: UART Interrupt Request Flag Bit 7 0: No request 1: Interrupt request INT5F: INT5 Interrupt Request Flag Bit 6 0: No request 1: Interrupt request INT4F: INT4 Interrupt Request Flag Bit 5 0: No request 1: Interrupt request INT3F: INT3 Interrupt Request Flag Bit 4 0: No request...
Page 150 HT66F488/HT66F489 A/D Flash MCU with EEPROM INTC2 Register �a�e MF2F MF1F MF�F MF2E MF1E MF�E � � � � � � � � ADF: A/D Converter Interrupt Request Flag Bit 7 0: No request 1: Interrupt request MF2F: Multi-function 2 Interrupt Request Flag Bit 6 0: No request 1: Interrupt request MF1F: Multi-function 1 Interrupt Request Flag Bit 5 0: No request 1: Interrupt request MF0F: Multi-function 0 Interrupt Request Flag Bit 4 0: No request 1: Interrupt request ADE: A/D Converter Interrupt Control...
Page 151 HT66F488/HT66F489 A/D Flash MCU with EEPROM INTC3 Register �a�e SIMF TB1F TB�F SIME TB1E TB�E � � � � � � � � SIMF: Serial Interface Module Interrupt Request Flag Bit 7 0: No request 1: Interrupt request DEF: Data EEPROM Interrupt Request Flag Bit 6 0: No request 1: Interrupt request TB1F : Time Base 1 Interrupt Request Flag Bit 5 0: No request 1: Interrupt request TB0F: Time Base 0 Interrupt Request Flag Bit 4 0: No request 1: Interrupt request...
Page 152 HT66F488/HT66F489 A/D Flash MCU with EEPROM MFI0 Register �a�e — — CTMAF CTMPF — — CTMAE CTMPE — — — — — — � � — — � � Bit 7 ~ 6 Unimplemented, read as "0" CTMAF: CTM Comparator A match interrupt request flag Bit 5 0: No request 1: Interrupt request CTMPF: CTM Comparator P match interrupt request flag Bit 4 0: No request 1: Interrupt request Bit 3 ~ 2 Unimplemented, read as "0"...
Page 153 HT66F488/HT66F489 A/D Flash MCU with EEPROM MFI2 Register �a�e PTM1AF PTM1PF PTM�AF PTM�PF PTM1AE PTM1PE PTM�AE PTM�PE � � � � � � � � PTM1AF: PTM1 Comparator A match interrupt request flag Bit 7 0: No request 1: Interrupt request PTM1PF: PTM1 Comparator P match interrupt request flag Bit 6 0: No request 1: Interrupt request PTM0AF: PTM0 Comparator A match interrupt request flag Bit 5 0: No request 1: Interrupt request PTM0PF: PTM0 Comparator P match interrupt request flag Bit 4 0: No request...
Page 154: Inte
HT66F488/HT66F489 A/D Flash MCU with EEPROM Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P or Comparator A match or A/D conversion completion etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a “JMP” which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a “RETI”, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt...
Page 155: Exte�Nal Inte
HT66F488/HT66F489 A/D Flash MCU with EEPROM EMI auto disabled in ISR Interrupt Request Enable Master Priority Vector Name Flags Bits Enable High Legend INT0 Pin INT0F INT0E Request Flag, no auto reset in ISR INT1 Pin INT1F INT1E Request Flag, auto reset in ISR...
Page 156: Multi-Function Inte
HT66F488/HT66F489 A/D Flash MCU with EEPROM Multi-function Interrupt Within this device there are up to three Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM Interrupts and LVD interrupt. A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags, MF0F~MF2F are set. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related Multi- Function request flag will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts, namely the TM Interrupts and LVD interrupt, will not be automatically reset and must be manually reset by the application program. A/D Converter Interrupt The device contains an A/D converter which has its own independent interrupt. The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/D Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF, is set, which occurs when the A/D conversion process finishes. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the A/D Converter Interrupt vector, will take place. When the interrupt is serviced, the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Time Base Interrupts The function of the Time Base Interrupts is to provide regular time signal in the form of an internal interrupt. They are controlled by the overflow signals from their respective timer functions. When these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the...
Page 157 HT66F488/HT66F489 A/D Flash MCU with EEPROM TBC Register �a�e TBO� TBCK TB11 TB1� LXTLP TB�2 TB�1 TB�� TBON: TB0 and TB1 Control bit Bit 7 0: Disable 1: Enable TBCK: Select f Bit 6 Clock 0: f 1: f TB11 ~ TB10: Select Time Base 1 Time-out Period Bit 5 ~ 4 00: 4096/f 01: 8192/f 10: 16384/f 11: 32768/f LXTLP: LXT Low Power Mode control Bit 3 0: Disable (Quick Start Mode)
Page 158: Eeprom Inte
HT66F488/HT66F489 A/D Flash MCU with EEPROM EEPROM Interrupt An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit, DEE, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective EEPROM Interrupt vector, will take place. When the EEPROM Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, and the EEPROM interrupt request flag, DEF, will also be automatically cleared. TM Interrupts The Compact, Standard and Periodic Type TMs each has two interrupts. All of the TM interrupts are contained within the Multi-function Interrupts. For each of the Compact, Standard and Periodic Type TMs there are two interrupt request flags xTMnPF and xTMnAF and two enable bits xTMnPE and xTMnAE. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P or comparator A match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the respective TM Interrupt enable bit, and associated Multi-function interrupt enable bit, MFnF, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant TM Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. LVD Interrupt The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program...
Page 159: Inte
HT66F488/HT66F489 A/D Flash MCU with EEPROM Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pin, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program.
Page 160: Software Lcd Driver
HT66F488/HT66F489 A/D Flash MCU with EEPROM Software LCD Driver The devices have the capability of driving external LCD panels. The common pins for LCD driving, SCOM0~SCOM5, and segment pins, SSEG0~SSEG29, are pin shared with certain pin on the I/O ports. The LCD signals (COM and SEG) are generated using the application program. LCD operation An external LCD panel can be driven using this device by configuring the I/O pins as common pins and configuring the I/O pins as segment pins. The LCD driver function is controlled using the SLCDC0~SLCDC4 registers which in addition to controlling the overall on/off function, LCD bias current setup function also controls the pin function selection. This enables the LCD COM and SEG driver to generate the necessary V , (1/3)V , (2/3)V voltage and V levels for LCD 1/3 bias operation. The LCDEN bit in the SLCDC0 register is the overall master control for the LCD driver. The LCD SCOMn pin is selected to be used for LCD driving by the corresponding pin-shared function selection bits. Note that the Port Control register does not need to first setup the pins as outputs to...
Page 161 HT66F488/HT66F489 A/D Flash MCU with EEPROM SLCDC0 Register �a�e FRAME ISEL1 ISEL� LCDE� COM3E� COM2E� COM1E� COM�E� � � � � � � � � FRAME: Output frame0 or frame1 Bit 7 0: Frame 0 1: Frame 1 ISEL1~ISEL0: LCD bias current selection (V Bit 6~5 =5V) 00: 8.3μA 01: 16.7μA 10: 50μA 11: 100μA LCDEN: SCOM and SSEG module on/off control Bit 4 0: Off 1: On...
Page 162 HT66F488/HT66F489 A/D Flash MCU with EEPROM SLCDC1 Register �a�e COM5E� COM4E� COMSEGS5 COMSEGS4 COMSEGS3 COMSEGS2 COMSEGS1 COMSEGS� � � � � � � � � COM5EN: LCD or other function selection Bit 7 0: Other function 1: SCOM5/SSEG5 COM4EN: LCD or other function selection Bit 6 0: Other function 1: SCOM4/SSEG4 COMSEGS5: SCOM5 or SSEG 5 selection Bit 5 0: SCOM5 1: SSEG5 COMSEGS4: SCOM4 or SSEG 4 selection Bit 4 0: SCOM4...
Page 163 HT66F488/HT66F489 A/D Flash MCU with EEPROM SLCDC2 Register �a�e SEG13E� SEG12E� SEG11E� SEG1�E� SEG�E� SEG8E� SEG�E� SEG6E� � � � � � � � � SEG13EN: SSEG13 function control Bit 7 0: Disable 1: Enable SEG12EN: SSEG12 function control Bit 6 0: Disable 1: Enable SEG11EN: SSEG11 function control Bit 5 0: Disable 1: Enable SEG10EN: SSEG10 function control Bit 4 0: Disable...
Page 164 HT66F488/HT66F489 A/D Flash MCU with EEPROM SLCDC3 Register �a�e SEG21E� SEG2�E� SEG1�E� SEG18E� SEG1�E� SEG16E� SEG15E� SEG14E� � � � � � � � � SEG21EN: SSEG21 function control Bit 7 0: Disable 1: Enable SEG20EN: SSEG20 function control Bit 6 0: Disable 1: Enable SEG19EN: SSEG19 function control Bit 5 0: Disable 1: Enable SEG18EN: SSEG18 function control Bit 4 0: Disable...
Page 165: Lcd Wavefo
HT66F488/HT66F489 A/D Flash MCU with EEPROM SLCDC4 Register �a�e SEG2�E� SEG28E� SEG2�E� SEG26E� SEG25E� SEG24E� SEG23E� SEG22E� � � � � � � � � SEG29EN: SSEG29 function control Bit 7 0: Disable 1: Enable SEG28EN: SSEG28 function control Bit 6 0: Disable 1: Enable SEG27EN: SSEG27 function control Bit 5 0: Disable 1: Enable SEG26EN: SSEG26 function control Bit 4 0: Disable...
Page 166 HT66F488/HT66F489 A/D Flash MCU with EEPROM f r a m e 0 f r a m e 0 f r a m e 1 V D D 2 / 3 V D D C O M 0 1 / 3 V D D...
Page 167: Low Voltage Detector - Lvd
HT66F488/HT66F489 A/D Flash MCU with EEPROM Low Voltage Detector – LVD Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, V , and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be determined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the V voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register �a�e — — LVDO LVDE� — VLVD2 VLVD1 VLVD�...
Page 168: Lvd Ope�Ation
HT66F488/HT66F489 A/D Flash MCU with EEPROM LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, V , with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V. When the power supply voltage, V , falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay t should be allowed for the circuitry to stabilise before reading the LVDS LVDO bit. Note also that as the V voltage may rise and fall rather slowly, at the voltage nears that of V , there may be multiple bit LVDO transitions. V D D L V D L V D E N L V D O L V D S...
Page 169: Configuration Option
HT66F488/HT66F489 A/D Flash MCU with EEPROM Configuration Option Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. All options must be defined for proper system function, the details of which are shown in the table. Options Oscillator Option High Speed/Low Speed Syste� Oscillato� Selection – f HIRC+LIRC HIRC+LXT HXT+LIRC Application Circuit V D D 0 . 1 m F P A 0 ~ P A 7...
Page 170: Instruction Set
HT66F488/HT66F489 A/D Flash MCU with EEPROM Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be “CLR PCL” or “MOV PCL, A”. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of several kinds of MOV instructions, data can be transferred from registers...
Page 171 HT66F488/HT66F489 A/D Flash MCU with EEPROM Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such...
Page 172 HT66F488/HT66F489 A/D Flash MCU with EEPROM Instruction Set Summary The instructions related to the data memory access in the following table can be used when the desired data memory is located in Data Memory sector 0. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Arithmetic ADD A�[�] Add Data Me�o�y to ACC Z� C� AC� OV� SC ADDM A�[�] Add ACC to Data Me�o�y �ote...
Page 173 HT66F488/HT66F489 A/D Flash MCU with EEPROM Mnemonic Description Cycles Flag Affected Data Move MOV A�[�] Move Data Me�o�y to ACC �one MOV [�]�A Move ACC to Data Me�o�y �ote �one MOV A�x Move i��ediate data to ACC �one Bit Operation CLR [�].i...
Page 174 HT66F488/HT66F489 A/D Flash MCU with EEPROM Extended Instruction Set The extended instructions are used to support the full range address access for the data memory. When the accessed data memory is located in any data memory sections except sector 0, the extended instruction can be used to access the data memory instead of using the indirect addressing access to improve the CPU firmware performance. Mnemonic Description Cycles Flag Affected Arithmetic LADD A�[�] Add Data Me�o�y to ACC Z�...
Page 175 HT66F488/HT66F489 A/D Flash MCU with EEPROM Mnemonic Description Cycles Flag Affected Branch LSZ [�] Skip if Data Me�o�y is ze�o �ote �one LSZA [�] Skip if Data Me�o�y is ze�o with data �ove�ent to ACC �ote �one LS�Z [�] Skip if Data Me�o�y is not ze�o �ote...
Page 176 HT66F488/HT66F489 A/D Flash MCU with EEPROM Instruction Definition Add Data Memory to ACC with Carry ADC A,[m] Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] + C Affected flag(s) OV, Z, AC, C, SC ADCM A,[m] Add ACC to Data Memory with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. Operation [m] ← ACC + [m] + C Affected flag(s) OV, Z, AC, C, SC ADD A,[m] Add Data Memory to ACC Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] Affected flag(s) OV, Z, AC, C, SC ADD A,x...
Page 177 HT66F488/HT66F489 A/D Flash MCU with EEPROM CALL addr Subroutine call Description Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Operation Stack ← Program Counter + 1 Program Counter ← addr Affected flag(s) None CLR [m] Clear Data Memory Description Each bit of the specified Data Memory is cleared to 0. Operation [m] ← 00H Affected flag(s) None CLR [m].i Clear bit of Data Memory Description Bit i of the specified Data Memory is cleared to 0. Operation [m].i ← 0 Affected flag(s) None CLR WDT Clear Watchdog Timer Description The TO, PDF flags and the WDT are all cleared.
Page 178 HT66F488/HT66F489 A/D Flash MCU with EEPROM DEC [m] Decrement Data Memory Description Data in the specified Data Memory is decremented by 1. Operation [m] ← [m] − 1 Affected flag(s) DECA [m] Decrement Data Memory with result in ACC Description Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. Operation ACC ← [m] − 1 Affected flag(s) Enter power down mode HALT Description This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO ← 0 PDF ← 1 Affected flag(s) TO, PDF INC [m] Increment Data Memory Description Data in the specified Data Memory is incremented by 1. Operation [m] ← [m] + 1...
Page 179 HT66F488/HT66F489 A/D Flash MCU with EEPROM NOP No operation Description No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. Operation ACC ← ACC ″OR″ [m] Affected flag(s) Logical OR immediate data to ACC OR A,x Description Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. Operation ACC ← ACC ″OR″ x Affected flag(s) ORM A,[m] Logical OR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. Operation [m] ← ACC ″OR″ [m]...
Page 180 HT66F488/HT66F489 A/D Flash MCU with EEPROM RLA [m] Rotate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 Affected flag(s) None Rotate Data Memory left through Carry RLC [m] Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. Operation [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 Affected flag(s) RLCA [m] Rotate Data Memory left through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7...
Page 181 HT66F488/HT66F489 A/D Flash MCU with EEPROM RRCA [m] Rotate Data Memory right through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 Affected flag(s) SBC A,[m] Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − [m] − C Affected flag(s) OV, Z, AC, C, SC, CZ SBC A, x Subtract immediate data from ACC with Carry Description The immediate data and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC - [m] - C...
Page 182 HT66F488/HT66F489 A/D Flash MCU with EEPROM Set Data Memory SET [m] Description Each bit of the specified Data Memory is set to 1. Operation [m] ← FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i ← 1 Affected flag(s) None SIZ [m] Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation [m] ← [m] + 1 Skip if [m]=0 Affected flag(s) None SIZA [m] Skip if increment Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the...
Page 183 HT66F488/HT66F489 A/D Flash MCU with EEPROM SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] ← ACC − [m] Affected flag(s) OV, Z, AC, C, SC, CZ SUB A,x Subtract immediate data from ACC Description The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − x Affected flag(s) OV, Z, AC, C, SC, CZ SWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. Operation [m].3~[m].0 ↔ [m].7~[m].4 Affected flag(s) None SWAPA [m] Swap nibbles of Data Memory with result in ACC Description The low-order and high-order nibbles of the specified Data Memory are interchanged. The...
Page 184 HT66F488/HT66F489 A/D Flash MCU with EEPROM TABRD [m] Read table (current page) to TBLH and Data Memory Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None TABRDL [m] Read table (last page) to TBLH and Data Memory Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None ITABRD [m] Increment table pointer low byte first and read table to TBLH and Data Memory Description Increment table pointer low byte, TBLP, first and then the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None...
Page 185 HT66F488/HT66F489 A/D Flash MCU with EEPROM Extended Instruction Definition The extended instructions are used to directly access the data stored in any data memory sections. LADC A,[m] Add Data Memory to ACC with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] + C Affected flag(s) OV, Z, AC, C, SC LADCM A,[m] Add ACC to Data Memory with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. Operation [m] ← ACC + [m] + C Affected flag(s) OV, Z, AC, C, SC LADD A,[m] Add Data Memory to ACC Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] Affected flag(s) OV, Z, AC, C, SC...
Page 186 HT66F488/HT66F489 A/D Flash MCU with EEPROM LCPL [m] Complement Data Memory Description Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. Operation [m] ← [m] Affected flag(s) LCPLA [m] Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC ← [m] Affected flag(s) LDAA [m] Decimal-Adjust ACC for addition with result in Data Memory Description Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. Operation [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or...
Page 187 HT66F488/HT66F489 A/D Flash MCU with EEPROM LMOV A,[m] Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator. Operation ACC ← [m] Affected flag(s) None LMOV [m],A Move ACC to Data Memory Description The contents of the Accumulator are copied to the specified Data Memory. Operation [m] ← ACC Affected flag(s) None LOR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. Operation ACC ← ACC ″OR″ [m] Affected flag(s) LORM A,[m] Logical OR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. Operation [m] ← ACC ″OR″ [m]...
Page 188 HT66F488/HT66F489 A/D Flash MCU with EEPROM LRR [m] Rotate Data Memory right Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. Operation [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 Affected flag(s) None LRRA [m] Rotate Data Memory right with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 Affected flag(s) None LRRC [m] Rotate Data Memory right through Carry Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. Operation [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 Affected flag(s) LRRCA [m]...
Page 189 HT66F488/HT66F489 A/D Flash MCU with EEPROM LSDZ [m] Skip if decrement Data Memory is 0 Description The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation [m] ← [m] − 1 Skip if [m]=0 Affected flag(s) None LSDZA [m] Skip if decrement Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation ACC ← [m] − 1 Skip if ACC=0 Affected flag(s) None Set Data Memory LSET [m] Description Each bit of the specified Data Memory is set to 1. Operation [m] ← FFH...
Page 190 HT66F488/HT66F489 A/D Flash MCU with EEPROM LSNZ [m] Skip if Data Memory is not 0 Description If the content of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Operation Skip if [m] ≠ 0 Affected flag(s) None LSUB A,[m] Subtract Data Memory from ACC Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − [m] Affected flag(s) OV, Z, AC, C, SC, CZ LSUBM A,[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] ← ACC − [m] Affected flag(s) OV, Z, AC, C, SC, CZ LSWAP [m]...
Page 191 HT66F488/HT66F489 A/D Flash MCU with EEPROM LSZ [m].i Skip if bit i of Data Memory is 0 Description If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation Skip if [m].i=0 Affected flag(s) None LTABRD [m] Read table (current page) to TBLH and Data Memory Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None LTABRDL [m] Read table (last page) to TBLH and Data Memory Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None LITABRD [m]...
Page 192 HT66F488/HT66F489 A/D Flash MCU with EEPROM Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/Carton Information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • The Operation Instruction of Packing Materials • Carton information Rev. 1.21 1�2 �ove��e� �� 2�1�...
Page 193 HT66F488/HT66F489 A/D Flash MCU with EEPROM 28-pin SOP (300mil) Outline Dimensions & " Dimensions in inch Symbol Min. Nom. Max. — �.4�6 BSC — — �.2�5 BSC — �.�12 — �.�2� C’ — �.��5 BSC — — — �.1�4 —...
Page 194 HT66F488/HT66F489 A/D Flash MCU with EEPROM 28-pin SSOP (150mil) Outline Dimensions & " Dimensions in inch Symbol Min. Nom. Max. — �.236 BSC — — �.154 BSC — �.��8 — �.�12 C’ — �.3�� BSC — — — �.�6�...
Page 195 Howeve�� Holtek assu�es no �esponsi�ility a�ising f�o� the use of the specifications described. The applications mentioned herein are used solely fo� the pu�pose of illust�ation and Holtek �akes no wa��anty o� �ep�esentation that such applications will �e suita�le without fu�the� �odification� no� �eco��ends the use of its p�oducts fo�...

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Ht66f489

Holtek HT66F488 Manual

Features

General Description

Selection Table

Block Diagram

Pin Assignment

Pin Descriptions

Absolute Maximum Ratings

D.C. Characteristics

A.C. Characteristics

LVR & LVD Characteristics

A/D Converter Electrical Characteristics

Power on Reset Electrical Characteristics

System Architecture

Flash Program Memory

RAM Data Memory

Special Function Register Description

EEPROM Data Memory

Oscillator

Operating Modes and System Clocks

Watchdog Timer

Reset and Initialisation

Input/Output Ports

Timer Modules - TM

Compact Type TM - CTM

Standard Type TM - STM

Periodic Type TM - PTM0, PTM1

Analog to Digital Converter

Serial Interface Module - SIM

UART Module Serial Interface

Interrupts

Software LCD Driver

Low Voltage Detector - LVD

Configuration Option

Application Circuit

Instruction Set

Quick Links

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Table of Contents