Channel Polarity Configuration Register - Chpolr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Channel Polarity Configuration Register – CHPOLR
This register contains the channel capture input or compare output polarity control.
Offset: 0x054
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Reserved
Type/Reset RW
Bits Field
[6] CH3P
[5] CH2NP
[4] CH2P
[3] CH1NP
[2] CH1P
[1] CH0NP
Rev. 1.00
30 29 28
22 21 20
14 13 12
6 5 4
CH3P CH2NP CH2P
0 RW 0 RW
Descriptions
Channel 3 Capture/Compare Polarity
- When Channel 3 is configured as an input (CH3CCS = 0x1 / 0x2 / 0x3)
0: capture event occurs on a Channel 3 rising edge
1: capture event occurs on a Channel 3 falling edge
- When Channel 3 is configured as an output (CH3CCS = 0x0)
0: Channel 3 Output is active high
1: Channel 3 Output is active low
Channel 2 Capture/Compare Complementary Polarity
0: Channel 2 Output is active high
1: Channel 2 Output is active low
Channel 2 Capture/Compare Polarity
- When Channel 2 is configured as an input (CH2CCS = 0x1 / 0x2 / 0x3)
0: capture event occurs on a Channel 2 rising edge
1: capture event occurs on a Channel 2 falling edge
- When Channel 2 is configured as an output (CH2CCS = 0x0)
0: Channel 2 Output is active high
1: Channel 2 Output is active low
Channel 1 Capture/Compare Complementary Polarity
0: Channel 1 Output is active high
1: Channel 1 Output is active low
Channel 1 Capture/Compare Polarity
- When Channel 1 is configured as an input (CH1CCS = 0x1 / 0x2 / 0x3)
0: capture event occurs on a Channel 1 rising edge
1: capture event occurs on a Channel 1 falling edge
- When Channel 1 is configured as an output (CH1CCS = 0x0)
0: Channel 1 Output is active high
1: Channel 1 Output is active low
Channel 0 Capture/Compare Complementary Polarity
0: Channel 0 Output is active high
1: Channel 0 Output is active low
355 of 486
27 26
Reserved
19 18
Reserved
11 10
Reserved
3 2
CH1NP CH1P
0 RW 0 RW 0 RW
25 24
17 16
9 8
1 0
CH0NP CH0P
0 RW 0
July 31, 2018