32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F50231/HT32F50241
Update Event 2
The CHxE, CHxNE, CHxOM control bits for the complementary outputs can be preloaded by
setting the COMPRE bit in the CTR register. Here the shadow bits of the CHxE, CHxNE, and
CHxOM bits will be updated when an update event 2 occurs.
Update Event 2
CHxE
CHxNE
Shadow CHxE
Shadow CHxNE
CHxOM
Shadow CHxOM
CHxO
CHxNO
Figure 126. CHxE, CHxNE and CHxOM Updated by Update Event 2
An update event 2 can be generated by setting the software update bit, UEV2G, in the EVGR
register or by the rising edge of the STI signal if the COMUS bit is set in the CTR register.
Figure 127. Update Event 2 Setup Diagram
Rev. 1.00
COMPRE = 1, CHOSSR = 1, CHxP = CHxNP = 0, CHDTG = 0
Forced
PWM1
Inactive
Forced Inactive
PWM1
UEV2G
STI Rising Edge
COMUS
323 of 486
Forced Active
Forced Active
Update Event 2
(Update CHxE / CHxNE / CHxOM)
July 31, 2018
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