Bus Architecture; Figure 2. Cortex ® -M0+ Block Diagram - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
®
Cortex -M0+ Components
Interrupts
‡ Wakeup
Interrupt
Controller (WIC)
‡ Optional Component
Figure 2. Cortex ® -M0+ Block Diagram

Bus Architecture

The HT32F50231/50241 series devices consist of one master and four slaves in the bus architecture.
The Cortex ® -M0+ AHB-Lite bus is the master while the internal SRAM access bus, the internal
Flash memory access bus, the AHB peripherals access bus and the AHB to APB bridges are the
slaves. The single 32-bit AHB-Lite system interface provides simple integration to all system
regions include the internal SRAM region and the peripheral region. All of the master buses are
based on 32-bit Advanced High-performance Bus-Lite (AHB-Lite) protocol. The following figure
shows the bus architecture of the HT32F50231/50241 series.
Rev. 1.00
Execution Trace Interface
®
Cortex -M0+ Processor
Nested
®
Cortex
Vectored
Processor
Interrupt
Core
Controller
(NVIC)
‡ Memory
Protection
Unit
AHB-Lite Interface
to System
29 of 486
Debug
‡ Breakpoint
-M0+
and
Watchpoint
Unit
‡ Debugger
Interface
Bus Matrix
‡ Single-cycle
I/O Port
‡ Debug
Access Port
(DAP)
‡ Serial Wire or
JTAG Debug Port
July 31, 2018