Holtek HT32F52220 User Manual
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Holtek HT32F52220 User Manual

32-bit microcontroller with arm cortex-m0+ core
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Holtek 32-Bit Microcontroller with Arm
®
Cortex
®
-M0+ Core
HT32F52220/HT32F52230
User Manual
Revision: V1.10
Date: November 09, 2018

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Summary of Contents for Holtek HT32F52220

  • Page 1 Holtek 32-Bit Microcontroller with Arm ® Cortex ® -M0+ Core HT32F52220/HT32F52230 User Manual Revision: V1.10 Date: November 09, 2018...

  • Page 2: Table Of Contents

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Table of Contents 1 Introduction ......................17 Overview ..........................17 Features ..........................18 Device Information ....................... 21 Block Diagram ........................22 2 Document Conventions ..................23 3 System Architecture ..................... 24 ®...
  • Page 3 ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Flash Vector Mapping Control Register – VMCR ................50 Flash Manufacturer and Device ID Register – MDID ..............51 Flash Page Number Status Register – PNSR ................52 Flash Page Size Status Register – PSSR ..................53 Device ID Register –...
  • Page 4 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 APB Configuration Register – APBCFGR ..................87 APB Clock Control Register 0 – APBCCR0 ..................88 APB Clock Control Register 1 – APBCCR1 ..................89 Clock Source Status Register – CKST ................... 90 APB Peripheral Clock Selection Register 0 –...
  • Page 5 ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Port B Pull-Up Selection Register – PBPUR ................121 Port B Pull-Down Selection Register – PBPDR ................122 Port B Open Drain Selection Register – PBODR ................. 123 Port B Output Current Drive Selection Register – PBDRVR ............124 Port B Lock Register –...
  • Page 6 ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 EXTI Interrupt Software Set Command Register – EXTISSCR ............ 148 EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR ............149 EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR ........... 150 EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG ............151 12 Analog to Digital Converter (ADC) ..............
  • Page 7 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Quadrature Decoder ........................191 Output Stage ..........................193 Update Management ........................197 Single Pulse Mode ........................198 Asymmetric PWM Mode ....................... 200 Trigger ADC Start.......................... 201 Register Map ........................201 Register Descriptions ......................202 Timer Counter Configuration Register –...
  • Page 8 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Register Map ........................239 Register Descriptions ......................239 BFTM Control Register – BFTMCR ....................239 BFTM Status Register – BFTMSR ....................240 BFTM Counter Register – BFTMCNTR ..................241 BFTM Compare Value Register – BFTMCMPR ................241 15 Single-Channel Timer (SCTM) .................
  • Page 9 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Watchdog Timer Mode Register 0 – WDTMR0................273 Watchdog Timer Mode Register 1 – WDTMR1................274 Watchdog Timer Status Register – WDTSR ................. 275 Watchdog Timer Protection Register – WDTPR ................276 Watchdog Timer Clock Selection Register –...
  • Page 10 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 SPI Serial Frame Format ......................309 Status Flags ..........................313 Register Map ........................315 Register Descriptions ......................316 SPI Control Register 0 – SPICR0 ....................316 SPI Control Register 1 – SPICR1 ....................317 SPI Interrupt Enable Register –...
  • Page 11 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Baud Rate Generation ........................356 Interrupts and Status ........................358 Register Map ........................358 Register Descriptions ......................359 UART Data Register – URDR ....................... 359 UART Control Register – URCR ....................359 UART Interrupt Enable Register –...
  • Page 12 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 List of Tables Table 1. Features and Peripheral List ..................... 21 Table 2. Document Conventions ......................23 Table 3. Register Map ..........................28 Table 4. Flash Memory and Option Byte ....................32 Table 5.
  • Page 13 ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Table 40. SPI Interface Format Setup ....................309 Table 41. SPI Mode Fault Trigger Conditions ..................314 Table 42. SPI Master Mode SEL Pin Status ..................314 Table 43. SPI Register Map ........................315 Table 44.
  • Page 14 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 List of Figures Figure 1. Block Diagram ......................... 22 Figure 2. Cortex -M0+ Block Diagram ....................25 ® Figure 3. Bus Architecture ........................26 Figure 4. Memory Map ..........................27 Figure 5. Flash Memory Controller Block Diagram ................. 30 Figure 6.
  • Page 15 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Figure 40. MTO Selection ........................185 Figure 41. Capture/Compare Block Diagram ..................186 Figure 42. Input Capture Mode ......................187 Figure 43. PWM Pulse Width Measurement Example ................188 Figure 44. Channel 0 and Channel 1 Input Stages ................189 Figure 45.
  • Page 16 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Figure 81. Watchdog Timer Behavior ....................271 Figure 82. I C Module Block Diagram ....................278 Figure 83. START and STOP Condition ....................280 Figure 84. Data Validity ......................... 280 Figure 85. 7-bit Addressing Mode ......................281 Figure 86.

  • Page 17: Introduction

    Nested Vectored Interrupt Controller (NVIC), SysTick timer, and including advanced debug support. The devices operate at a frequency of up to 40 MHz for HT32F52220/52230 with a Flash accelerator to obtain maximum efficiency. It provides up to 32 KB of embedded Flash memory for code/data storage and 4 KB of embedded SRAM memory for system operation and application program usage.

  • Page 18: Features

    Features ▄ Core ● 32-bit Arm ® Cortex ® -M0+ processor core ● Up to 40MHz operating frequency for HT32F52220/52230 ● 0.93 DMIPS/MHz (Dhrystone v2.1) ● Single-cycle multiplication ● Integrated Nested Vectored Interrupt Controller (NVIC) ● 24-bit SysTick timer ▄...
  • Page 19 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 ▄ Analog to Digital Converter – ADC ● 12-bit SAR ADC engine ● Up to 1 MSPS conversion rate – 1 μs at 28 MHz, 1.4 μs at 40 MHz ● Up to 8 external analog input channels ▄...
  • Page 20 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 ▄ Serial Peripheral Interface – SPI ● Supports both master and slave mode ● Frequency of up to (f /2) MHz for master mode and (f /3) MHz for slave mode PCLK PCLK ●...

  • Page 21: Device Information

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Device Information Table 1. Features and Peripheral List Peripherals HT32F52220 HT32F52230 Main Flash (KB) Option Bytes Flash (KB) SRAM (KB) GPTM SCTM Timers BFTM USART Communication UART EXTI 12-bit ADC Number of channels...

  • Page 22: Block Diagram

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Block Diagram PA; PB SWCLK SWDIO BOOT Powered by V DD15 /PDR Flash Memory Flash SW-DP Interface Memory XTALIN 4 ~ 16 XTALOUT GPIO ® Cortex -M0+ Processor 8 MHz Control Registers...

  • Page 23: Document Conventions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Document Conventions The conventions used in this document are shown in the following table. Table 2. Document Conventions Notation Example Description The number string with a 0x prefix indicates a hexadecimal 0x5a05 number.

  • Page 24: System Architecture

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 System Architecture The system architecture of devices that includes the Arm ® Cortex ® -M0+ processor, bus architecture and memory organization will be described in the following sections. The Cortex ® -M0+ is a next generation processor core which offers many new features.

  • Page 25: Bus Architecture

    Figure 2. Cortex -M0+ Block Diagram ® Bus Architecture The HT32F52220/HT32F52230 series consists of one master and four slaves in the bus architecture. The Cortex ® -M0+ AHB-Lite bus is the master while the internal SRAM access bus, the internal Flash memory access bus, the AHB peripherals access bus and the AHB to APB bridges are the slaves.

  • Page 26: Memory Organization

    -M0+ system peripherals. Refer to the Arm ® Cortex ® -M0+ Technical Reference Manual for more information. The following figure shows the memory map of HT32F52220/HT32F52230 series of devices, including Code, SRAM, peripheral, and other pre- defined regions. Rev. 1.10 26 of 366 November 09, 2018...

  • Page 27: Memory Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Memory Map 0xFFFF_FFFF Reserved 0xE010_0000 0x400F_FFFF Private peripheral bus Reserved 0xE000_0000 0x400B_4000 0x400B_0000 GPIO A ～ B 0x4008_A000 Reserved 0x4008_8000 CKCU/RSTCU 0x4008_2000 Reserved 0x4008_0000 Reserved Reserved 0x4007_7000 BFTM 0x4007_6000 0x4007_5000 Reserved 0x4007_4000...

  • Page 28: Table 3. Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Table 3. Register Map Start Address End Address Peripheral 0x4000_0000 0x4000_0FFF USART 0x4000_1000 0x4000_1FFF UART 0x4000_2000 0x4000_3FFF Reserved 0x4000_4000 0x4000_4FFF 0x4000_5000 0x4001_9FFF Reserved 0x4001_0000 0x4001_0FFF 0x4001_1000 0x4002_1FFF Reserved 0x4002_2000 0x4002_2FFF AFIO 0x4002_3000...

  • Page 29: Embedded Flash Memory

    Programming (IAP) or In Circuit Programming (ICP). For more information, refer to the Flash Memory Controller section. Embedded SRAM Memory The HT32F52220/HT32F52230 series contain up to 4 KB on-chip SRAM which is located at address 0x2000_0000. It support byte, half-word and word access operations. AHB Peripherals The address of the AHB peripherals ranges from 0x4008_0000 to 0x400F_FFFF.

  • Page 30: Flash Memory Controller (Fmc)

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Flash Memory Controller (FMC) Introduction The Flash Memory Controller, FMC, provides all the necessary flash operation functions and pre- fetch buffer for the embedded on-chip Flash memory. Figure below shows the block diagram of the FMC which includes programming interface, control register, pre-fetch buffer and access interface.

  • Page 31: Functional Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Functional Descriptions Flash Memory Map The following figure is the Flash memory map of the system. The address ranges from 0x0000_0000 to 0x1FFF_FFFF (0.5 GB). The address from 0x1F00_0000 to 0x1F00_07FF is mapped to Boot Loader Block (2 KB).

  • Page 32: Flash Memory Architecture

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Flash Memory Architecture The Flash memory consists of up to 32 KB main Flash with 1 KB per page and 2 KB Information Block for Boot Loader. The main Flash memory contains a total of 32 pages (or 16 pages for 16 KB device) which can be erased individually.

  • Page 33: Booting Configuration

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Booting Configuration The system provides two kinds of boot modes which can be selected using the BOOT pin. The BOOT pin is sampled during a power-on reset or system reset. Once the logic value is decided, the first 4 words of vector will be remapped to the corresponding source according to the boot modes.

  • Page 34: Page Erase

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Page Erase The FMC provides a page erase function which is used to initialize the contents of the specific Flash memory page. Each page can be erased independently without affecting the contents of other pages.

  • Page 35: Mass Erase

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Mass Erase The FMC provides a mass erase function which is used to initialize all the main Flash memory contents to a high state. The following steps show the mass erase operation register access sequence.

  • Page 36: Word Programming

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Word Programming The FMC provides a 32-bit word programming function which is used to modify the specific Flash memory word contents. The following steps show the word programming operation register access sequence.

  • Page 37: Option Byte Description

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Option Byte Description The Option Byte region can be treated as an independent Flash memory in which the base address is 0x1FF0_0000. The following table shows the functional description and the Option Byte memory map.

  • Page 38: Page Erase/Program Protection

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Page Erase/Program Protection The FMC provides the page erase/program protection function to prevent unexpected operation of the Flash memory. The page erase (CMD [3:0] = 0x8 in the OCMR register) or word program (CMD [3:0] = 0x4) command will not be accepted by the FMC on the protected pages.

  • Page 39: Security Protection

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Security Protection The FMC provides a Security protection function to prevent an illegal code/data access of the Flash memory. This function is useful for protecting the software / firmware from the illegal users. The function is activated by configuring the Option Byte OB_CP [0] bit. Once the function has been enabled, all the main Flash data access through ICP/Debug mode, programming and page erase operation will not be allowed except via the user’s application.

  • Page 40: Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Register Map The following table shows the FMC registers and reset values. Table 10. FMC Register Map Register Offset Description Reset Value FMC Base Address = 0x4008_0000 TADR 0x000 Flash Target Address Register...

  • Page 41: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Register Descriptions Flash Target Address Register – TADR This register specifies the target address of the page erase and word programming operations. Offset: 0x000 Reset value: 0x0000_0000 TADB Type/Reset 0 RW 0 RW...

  • Page 42: Flash Write Data Register - Wrdr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Flash Write Data Register – WRDR This register specifies the data to be written for programming operation. Offset: 0x004 Reset value: 0x0000_0000 WRDB Type/Reset 0 RW 0 RW 0 RW 0 RW...

  • Page 43: Flash Operation Command Register - Ocmr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Flash Operation Command Register – OCMR This register is used to specify the Flash operation commands that include word program, page erase and mass erase. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset...

  • Page 44: Flash Operation Control Register - Opcr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Flash Operation Control Register – OPCR This register is used for controlling the command commitment and checking the status of the FMC operations. Offset: 0x010 Reset value: 0x0000_000C Reserved Type/Reset Reserved Type/Reset...

  • Page 45: Flash Operation Interrupt Enable Register - Oier

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Flash Operation Interrupt Enable Register – OIER This register is used to enable or disable the FMC interrupt function. The FMC generates interrupts to the controller when corresponding interrupt enable bits are set. Offset:...

  • Page 46: Flash Operation Interrupt And Status Register - Oisr

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Flash Operation Interrupt and Status Register – OISR This register indicates the FMC interrupt status which is used to check if a Flash operation has been finished or an error occurs. The status bits, bit [4:0], are available when the corresponding bits in the OIER register are set.
  • Page 47 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions ITADF Invalid Target Address Flag 0: The target address is valid 1: The target address is invalid The data in the TADR field must be in the range from 0x0000_0000 to 0x1FFF_ FFFF.

  • Page 48: Flash Page Erase/Program Protection Status Register - Ppsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Flash Page Erase/Program Protection Status Register – PPSR This register indicates the page protection status of the Flash page erase/program protection functions. Offset: 0x020 (0) ~ 0x02C (3) Reset value: 0xXXXX_XXXX PPSBn...

  • Page 49: Flash Security Protection Status Register - Cpsr

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Flash Security Protection Status Register – CPSR This register indicates the Flash Memory Security protection status. The content of this register is not dynamically updated and will only be reloaded by the Option Byte loader which is active when any kind of reset occurs.

  • Page 50: Flash Vector Mapping Control Register - Vmcr

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Flash Vector Mapping Control Register – VMCR This register is used to control the vector mapping. The reset value of the VMCR register is determined by the external BOOT pin during the power-on reset period.

  • Page 51: Flash Manufacturer And Device Id Register - Mdid

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Flash Manufacturer and Device ID Register – MDID This register is used to store the manufacture ID and device part number information which can be used as the product identity. Offset: 0x180...

  • Page 52: Flash Page Number Status Register - Pnsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Flash Page Number Status Register – PNSR This register is used to indicate the Flash memory page number. Offset: 0x184 Reset value: 0x0000_00XX PNSB Type/Reset 0 RO 0 RO 0 RO 0 RO...

  • Page 53: Flash Page Size Status Register - Pssr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Flash Page Size Status Register – PSSR This register is used to indicate the page size in bytes. Offset: 0x188 Reset value: 0x0000_0400 PSSB Type/Reset 0 RO 0 RO 0 RO 0 RO...

  • Page 54: Device Id Register - Did

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Device ID Register – DID This register is used to store the device part number information which can be used as the product identity. Offset: 0x18C Reset value: 0x000X_XXXX Reserved Type/Reset Reserved...

  • Page 55: Flash Pre-Fetch Control Register - Cfcr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Flash Pre-fetch Control Register – CFCR This register is used to control the FMC pre-fetch module. Offset: 0x200 Reset value: 0x0000_0011 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved PFBE Reserved WAIT Type/Reset...

  • Page 56: Custom Id Register N - Cidrn ( N = 0 ~3)

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Custom ID Register n – CIDRn ( n = 0 ~3) This register is used to store the custom ID information which can be used as the custom identity. Offset: 0x310 (0) ~ 0x31C (3) Reset value: Various depending on Flash Manufacture Privilege Information Block.

  • Page 57: Power Control Unit (Pwrcu)

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Power Control Unit (PWRCU) Introduction The power consumption can be regarded as one of the most important issues for many embedded system applications. Accordingly the Power Control Unit, PWRCU, provides many types of power saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2, and Power-Down modes.

  • Page 58: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Features ▄ Two power domains: V 3.3 V and V 1.5 V power domains. DD15 ▄ Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down modes. ▄ Internal Voltage regulator supplies 1.5 V voltage source.

  • Page 59: Figure 12. Power On Reset / Power Down Reset Waveform

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Power On Reset (POR) / Power Down Reset (PDR) The device has an integrated POR/PDR circuitry that allows proper operation starting from/down to 2.0 V. The device remains in Power-Down mode when V is below a specified threshold V without the need for an external reset circuit.

  • Page 60: 1.5 V Power Domain

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 High Speed External Oscillator The High Speed External Oscillator, HSE, is located in the V power domain. The HSE crystal oscillator can be switched on or off using the HSEEN bit in the Global Clock Control Register, GCCR.

  • Page 61: Table 12. Enter/Exit Power Saving Modes

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Sleep Mode By default, only the CPU clock will be stopped in the Sleep mode. Clearing the FMCEN or SRAMEN bit in the CKCU AHBCCR register to 0 will have the effect of stopping the Flash clock or SRAM clock after the system enters the Sleep mode.

  • Page 62: Register Map

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Power-Down Mode The Power-Down mode is derived from the Deep-Sleep mode of the CPU together with the additional control bits LDOOFF and DMOSON. To enter the Power-Down mode, users can configure the registers shown in the preceding Mode-Entering table and execute the WFI or WFE instruction.

  • Page 63: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Register Descriptions Power Control Status Register – PWRSR This register indicates the power control status. Offset: 0x100 Reset value: 0x0000_0001 (Reset only by V domain power on reset) Reserved Type/Reset Reserved Type/Reset...

  • Page 64: Power Control Register - Pwrcr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Power Control Register – PWRCR This register provides power control bits for the different kinds of power saving modes. Offset: 0x104 Reset value: 0x0000_0000 (Reset only by V domain power on reset)
  • Page 65 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions WUPEN External WAKEUP Pin Enable 0: Disable WAKEUP pin function. 1: Enable WAKEUP pin function. The Software can set the WUPEN bit as 1 to enable the WAKEUP pin function before entering the power saving mode.

  • Page 66: Vdd Power Domain Test Register - Pwrtest

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Power Domain Test Register – PWRTEST This register specifies a read-only value for the software to recognize whether V Power Domain is ready for access. Offset: 0x108 Reset value: 0x0000_0027 Reserved Type/Reset...

  • Page 67: Low Voltage / Brown Out Detect Control And Status Register - Lvdcsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Low Voltage / Brown Out Detect Control and Status Register – LVDCSR This register specifies flags, enable bits and option bits for low voltage detector. Offset: 0x110 Reset value: 0x0000_0000 (Reset only by V...
  • Page 68 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions [16] LVDEN Low Voltage Detect Enable 0: Disable Low Voltage Detect 1: Enable Low Voltage Detect Setting this bit to 1 will generate a LVD event when the V power is lower than the voltage set by LVDS bits.

  • Page 69: Clock Control Unit (Ckcu)

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Clock Control Unit (CKCU) Introduction The Clock Control unit (CKCU) provides functions of high speed internal RC oscillator (HSI), High speed external crystal oscillator (HSE), Low speed internal RC oscillator (LSI), Phase Lock Loop (PLL), HSE clock monitor, clock prescaler, clock multiplexer and clock gating.

  • Page 70: Figure 13. Ckcu Block Diagram

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Prescaler Divider CK_REF 1 ~ 32 CKREFPRE CKREFEN PLLSRC 8 MHz HSI RC PLLEN = 40 MHz (Recommended) STCLK CK_PLL,max (to SysTick) CK_PLL HSIEN SW[2:0] CK_GPIO GPIOAEN ( to GPIO port) 4-16 MHz...

  • Page 71: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Features ▄ 4 ~ 16 MHz external crystal oscillator (HSE) ▄ Internal 8 MHz RC oscillator (HSI) with configuration option calibration and custom trimming capability. ▄ PLL with selectable clock source (from HSE or HSI) for system clock.

  • Page 72: High Speed Internal Rc Oscillator - Hsi

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 The HSE crystal oscillator can be switched on or off using the HSEEN bit in the Global Clock Control Register (GCCR). The HSERDY flag in the Global Clock Status Register (GCSR) will indicate if the high-speed external crystal oscillator is stable. When switching on the HSE oscillator, the HSE clock will still not be released until this HSERDY bit is set by the hardware.

  • Page 73: Phase Locked Loop - Pll

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Phase Locked Loop – PLL This PLL can provide 4 ~ 48 MHz clock output which is 1~12 multiples of a fundamental reference frequency of 4 ~ 16 MHz. The rationale of the clock synthesizer relies on the digital Phase Locked...

  • Page 74: Low Speed Internal Rc Oscillator - Lsi

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Table 15. Output Divider2 Value Mapping Output divider 2 setup bits S[1:0] NO2 (Output divider 2 value) (POTD bits in the PLLCFGR register) Table 16. Feedback Divider2 Value Mapping Feedback divider2 setup bits B[3:0]...

  • Page 75: System Clock (Ck_Sys) Selection

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 System Clock (CK_SYS) Selection After the system reset occurs, the default system clock source, CK_SYS, will be the high speed internal RC oscillator, HSI. The CK_SYS may come from the HSI, HSE, LSI or PLL output clock and it can be switched from one clock source to another by configuring the System Clock Switch bits SW in the Global Clock Control Register, GCCR.

  • Page 76: Hse Clock Monitor

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 HSE Clock Monitor The HSE Clock Monitor main function is enabled by the HSE Clock Monitor Enable bit CKMEN in the Global Clock Control Register, GCCR. The HSE clock monitor function should be enabled after the HSE oscillator start-up delay and disabled when the HSE oscillator is stopped.

  • Page 77: Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Register Map The following table shows the CKCU register and reset value. Table 18. CKCU Register Map Register Offset Description Reset Value GCFGR 0x000 Global Clock Configuration Register 0x0000_0102 GCCR 0x004 Global Clock Control Register...

  • Page 78: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Register Descriptions Global Clock Configuration Register – GCFGR This register specifies the clock source for the PLL/USART/Watchdog Timer/CKOUT. Offset: 0x000 Reset value: 0x0000_0102 LPMOD Reserved Type/Reset 0 RO 0 RO Reserved Type/Reset...
  • Page 79 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions [2:0] CKOUTSRC CKOUT Clock Source Selection 000: CK_REF is selected where CK_REF = CK_PLL / (CKREFPRE+1) / 2 001: (HCLKC / 16) is selected 010: (CK_SYS / 16) is selected...

  • Page 80: Global Clock Control Register - Gccr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Global Clock Control Register – GCCR This register specifies the clock enable bits. Offset: 0x004 Reset value: 0x0000_0803 Reserved Type/Reset Reserved PSRCEN CKMEN Type/Reset 0 RW Reserved HSIEN HSEEN PLLEN HSEGAIN Type/Reset...
  • Page 81 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions PLLEN PLL Enable 0: PLL is disabled 1: PLL is enabled Set and reset by software. This bit cannot be reset if the PLL clock is used as the system clock.

  • Page 82: Global Clock Status Register - Gcsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Global Clock Status Register – GCSR This register indicates the clock ready status. Offset: 0x008 Reset value: 0x0000_0028 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved LSIRDY Reserved HSIRDY HSERDY PLLRDY Reserved Type/Reset...

  • Page 83: Global Clock Interrupt Register - Gcir

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Global Clock Interrupt Register – GCIR This register specifies the interrupt enable and flag bits. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved CKSIE Type/Reset Reserved Type/Reset Reserved CKSF Type/Reset Bits Field...

  • Page 84: Pll Configuration Register - Pllcfgr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 PLL Configuration Register – PLLCFGR This register specifies the PLL configurations. Offset: 0x018 Reset value: 0x0000_0000 Reserved PFBD Type/Reset 0 RW 0 RW PFBD POTD Reserved Type/Reset 0 RW 0 RW Reserved...

  • Page 85: Ahb Configuration Register - Ahbcfgr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 AHB Configuration Register – AHBCFGR This register specifies the system clock frequency. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved AHBPRE Type/Reset 0 RW 0 RW Bits Field...

  • Page 86: Ahb Clock Control Register - Ahbccr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 AHB Clock Control Register – AHBCCR This register specifies the AHB clock enable control bits. Offset: 0x024 Reset value: 0x0000_0065 Reserved Type/Reset Reserved PBEN PAEN Type/Reset 0 RW Reserved CKREFEN Reserved Type/Reset...

  • Page 87: Apb Configuration Register - Apbcfgr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions FMCEN Flash Memory Controller Clock Enable 0: FMC clock is automatically disabled by hardware during Sleep mode 1: FMC clock is always enabled during Sleep mode Set and reset by software. User can set the FMCEN bit to 0 to reduce the power consumption if the Flash Memory is unused during the Sleep mode.

  • Page 88: Apb Clock Control Register 0 - Apbccr0

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 APB Clock Control Register 0 – APBCCR0 This register specifies the APB peripherals clock enable control bits. Offset: 0x02C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTIEN AFIOEN Reserved UREN Reserved USREN...

  • Page 89: Apb Clock Control Register 1 - Apbccr1

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 APB Clock Control Register 1 – APBCCR1 This register specifies the APB peripherals clock enable control bits. Offset: 0x030 Reset value: 0x0000_0000 Reserved SCTM1EN SCTM0EN Reserved ADCCEN Type/Reset 0 RW Reserved BFTMEN...

  • Page 90: Clock Source Status Register - Ckst

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Clock Source Status Register – CKST This register specifies the clock source status. Offset: 0x034 Reset value: 0x0100_0003 Reserved HSIST Type/Reset 0 RO 0 RO Reserved HSEST Type/Reset 0 RO Reserved PLLST...

  • Page 91: Apb Peripheral Clock Selection Register 0 - Apbpcsr0

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 APB Peripheral Clock Selection Register 0 – APBPCSR0 This register specifies the APB peripheral clock prescaler selection. Offset: 0x038 Reset value: 0x0000_0000 Reserved URPCLK Reserved USRPCLK Type/Reset 0 RW 0 RW Reserved...
  • Page 92 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions [1:0] I2CPCLK I2C Peripheral Clock Selection 00: PCLK = CK_AHB 01: PCLK = CK_AHB / 2 10: PCLK = CK_AHB / 4 11: PCLK = CK_AHB / 8 PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock Rev.

  • Page 93: Apb Peripheral Clock Selection Register 1 - Apbpcsr1

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 APB Peripheral Clock Selection Register 1 – APBPCSR1 This register specifies the APB peripheral clock prescaler selection. Offset: 0x03C Reset value: 0x0000_0000 Reserved SCTM1PCLK SCTM0PCLK Type/Reset 0 RW 0 RW 0 RW...
  • Page 94 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions [3:2] EXTIPCLK EXTI Peripheral Clock Selection 00: PCLK = CK_AHB 01: PCLK = CK_AHB / 2 10: PCLK = CK_AHB / 4 11: PCLK = CK_AHB / 8 PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock...

  • Page 95: Low Power Control Register - Lpcr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Low Power Control Register – LPCR This register specifies the low power control. Offset: 0x300 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved VDDISO Type/Reset Bits Field Descriptions VDDISO Domain Isolation Control...

  • Page 96: Mcu Debug Control Register - Mcudbgcr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 MCU Debug Control Register – MCUDBGCR This register specifies the MCU debug control. Offset: 0x304 Reset value: 0x0000_0000 Reserved Type/Reset DBSCTM1 DBSCTM0 Reserved DBUR Reserved DBBFTM Type/Reset 0 RW Reserved DBDSLP2 Reserved...
  • Page 97 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions DBUSR USART Debug Mode Enable 0: Same behavior as in normal mode 1: USART FIFO timeout is frozen when the core is halted Set and reset by software. DBGPTM...

  • Page 98: Reset Control Unit (Rstcu)

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Reset Control Unit (RSTCU) Introduction The Reset Control Unit, RSTCU, has three kinds of reset, the power on reset, system reset and APB unit reset. The power on reset, known as a cold reset, resets the full system during a power up.

  • Page 99: Functional Descriptions

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Functional Descriptions Power On Reset The Power on reset, POR, is generated by either an external reset or the internal reset generator. Both types have an internal filter to prevent glitches from causing erroneous reset operations. By referring to Figure 17, the POR15 active low signal will be de-asserted when the internal LDO voltage regulator is ready to provide 1.5 V power.

  • Page 100: Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Register Map The following table shows the RSTCU registers and reset values. Table 19. RSTCU Register Map Register Offset Description Reset Value RSTCU Base Address = 0x4008_8000 GRSR 0x100 Global Reset Status Register...

  • Page 101: Ahb Peripheral Reset Register - Ahbprstr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions NVICRSTF NVIC Reset Flag 0: No NVIC asserting system reset occurred 1: NVIC asserting system reset occurred This bit is set by hardware when a system reset occurs and reset by writing 1 into it or by hardware when a power on reset occurs.

  • Page 102: Apb Peripheral Reset Register 0 - Apbprstr0

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 APB Peripheral Reset Register 0 – APBPRSTR0 This register specifies several APB peripherals software reset control bits. Offset: 0x108 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTIRST AFIORST Reserved URRST Reserved USRRST...

  • Page 103: Apb Peripheral Reset Register 1 - Apbprstr1

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 APB Peripheral Reset Register 1 – APBPRSTR1 This register specifies several APB peripherals software reset control bits. Offset: 0x10C Reset value: 0x0000_0000 Reserved SCTM1RST SCTM0RST Reserved ADCRST Type/Reset 0 RW Reserved BFTMRST...

  • Page 104: General Purpose I/O (Gpio)

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 General Purpose I/O (GPIO) Introduction There are up to 23 General Purpose I/O port, GPIO, named PA0~PA7, PA9, PA12~PA15, PB0~PB4, PB7~PB8 and PB12~PB14 for the device to implement the logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirement of specific applications.

  • Page 105: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Features ▄ Input/output direction control ▄ Schmitt Trigger Input function enable control ▄ Input weak pull-up/pull-down control ▄ Output push-pull/open drain enable control ▄ Output set/reset control ▄ Output drive current selection ▄...

  • Page 106: Table 20. Afio, Gpio And Io Pad Control Signal True Table

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 PxCFGn Input DMUX Output AFIO Control IOPAD AFIO ADEN PxDOUTn PxDINn PxRSTn PxDVn PxINENn PxSETn PxODn PxDIRn PxPDn PxPUn GPIO Figure 19. AFIO/GPIO Control Signal PxDINn/PxDOUTn (x=A ~ B): Data Input/Data Output...

  • Page 107: Gpio Locking Mechanism

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 GPIO Locking Mechanism The GPIO also offers a lock function to lock the port until a reset event occurs. The PxLOCKR (x = A ~ B) registers are used to lock the port x and lock control options. The value 0x5FA0 is written...

  • Page 108: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Register Descriptions Port A Data Direction Control Register – PADIRCR This register is used to control the direction of the GPIO Port A pin as input or output. Offset: 0x000 Reset value: 0x0000_0000...

  • Page 109: Port A Input Function Enable Control Register - Painer

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Port A Input Function Enable Control Register – PAINER This register is used to enable or disable the GPIO Port A input function. Offset: 0x004 Reset value: 0x0000_0200 Reserved Type/Reset Reserved Type/Reset...

  • Page 110: Port A Pull-Up Selection Register - Papur

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Port A Pull-Up Selection Register – PAPUR This register is used to enable or disable the GPIO Port A pull-up function. Offset: 0x008 Reset value: 0x0000_3200 Reserved Type/Reset Reserved Type/Reset PAPU Reserved...

  • Page 111: Port A Pull-Down Selection Register - Papdr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Port A Pull-Down Selection Register – PAPDR This register is used to enable or disable the GPIO Port A pull-down function. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PAPD Reserved...

  • Page 112: Port A Open Drain Selection Register - Paodr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Port A Open Drain Selection Register – PAODR This register is used to enable or disable the GPIO Port A open drain function. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...

  • Page 113: Port A Output Current Drive Selection Register - Padrvr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Port A Output Current Drive Selection Register – PADRVR This register specifies the GPIO Port A output driving current. Offset: 0x014 Reset value: 0x0000_0000 PADV15 PADV14 PADV13 PADV12 Type/Reset 0 RW 0 RW...

  • Page 114: Port A Lock Register - Palockr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Port A Lock Register – PALOCKR This register specifies the GPIO Port A lock configuration. Offset: 0x018 Reset value: 0x0000_0000 PALKEY Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...

  • Page 115: Port A Data Input Register - Padinr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Port A Data Input Register – PADINR This register specifies the GPIO Port A input data. Offset: 0x01C Reset value: 0x0000_3200 Reserved Type/Reset Reserved Type/Reset PADIN Reserved PADIN Reserved Type/Reset 0 RO...

  • Page 116: Port A Output Data Register - Padoutr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Port A Output Data Register – PADOUTR This register specifies the GPIO Port A output data. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PADOUT Reserved PADOUT Reserved Type/Reset 0 RW...

  • Page 117: Port A Output Set/Reset Control Register - Pasrr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Port A Output Set/Reset Control Register – PASRR This register is used to set or reset the corresponding bit of the GPIO Port A output data. Offset: 0x024 Reset value: 0x0000_0000 PARST...

  • Page 118: Port A Output Reset Register - Parr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Port A Output Reset Register – PARR This register is used to reset the corresponding bit of the GPIO Port A output data. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...

  • Page 119: Port B Data Direction Control Register - Pbdircr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Port B Data Direction Control Register – PBDIRCR This register is used to control the direction of GPIO Port B pin as input or output. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset...

  • Page 120: Port B Input Function Enable Control Register - Pbiner

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Port B Input Function Enable Control Register – PBINER This register is used to enable or disable the GPIO Port B input function. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...

  • Page 121: Port B Pull-Up Selection Register - Pbpur

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Port B Pull-Up Selection Register – PBPUR This register is used to enable or disable the GPIO Port B pull-up function. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved PBPU...

  • Page 122: Port B Pull-Down Selection Register - Pbpdr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Port B Pull-Down Selection Register – PBPDR This register is used to enable or disable the GPIO Port B pull-down function. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved PBPD...

  • Page 123: Port B Open Drain Selection Register - Pbodr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Port B Open Drain Selection Register – PBODR This register is used to enable or disable the GPIO Port B open drain function. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...

  • Page 124: Port B Output Current Drive Selection Register - Pbdrvr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Port B Output Current Drive Selection Register – PBDRVR This register specifies the GPIO Port B output driving current. Offset: 0x014 Reset value: 0x0000_0000 Reserved PBDV14 PBDV13 PBDV12 Type/Reset 0 RW 0 RW...

  • Page 125: Port B Lock Register - Pblockr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Port B Lock Register – PBLOCKR This register specifies the GPIO Port B lock configuration. Offset: 0x018 Reset value: 0x0000_0000 PBLKEY Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...

  • Page 126: Port B Data Input Register - Pbdinr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Port B Data Input Register – PBDINR This register specifies the GPIO Port B input data. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved PBDIN Reserved PBDIN Type/Reset 0 RO...

  • Page 127: Port B Output Data Register - Pbdoutr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Port B Output Data Register – PBDOUTR This register specifies the GPIO Port B output data. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved PBDOUT Reserved PBDOUT Type/Reset 0 RW...

  • Page 128: Port B Output Set/Reset Control Register - Pbsrr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Port B Output Set/Reset Control Register – PBSRR This register is used to set or reset the corresponding bit of the GPIO Port B output data. Offset: 0x024 Reset value: 0x0000_0000 Reserved...

  • Page 129: Port B Output Reset Register - Pbrr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Port B Output Reset Register – PBRR This register is used to reset the corresponding bit of the GPIO Port B output data. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...

  • Page 130: Alternate Function Input/Output Control Unit (Afio)

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Alternate Function Input/Output Control Unit (AFIO) Introduction In order to expand the flexibility of the GPIO or the usage of peripheral functions, each IO pin can be configured to have up to sixteen different functions such as GPIO or IP functions by setting the GPxCFGLR or GPxCFGHR register where x is the different port name.

  • Page 131: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Features ▄ APB slave interface for register access ▄ EXTI source selection ▄ Configurable pin function for each GPIO, up to sixteen alternative functions on each pin ▄ AFIO lock mechanism Functional Descriptions External Interrupt Pin Selection The GPIO pins are connected to the 16 EXTI lines as shown in the accompanying figure.

  • Page 132: Alternate Function

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Alternate Function Up to sixteen alternative functions can be chosen for each I/O pad by setting the PxCFGn [3:0] field in the GPxCFGLR or GPxCFGHR (n = 0~15, x = A~ B) registers. If the pin is selected as an unavailable item which is noted as a “N/A”...

  • Page 133: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Register Descriptions EXTI Source Selection Register 0 – ESSR0 This register specifies the IO selection of EXTI0 ~ EXTI7. Offset: 0x000 Reset value: 0x0000_0000 EXTI7PIN EXTI6PIN Type/Reset 0 RW 0 RW 0 RW...

  • Page 134: Exti Source Selection Register 1 - Essr1

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 EXTI Source Selection Register 1 – ESSR1 This register specifies the IO selection of EXTI8~EXTI15. Offset: 0x004 Reset value: 0x0000_0000 EXTI15PIN EXTI14PIN Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...

  • Page 135: Gpio X Configuration Low Register - Gpxcfglr, X = A, B

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 GPIO x Configuration Low Register – GPxCFGLR, x = A, B This low register specifies the alternate function of GPIO Port x. x = A, B Offset: 0x020, 0x028 Reset value: 0x0000_0000...

  • Page 136: Gpio X Configuration High Register - Gpxcfghr, X = A, B

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 GPIO x Configuration High Register – GPxCFGHR, x = A, B This high register specifies the alternate function of GPIO Port x. x = A, B Offset: 0x024, 0x02C Reset value: 0x0000_0000...

  • Page 137: Nested Vectored Interrupt Controller (Nvic)

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Nested Vectored Interrupt Controller (NVIC) Introduction In order to reduce the latency and increase the interrupt processing efficiency, a tightly coupled integrated section, which is named as Nested Vectored Interrupt Controller (NVIC) is provided by the Cortex -M0+.

  • Page 138: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Interrupt Exception Exception Vector Priority Description Number Number type Address Reserved — 0x07C — Reserved — 0x080 — BFTM Configurable 0x084 BFTM global interrupt Reserved — 0x088 — Configurable 0x08C I2C global interrupt Reserved —...

  • Page 139: Function Descriptions

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Function Descriptions SysTick Calibration The SysTick Calibration Value Register (SCALIB) is provided by the NVIC to give a reference time base of 1ms for the RTOS tick timer or other purpose. The TENMS field in the SCALIB register...

  • Page 140: External Interrupt/Event Controller (Exti)

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 External Interrupt/Event Controller (EXTI) Introduction The External Interrupt/Event Controller, EXTI, comprises 16 edge detectors which can generate a wake-up event or interrupt requests independently. In interrupt mode there are five trigger types...

  • Page 141: Function Descriptions

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Function Descriptions Wakeup Event Management In order to wakeup the system from the power saving mode, the EXTI controller provides a function which can monitor external events and send them to the CPU core and the Clock Control Unit, CKCU.

  • Page 142: External Interrupt/Event Line Mapping

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 External Interrupt/Event Line Mapping All GPIO pins can be selected as EXTI trigger sources by configuring the EXTInPIN [3:0] field in the AFIO ESSRn (n = 0 ~ 1) register to trigger an interrupt or event. Refer to the AFIO section for more details.

  • Page 143: Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Register Map The following table shows the EXTI registers and reset values. Table 26. EXTI Register Map Register Offset Description Reset Value EXTICFGR0 0x000 EXTI Interrupt 0 Configuration Register 0x0000_0000 EXTICFGR1 0x004...

  • Page 144: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Register Descriptions EXTI Interrupt Configuration Register n – EXTICFGRn, n = 0 ~ 15 This register is used to specify the debounce function and select the trigger type. Offset: 0x000 (0) ~ 0x03C (15)

  • Page 145: Exti Interrupt Control Register - Exticr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 EXTI Interrupt Control Register – EXTICR This register is used to control the EXTI interrupt. Offset: 0x040 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15EN EXTI14EN EXTI13EN EXTI12EN EXTI11EN EXTI10EN EXTI9EN EXTI8EN...

  • Page 146: Exti Interrupt Edge Flag Register - Extiedgeflgr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR This register is used to indicate if an EXTI edge has been detected. Offset: 0x044 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15EDF EXTI14EDF EXTI13EDF EXTI12EDF EXTI11EDF EXTI10EDF EXTI9EDF EXTI8EDF...

  • Page 147: Exti Interrupt Edge Status Register - Extiedgesr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 EXTI Interrupt Edge Status Register – EXTIEDGESR This register indicates the polarity of a detected EXTI edge. Offset: 0x048 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15EDS EXTI14EDS EXTI13EDS EXTI12EDS EXTI11EDS EXTI10EDS EXTI9EDS EXTI8EDS...

  • Page 148: Exti Interrupt Software Set Command Register - Extisscr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 EXTI Interrupt Software Set Command Register – EXTISSCR This register is used to activate the EXTI interrupt. Offset: 0x04C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15SC EXTI14SC EXTI13SC EXTI12SC EXTI11SC EXTI10SC...

  • Page 149: Exti Interrupt Wakeup Control Register - Extiwakupcr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR This register is used to control the EXTI interrupt and wakeup function. Offset: 0x050 Reset value: 0x0000_0000 EVWUPIEN Reserved Type/Reset Reserved Type/Reset EXTI15WEN EXTI14WEN EXTI13WEN EXTI12WEN EXTI11WEN EXTI10WEN EXTI9WEN EXTI8WEN...

  • Page 150: Exti Interrupt Wakeup Polarity Register - Extiwakuppolr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR This register is used to select the EXTI line interrupt wakeup polarity. Offset: 0x054 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15WPOL EXTI14WPOL EXTI13WPOL EXTI12WPOL EXTI11WPOL EXTI10WPOL EXTI9WPOL EXTI8WPOL...

  • Page 151: Exti Interrupt Wakeup Flag Register - Extiwakupflg

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG This register is the EXTI interrupt wake flag register. Offset: 0x058 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15WFL EXTI14WFL EXTI13WFL EXTI12WFL EXTI11WFL EXTI10WFL EXTI9WFL...

  • Page 152: Analog To Digital Converter (Adc)

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Analog to Digital Converter (ADC) Introduction A 12-bit multi-channel Analog to Digital Converter is integrated in the device. There are a total of 10 multiplexed channels including 8 external channels on which the external analog signal can be supplied and 2 internal channels.

  • Page 153: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Features ▄ 12-bit SAR ADC engine ▄ Up to 1 MSPS conversion rate ▄ 8 external analog input channels ▄ 2 internal analog input channels for reference voltage detection ▄ Programmable sampling time for conversion channel ▄...

  • Page 154: Function Descriptions

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Function Descriptions ADC Clock Setup The ADC clock, CK_ADC, is provided by the Clock Controller, which is synchronous and divided by with the AHB clock known as HCLK. Refer to the Clock Control Unit chapter for more details.

  • Page 155: Figure 26. One Shot Conversion Mode

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Conversion (ex: Sequence Length=8) Cycle Cycle Start of Conversion Single sample End of Conversion Cycle End of Conversion Figure 26. One Shot Conversion Mode Continuous Conversion Mode In the Continuous Conversion Mode, repeated conversion cycle will start automatically without requiring additional A/D start trigger signals after a channels group conversion has completed.
  • Page 156 ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Discontinuous Conversion Mode The A/D converter will operate in the Discontinuous Conversion Mode for channels group when the A/D conversion mode bit field ADMODE [1:0] in the ADCCONV register is set to 0x3. The group to be converted can have up to 8 channels and can be arranged in a specific sequence by configuring the ADCLSTn registers where n ranges from 0 to 1.

  • Page 157: Start Conversion On External Event

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Discontinuous Conversion Mode (ex: Sequence Length=8, Subgroup Length=3 ) Cycle Cycle Subgroup 0 Subgroup 1 Subgroup 2 Subgroup 0 Start of Conversion Single sample End of Conversion Subgroup End of Conversion Cycle End of Conversion Figure 28.

  • Page 158: Sampling Time Setting

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Sampling Time Setting The conversion channel sampling time can be programmed according to the input resistance of the input voltage source. This sampling time must be enough for the input voltage source to charge the internal sample and hold capacitor in the A/D converter to the input voltage level.

  • Page 159: Interrupts

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Interrupts When an A/D conversion is completed, an End of Conversion EOC event will occur. There are three kinds of EOC events which are known as single sample EOC, subgroup EOC and cycle EOC for A/D conversion.

  • Page 160: Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Register Map The following table shows the A/D Converter registers and reset values. Table 28. A/D Converter Register Map Register Offset Description Reset Value ADCCR 0x000 ADC Conversion Control Register 0x0000_0000 ADCLST0...

  • Page 161: Register Descriptions

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Register Descriptions ADC Conversion Control Register – ADCCR This register specifies the mode setting, sequence length, and subgroup length of the ADC conversion mode. Note that once the content of ADCCR is changed, the conversion in progress will be aborted and the A/D converter will return to idle state.
  • Page 162 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions [1:0] ADMODE ADC Conversion Mode ADMODE [1:0] Mode Descriptions After a start trigger, the conversion will be One shot mode executed on the specific channels for the whole conversion sequence once.

  • Page 163: Adc Conversion List Register 0 - Adclst0

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 ADC Conversion List Register 0 – ADCLST0 This register specifies the conversion sequence order No.0 ~ No.3 of the ADC. Offset: 0x004 Reset value: 0x0000_0000 Reserved ADSEQ3 Type/Reset 0 RW 0 RW...

  • Page 164: Adc Conversion List Register 1 - Adclst1

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 ADC Conversion List Register 1 – ADCLST1 This register specifies the conversion sequence order No.4 ~ No.7 of the ADC. Offset: 0x008 Reset value: 0x0000_0000 Reserved ADSEQ7 Type/Reset 0 RW 0 RW...

  • Page 165: Adc Input Sampling Time Register - Adcstr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 ADC Input Sampling Time Register – ADCSTR This register specifies the A/D conversion input channel sampling time. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset ADST Type/Reset 0 RW...

  • Page 166: Adc Conversion Data Register Y - Adcdry, Y = 0 ~ 7

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7 This register is used to store the conversion data of the ADC conversion sequence order No.y which is specified by the ADSEQy field in the ADCLSTn (n=0~1) registers.

  • Page 167: Adc Trigger Control Register - Adctcr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 ADC Trigger Control Register – ADCTCR This register contains the ADC start conversion trigger enable bits. Offset: 0x070 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved BFTM ADEXTI ADSW Type/Reset...

  • Page 168: Adc Trigger Source Register - Adctsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 ADC Trigger Source Register – ADCTSR This register contains the trigger source selection and the software trigger bit of the conversion. Offset: 0x074 Reset value: 0x0000_0000 Reserved Type/Reset 0 RW 0 RW...

  • Page 169: Adc Watchdog Control Register - Adcwcr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 ADC Watchdog Control Register – ADCWCR This register provides the control bits and status of the ADC watchdog function. Offset: 0x078 Reset value: 0x0000_0000 Reserved ADUCH Type/Reset 0 RO 0 RO 0 RO...

  • Page 170: Adc Watchdog Threshold Register - Adctr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions ADWUE ADC Watchdog Upper Threshold Enable Bit 0: Disable upper threshold monitor function 1: Enable upper threshold monitor function ADWLE ADC Watchdog Lower Threshold Enable Bit 0: Disable lower threshold monitor function 1: Enable lower threshold monitor function ADC Watchdog Threshold Register –...

  • Page 171: Adc Interrupt Enable Register - Adcier

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 ADC Interrupt Enable Register – ADCIER This register contains the ADC interrupt enable bits. Offset: 0x080 Reset value: 0x0000_0000 Reserved ADIEO Type/Reset Reserved ADIEU ADIEL Type/Reset 0 RW Reserved Type/Reset Reserved ADIEC...

  • Page 172: Adc Interrupt Raw Status Register - Adciraw

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 ADC Interrupt Raw Status Register – ADCIRAW This register contains the ADC interrupt raw status bits. Offset: 0x084 Reset value: 0x0000_0000 Reserved ADIRAWO Type/Reset Reserved ADIRAWU ADIRAWL Type/Reset 0 RO Reserved Type/Reset...

  • Page 173: Adc Interrupt Status Register - Adcisr

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 ADC Interrupt Status Register – ADCISR This register contains the ADC interrupt masked status bits. The corresponding interrupt status will be set to 1 if the associated interrupt event occurs and the related enable bit is set to 1.

  • Page 174: Adc Interrupt Clear Register - Adciclr

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 ADC Interrupt Clear Register – ADCICLR This register provides the clear bits used to clear the interrupt raw and masked status of the ADC. These bits are set to 1 by software to clear the interrupt status and automatically cleared to 0 by hardware after being set to 1.

  • Page 175: General-Purpose Timer (Gptm)

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 General-Purpose Timer (GPTM) Introduction The General-Purpose Timer consists of one 16-bit up/down-counter, four 16-bit Capture/ Compare Registers (CCRs), one 16-bit Counter-Reload Register (CRR) and several control/status registers. It can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as single pulse generation or PWM output.

  • Page 176: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Features ▄ 16-bit up/down auto-reload counter ▄ 16-bit programmable prescaler that allows division of the counter clock frequency by any factor between 1 and 65536 ▄ Up to 4 independent channels for: ●...

  • Page 177: Functional Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Functional Descriptions Counter Mode Up-Counting In this mode the counter counts continuously from 0 to the counter-reload value, which is defined in the CRR register, in a count-up direction. Once the counter reaches the counter-reload value, the Timer Module generates an overflow event and the counter restarts to count once again from 0.

  • Page 178: Figure 31. Down-Counting Example

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Down-Counting In this mode the counter counts continuously from the counter-reload value, which is defined in the CRR register, to 0 in a count-down direction. Once the counter reaches 0, the Timer module generates an underflow event and the counter restarts to count once again from the counter-reload value.

  • Page 179: Figure 32. Center-Aligned Counting Example

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Center-Align Counting In the center-aligned counting mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The Timer module generates an overflow event when the counter counts to the counter-reload value in the up-counting mode and generates an underflow event when the counter counts to 0 in the down-counting mode.

  • Page 180: Clock Controller

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Clock Controller The following describes the Timer Module clock controller which determines the clock source of the internal prescaler counter. ▄ Internal APB clock f CLKIN The default internal clock source is the APB clock f...

  • Page 181: Trigger Controller

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Trigger Controller The trigger controller is used to select the trigger source and setup the trigger level or edge trigger condition. For the internal trigger input, it can be selected by the Trigger Selection bits TRSEL in the TRCFR register.

  • Page 182: Slave Controller

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Slave Controller The GPTM can be synchronized with an external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which is selected by the SMSEL field in the MDCFR register.

  • Page 183: Figure 37. Gptm In Pause Mode

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Pause Mode In the Pause Mode, the selected STI input signal level is used to control the counter start/stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level, here the counter will maintain its present value and will not be reset.

  • Page 184: Figure 38. Gptm In Trigger Mode

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Trigger Mode After the counter is disabled to count, the counter can resume counting when a STI rising edge signal occurs. When an STI rising edge occurs, the counter will start to count from the current value in the counter.

  • Page 185: Master Controller

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Master Controller The GPTMs and MCTMs can be linked together internally for timer synchronization or chaining. When one GPTM is configured to be in the Master Mode, the GPTM Master Controller will generate a Master Trigger Output (MTO) signal which includes a reset, a start, a stop signal or a clock source which is selected by the MMSEL field in the MDCFR register to trigger or drive another GPTM or MCTM, if exists, which is configured in the Slave Mode.

  • Page 186: Channel Controller

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Channel Controller The GPTM has four independent channels which can be used as capture inputs or compare match outputs. Each capture input or compare match output channel is composed of a preload register and a shadow register.

  • Page 187: Figure 42. Input Capture Mode

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Capture Counter Value Transferred to CHxCCR When the channel is used as a capture input, the counter value is captured into the Channel Capture/Compare Register (CHxCCR) when an effective input signal transition occurs. Once the capture event occurs, the CHxCCIF flag in the INTSR register is set accordingly.

  • Page 188: Figure 43. Pwm Pulse Width Measurement Example

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Pulse Width Measurement The input capture mode can be also used for pulse width measurement from signals on the GT_ CHx pins, TIx. The following example shows how to configure the GPTM operated in the input capture mode to measure the high pulse width and the input period on the GT_CH0 pin using channel 0 and channel 1.

  • Page 189: Input Stage

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Input Stage The input stage consists of a digital filter, a channel polarity selection, edge detection and a channel prescaler. The channel 0 input signal (TI0) can be chosen to come from the GT_CH0 signal or the Excusive-OR function of the GT_CH0, GT_CH1 and GT_CH2 signals.

  • Page 190: Figure 45. Channel 2 And Channel 3 Input Stages

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 TRCED CH2CCS CLKIN GT_CH2 TI2FP Filter TI2S2 Edge TI2S2ED fsampling TI2FN Detection CH2PSC TI2F CH2PRESCALER CH2P CH2CAP Event TI3S2 TI3S2ED Edge CH2PSC Detection TI2S3 Edge TI2S3ED Detection CH3P CH3PSC TI3FP GT_CH3 CH3PRESCALER...

  • Page 191: Quadrature Decoder

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Quadrature Decoder The Quadrature Decoder function uses two quadrantal inputs TI0 and TI1 derived from the GT_ CH0 and GT_CH1 pins respectively to interact to generate the counter value. The DIR bit is modified by hardware automatically during each input source transition. The input source can be either TI0 only, TI1 only or both TI0 and TI1, the selection made by setting the SMSEL field to 0x01, 0x02 or 0x03.

  • Page 192: Table 29. Counting Direction And Encoding Signals

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Table 29. Counting Direction and Encoding Signals TI0S0 TI1S1 Counting mode Level Rising Falling Rising Falling TI1S1 = High Down — — Counting on TI0 only (SMSEL = 0x01) TI1S1 = Low Down —...

  • Page 193: Output Stage

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Output Stage The GPTM has four channels for compare match, single pulse or PWM output function. The channel output GT_CHxO is controlled by the CHxOM, CHxP and CHxE bits in the corresponding CHxOCFR, CHPOLR and CHCTR registers.

  • Page 194: Figure 50. Toggle Mode Channel Output Reference Signal - Chxpre = 0

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Counter Value CHxOM=0x03, CHxPRE=0 (Output toggle, preload disable) CHxCCR (New value 2) CHxCCR (New value 3) CHxCCR (New value 1) CHxCCR Time Update CHxCCR value CHxOREF (Update Event) Figure 50. Toggle Mode Channel Output Reference Signal – CHxPRE = 0...

  • Page 195: Figure 52. Pwm Mode Channel Output Reference Signal And Counter In Up-Counting Mode

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Counter Value Counter Value Counter Value CHxCCR CHxCCR CHxCCR = 0x00 CHxOM = 0x06 100% CHxOREF CHxOREF CHxOREF CHxCCIF CHxCCIF CHxCCIF CHxOM = 0x07 CHxOREF Figure 52. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode...

  • Page 196: Figure 54. Pwm Mode Channel Output Reference Signal And Counter In Centre-Align Mode

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 CRR = 5 CMSEL= 0x01 Up-counting Down-counting CHxCCR = 3 CHxCCIF CHxCCR = 4 CHxCCIF CHxCCR >= 5 100% CHxCCIF CHxCCR = 0 CHxCCIF Figure 54. PWM Mode Channel Output Reference Signal and Counter in Centre-align Mode Rev.

  • Page 197: Update Management

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Update Management The Update event is used to update the CRR, the PSCR, the CHxACR and the CHxCCR values from the actual registers to the corresponding shadow registers. An update event occurs when the counter overflows or underflows, the software update control bit is triggered or an update event from the slave controller is generated.

  • Page 198: Single Pulse Mode

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Single Pulse Mode Once the timer is set to operate in the single pulse mode, it is not necessary to set the timer enable bit TME in the CTR register to 1 to enable the counter. The trigger to generate a pulse can be sourced from the STI signal rising edge or by setting the TME bit to 1 using software.

  • Page 199: Figure 57. Immediate Active Mode Minimum Delay

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 In the Single Pulse mode, the STI active edge which sets the TME bit to 1 will enable the counter. However, there exist several clock delays to perform the comparison result between the counter value and the CHxCCR value. In order to reduce the delay to a minimum value, the user can set the CHxIMAE bit in each CHxOCFR register.

  • Page 200: Asymmetric Pwm Mode

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Asymmetric PWM Mode The asymmetric PWM mode allows two center-aligned PWM signals to be generated with a programmable phase shift. The PWM frequency is determined by the value of the CRR register while the duty cycle and the phase-shift are determined by the CHxCCR and CHxACR register.

  • Page 201: Trigger Adc Start

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Trigger ADC Start To interconnect to the Analog-to-Digital Converter, the GPTM can output the MTO signal or the channel compare match output signal CHxOREF (x = 0 ~ 3) to be used as an Analog-to-Digital Converter input trigger signal.

  • Page 202: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Register Descriptions Timer Counter Configuration Register – CNTCFR This register specifies the GPTM counter configuration. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CMSEL Type/Reset 0 RW Reserved CKDIV Type/Reset 0 RW...

  • Page 203: Timer Mode Configuration Register - Mdcfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions UEVDIS Update event Disable control 0: Enable the update event request by one of following events: - Counter overflow/underflow - Setting the UEVG bit - Update generation through the slave mode...
  • Page 204 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions [18:16] MMSEL Master Mode Selection Master mode selection is used to select the MTO signal source which is used to synchronize the other slave timer. MMSEL [2:0] Mode Descriptions...
  • Page 205 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions [10:8] SMSEL Slave Mode Selection SMSEL [2:0] Mode Descriptions The prescaler is clocked directly by the internal Disable mode clock. The counter uses the clock pulse generated from the interaction between the TI0 and Quadrature Decoder TI1 signals to drive the counter prescaler.

  • Page 206: Timer Trigger Configuration Register - Trcfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Timer Trigger Configuration Register – TRCFR This register specifies the GPTM trigger source selection. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved TRSEL Type/Reset 0 RW 0 RW...

  • Page 207: Timer Counter Register - Ctr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Timer Counter Register – CTR This register specifies the timer enable bit (TME) and CRR buffer enable bit (CRBE). Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CRBE...

  • Page 208: Channel 0 Input Configuration Register - Ch0Icfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Channel 0 Input Configuration Register – CH0ICFR This register specifies the channel 0 input mode configuration. Offset: 0x020 Reset value: 0x0000_0000 TI0SRC Reserved Type/Reset Reserved CH0PSC CH0CCS Type/Reset 0 RW 0 RW...

  • Page 209: Channel 1 Input Configuration Register - Ch1Icfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions [3:0] TI0F Channel 0 Input Source TI0 Filter Setting These bits define the frequency divided ratio used to sample the TI0 signal. The Digital filter in the GPTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
  • Page 210 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions [17:16] CH1CCS Channel 1 Capture/Compare Selection 00: Channel 1 is configured as an output 01: Channel 1 is configured as an input derived from the TI1 signal 10: Channel 1 is configured as an input derived from the TI0 signal...

  • Page 211: Channel 2 Input Configuration Register - Ch2Icfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Channel 2 Input Configuration Register – CH2ICFR This register specifies the channel 2 input mode configuration. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CH2PSC CH2CCS Type/Reset 0 RW 0 RW 0 RW...

  • Page 212: Channel 3 Input Configuration Register - Ch3Icfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions [3:0] TI2F Channel 2 Input Source TI2 Filter Setting These bits define the frequency divided ratio used to sample the TI2 signal. The Digital filter in the GPTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
  • Page 213 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions [17:16] CH3CCS Channel 3 Capture/Compare Selection 00: Channel 3 is configured as an output 01: Channel 3 is configured as an input derived from the TI3 signal 10: Channel 3 is configured as an input derived from the TI2 signal...

  • Page 214: Channel 0 Output Configuration Register - Ch0Ocfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Channel 0 Output Configuration Register – CH0OCFR This register specifies the channel 0 output mode configuration. Offset: 0x040 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH0OM[3] Type/Reset Reserved CH0IMAE CH0PRE Reserved...
  • Page 215 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions [8][2:0] CH0OM[3:0] Channel 0 Output Mode Setting These bits define the functional types of the output reference signal CH0OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...

  • Page 216: Channel 1 Output Configuration Register - Ch1Ocfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Channel 1 Output Configuration Register – CH1OCFR This register specifies the channel 1 output mode configuration. Offset: 0x044 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH1OM[3] Type/Reset Reserved CH1IMAE CH1PRE Reserved...

  • Page 217: Channel 2 Output Configuration Register - Ch2Ocfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions [8][2:0] CH1OM[3:0] Channel 1 Output Mode Setting These bits define the functional types of the output reference signal CH1OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
  • Page 218 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions CH2IMAE Channel 2 Immediate Active Enable 0: No action 1: Single pulse Immediate Active Mode is enabled The CH2OREF will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH2CCR values.

  • Page 219: Channel 3 Output Configuration Register - Ch3Ocfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Channel 3 Output Configuration Register – CH3OCFR This register specifies the channel 3 output mode configuration. Offset: 0x04C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH3OM[3] Type/Reset Reserved CH3IMAE CH3PRE Reserved...
  • Page 220 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions [8][2:0] CH3OM[3:0] Channel 3 Output Mode Setting These bits define the functional types of the output reference signal CH3OREF 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...

  • Page 221: Channel Control Register - Chctr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Channel Control Register – CHCTR This register contains the channel capture input or compare output function enable control bits. Offset: 0x050 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3E...

  • Page 222: Channel Polarity Configuration Register - Chpolr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Channel Polarity Configuration Register – CHPOLR This register contains the channel capture input or compare output polarity control. Offset: 0x054 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3P Reserved...

  • Page 223: Timer Interrupt Control Register - Dictr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Timer Interrupt Control Register – DICTR This register contains the timer interrupt enable control bits. Offset: 0x074 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVIE Reserved UEVIE Type/Reset Reserved CH3CCIE CH2CCIE...

  • Page 224: Timer Event Generator Register - Evgr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Timer Event Generator Register – EVGR This register contains the software event generation bits. Offset: 0x078 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVG Reserved UEVG Type/Reset Reserved CH3CCG CH2CCG CH1CCG...

  • Page 225: Timer Interrupt Status Register - Intsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions CH1CCG Channel 1 Capture/Compare Generation A Channel 1 capture/compare event can be generated by setting this bit. It is cleared by hardware automatically. 0: No action 1: Capture/compare event is generated on channel 1 If Channel 1 is configured as an input, the counter value is captured into the CH1CCR register and then the CH1CCIF bit is set.
  • Page 226 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions UEVIF Update Event Interrupt Flag. This bit is set by hardware on an update event and is cleared by software. 0: No update event occurs 1: Update event occurs...

  • Page 227: Timer Counter Register - Cntr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions CH1CCIF Channel 1 Capture/Compare Interrupt Flag - Channel 1 is configured as an output: 0: No match event occurs 1: The contents of the counter CNTR have matched the contents of the CH1CCR...

  • Page 228: Timer Prescaler Register - Pscr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Timer Prescaler Register – PSCR This register specifies the timer prescaler value to generate the counter clock. Offset: 0x084 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PSCV Type/Reset 0 RW 0 RW...

  • Page 229: Timer Counter Reload Register - Crr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Timer Counter Reload Register – CRR This register specifies the timer counter reload value. Offset: 0x088 Reset value: 0x0000_FFFF Reserved Type/Reset Reserved Type/Reset Type/Reset 1 RW 1 RW 1 RW 1 RW...

  • Page 230: Channel 0 Capture/Compare Register - Ch0Ccr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Channel 0 Capture/Compare Register – CH0CCR This register specifies the timer channel 0 capture/compare value. Offset: 0x090 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH0CCV Type/Reset 0 RW 0 RW 0 RW...

  • Page 231: Channel 1 Capture/Compare Register - Ch1Ccr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Channel 1 Capture/Compare Register – CH1CCR This register specifies the timer channel 1 capture/compare value. Offset: 0x094 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH1CCV Type/Reset 0 RW 0 RW 0 RW...

  • Page 232: Channel 2 Capture/Compare Register - Ch2Ccr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Channel 2 Capture/Compare Register – CH2CCR This register specifies the timer channel 2 capture/compare value. Offset: 0x098 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2CCV Type/Reset 0 RW 0 RW 0 RW...

  • Page 233: Channel 3 Capture/Compare Register - Ch3Ccr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Channel 3 Capture/Compare Register – CH3CCR This register specifies the timer channel 3 capture/compare value. Offset: 0x09C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH3CCV Type/Reset 0 RW 0 RW 0 RW...

  • Page 234: Channel 0 Asymmetric Compare Register - Ch0Acr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Channel 0 Asymmetric Compare Register – CH0ACR This register specifies the timer channel 0 asymmetric compare value. Offset: 0x0A0 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH0ACV Type/Reset 0 RW 0 RW...

  • Page 235: Channel 2 Asymmetric Compare Register - Ch2Acr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Channel 2 Asymmetric Compare Register – CH2ACR This register specifies the timer channel 2 asymmetric compare value. Offset: 0x0A8 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2ACV Type/Reset 0 RW 0 RW...

  • Page 236: Basic Function Timer (Bftm)

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Basic Function Timer (BFTM) Introduction The Basic Function Timer Module, BFTM, is a 32-bit up-counting counter designed to measure time intervals, generate one shot pulses or generate repetitive interrupts. The BFTM can operate in two modes which are repetitive and one shot modes.

  • Page 237: Functional Description

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Functional Description The BFTM is a 32-bit up-counting counter which is driven by the BFTM APB clock, PCLK. The counter value can be changed or read at any time even when the timer is counting. The BFTM supports two operating modes known as the repetitive mode and one shot mode allowing the measurement of time intervals or the generation of periodic time durations.

  • Page 238: One Shot Mode

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 One Shot Mode By setting the OSM bit in BFTMCR register to 1, the BFTM will operate in the one shot mode. The BFTM starts to count when the CEN bit is set to 1 by the application program. The counter value will remain unchanged if the CEN bit is cleared to 0 by the application program.

  • Page 239: Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Register Map The following table shows the BFTM registers and their reset values. Table 33. BFTM Register Map Register Offset Description Reset Value BFTMCR 0x000 BFTM Control Register 0x0000_0000 BFTMSR 0x004 BFTM Status Register...

  • Page 240: Bftm Status Register - Bftmsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 BFTM Status Register – BFTMSR This register specifies the BFTM status. Offset: 0x004 Reset value: 0x0000_0004 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Bits Field Descriptions BFTM Compare Match Interrupt Flag...

  • Page 241: Bftm Counter Register - Bftmcntr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 BFTM Counter Register – BFTMCNTR This register specifies the BFTM counter value. Offset: 0x008 Reset value: 0x0000_0000 Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW...

  • Page 242: Single-Channel Timer (Sctm)

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Single-Channel Timer (SCTM) Introduction The Single-Channel Timer consists of one 16-bit up-counter, one 16-bit Capture/Compare Registers (CCRs), one 16-bit Counter-Reload Register (CRR) and several control/status registers. It can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as single pulse generation or PWM output.

  • Page 243: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Features ▄ 16-bit auto-reload up counter ▄ 16-bit programmable prescaler that allows division of the counter clock frequency by any factor between 1 and 65536 ▄ Single channel for: ● Input Capture function ●...

  • Page 244: Clock Controller

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Clock Controller The following describes the Timer Module clock controller which determines the clock source of the internal prescaler counter. ▄ Internal APB clock f CLKIN The default internal clock source is the APB clock f...

  • Page 245: Trigger Controller

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Trigger Controller The trigger controller is used to select the trigger source and setup the trigger level or edge trigger condition. For the internal trigger input, it can be selected by the Trigger Selection bits TRSEL in the TRCFR register.

  • Page 246: Slave Controller

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Slave Controller The SCTM can be synchronized with an external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which is selected by the SMSEL field in the MDCFR register.

  • Page 247: Figure 69. Sctm In Pause Mode

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Pause Mode In the Pause Mode, the selected STI input signal level is used to control the counter start/stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level, here the counter will maintain its present value and will not be reset.

  • Page 248: Channel Controller

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Channel Controller The SCTM channel can be used as the capture input or compare match output. The capture input or compare match output channel is composed of a preload register and a shadow register. The Data access of the APB bus is always through the read/write preload register.

  • Page 249: Input Stage

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Input Stage The input stage consists of a digital filter, a channel polarity selection, edge detection and a channel prescaler. The channel input signal (TI) is sampled by a digital filter to generate a filtered input signal TIFP.

  • Page 250: Output Stage

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Output Stage The SCTM output has functions for compare match, single pulse or PWM output. The channel output SCTM_CHO is controlled by the CHOM, CHP and CHE bits in the corresponding CHOCFR, CHPOLR and CHCTR registers.

  • Page 251: Figure 76. Toggle Mode Channel Output Reference Signal - Chpre = 0

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Counter Value CHOM=0x03, CHPRE=0 (Output toggle, preload disable) CHCCR (New value 2) CHCCR (New value 3) CHCCR (New value 1) CHCCR Time Update CHCCR value CHOREF (Update Event) Figure 76. Toggle Mode Channel Output Reference Signal – CHPRE = 0...

  • Page 252: Update Management

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Counter Value Counter Value Counter Value CHCCR CHCCR CHCCR = 0x00 CHOM = 0x06 100% CHOREF CHOREF CHOREF CHCCIF CHCCIF CHCCIF CHOM = 0x07 CHOREF Figure 78. PWM Mode Channel Output Reference Signal...

  • Page 253: Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Update Event Management Counter Overflow UEVG UEV (Update PSCR, CRR, CHCCR Shadow Registers) Slave Restart mode UEVDIS Update Event Interrupt Management Counter Overflow UEV interrupt UEVG UEVDIS Slave Restart mode UGDIS Figure 79. Update Event Setting Diagram Register Map The following table shows the SCTM registers and reset values.

  • Page 254: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Register Descriptions Timer Counter Configuration Register – CNTCFR This register specifies the SCTM counter configuration. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CKDIV Type/Reset 0 RW Reserved UGDIS UEVDIS...

  • Page 255: Timer Mode Configuration Register - Mdcfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Timer Mode Configuration Register – MDCFR This register specifies the SCTM slave mode selection. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved SMSEL Type/Reset 0 RW 0 RW Reserved Type/Reset...

  • Page 256: Timer Trigger Configuration Register - Trcfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Timer Trigger Configuration Register – TRCFR This register specifies the SCTM trigger source selection. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved TRSEL Type/Reset 0 RW 0 RW...

  • Page 257: Timer Counter Register - Ctr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Timer Counter Register – CTR This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE). Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CRBE Type/Reset...

  • Page 258: Channel Input Configuration Register - Chicfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Channel Input Configuration Register – CHICFR This register specifies the channel input mode configuration. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CHPSC CHCCS Type/Reset 0 RW 0 RW 0 RW Reserved...
  • Page 259 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions [3:0] Channel Input Source TI Filter Setting These bits define the frequency divided ratio used to sample the TI signal. The Digital filter in the SCTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.

  • Page 260: Channel Output Configuration Register - Chocfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Channel Output Configuration Register – CHOCFR This register specifies the channel output mode configuration. Offset: 0x040 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CHPRE Reserved CHOM[2:0] Type/Reset 0 RW...

  • Page 261: Channel Control Register - Chctr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Channel Control Register – CHCTR This register contains the channel capture input or compare output function enable control bit. Offset: 0x050 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset...

  • Page 262: Channel Polarity Configuration Register - Chpolr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Channel Polarity Configuration Register – CHPOLR This register contains the channel capture input or compare output polarity control bit. Offset: 0x054 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset...

  • Page 263: Timer Interrupt Control Register - Dictr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Timer Interrupt Control Register – DICTR This register contains the timer interrupt enable control bits. Offset: 0x074 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVIE Reserved UEVIE Type/Reset Reserved CHCCIE Type/Reset...

  • Page 264: Timer Event Generator Register - Evgr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Timer Event Generator Register – EVGR This register contains the software event generation bits. Offset: 0x078 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVG Reserved UEVG Type/Reset Reserved CHCCG Type/Reset Bits...

  • Page 265: Timer Interrupt Status Register - Intsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Timer Interrupt Status Register – INTSR This register stores the timer interrupt status. Offset: 0x07C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVIF Reserved UEVIF Type/Reset Reserved CHOCF Reserved CHCCIF Type/Reset...

  • Page 266: Timer Counter Register - Cntr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Timer Counter Register – CNTR This register stores the timer counter value. Offset: 0x080 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CNTV Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...

  • Page 267: Timer Counter Reload Register - Crr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Timer Counter Reload Register – CRR This register specifies the timer counter reload value. Offset: 0x088 Reset value: 0x0000_FFFF Reserved Type/Reset Reserved Type/Reset Type/Reset 1 RW 1 RW 1 RW 1 RW...

  • Page 268: Channel Capture/Compare Register - Chccr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Channel Capture/Compare Register – CHCCR This register specifies the timer channel capture/compare value. Offset: 0x090 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CHCCV Type/Reset 0 RW 0 RW 0 RW 0 RW...

  • Page 269: Watchdog Timer (Wdt)

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Watchdog Timer (WDT) Introduction The Watchdog timer is a hardware timing circuitry that can be used to detect a system lock-up due to software trapped in a deadlock. The Watchdog timer can operate in a reset mode. The Watchdog timer will generate a reset when the counter counts down to a zero value.

  • Page 270: Functional Description

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Functional Description The Watchdog timer is formed from a 12-bit count-down counter and a fixed 3-bit prescaler. The largest time-out period is 16 seconds, using the LSI clock and a 1/128 maximum prescaler value.

  • Page 271: Figure 81. Watchdog Timer Behavior

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 The Watchdog timer should be used in the following manners: ▄ Set the Watchdog timer reload value (WDTV) and reset in the WDTMR0 register. ▄ Set the Watchdog timer delta value (WDTD) and prescaler in the WDTMR1 register.

  • Page 272: Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Register Map The following table shows the Watchdog Timer registers and reset values. Table 36. Watchdog Timer Register Map Register Offset Description Reset Value WDTCR 0x000 Watchdog Timer Control Register 0x0000_0000 WDTMR0...

  • Page 273: Watchdog Timer Mode Register 0 - Wdtmr0

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Watchdog Timer Mode Register 0 – WDTMR0 This register specifies the Watchdog timer counter reload value and reset enable control. Offset: 0x004 Reset value: 0x0000_0FFF Reserved Type/Reset Reserved WDTEN Type/Reset WDTSHLT WDTRSTEN Reserved...

  • Page 274: Watchdog Timer Mode Register 1 - Wdtmr1

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Watchdog Timer Mode Register 1 – WDTMR1 This register specifies the Watchdog delta value and the prescaler selection. Offset: 0x008 Reset value: 0x0000_7FFF Reserved Type/Reset Reserved Type/Reset Reserved WPSC WDTD Type/Reset 1 RW...

  • Page 275: Watchdog Timer Status Register - Wdtsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Watchdog Timer Status Register – WDTSR This register specifies the Watchdog timer status. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved WDTERR WDTUF Type/Reset 0 WC Bits Field...

  • Page 276: Watchdog Timer Protection Register - Wdtpr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Watchdog Timer Protection Register – WDTPR This register specifies the Watchdog timer protect key configuration. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PROTECT Type/Reset 0 RW 0 RW 0 RW...

  • Page 277: Watchdog Timer Clock Selection Register - Wdtcsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Watchdog Timer Clock Selection Register – WDTCSR This register specifies the Watchdog timer clock source selection and lock configuration. Offset: 0x018 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved WDTLOCK...

  • Page 278: Inter-Integrated Circuit (I C)

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Inter-Integrated Circuit (I Introduction The I C Module is an internal circuit allowing communication with an external I C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line, SDA, and a serial clock line, SCL.

  • Page 279: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Features ▄ Two-wire I C serial interface ● Serial data line (SDA) and serial clock (SCL) ▄ Multiple speed modes ● Standard mode – 100 kHz ● Fast mode – 400 kHz ●...

  • Page 280: Data Validity

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 STOP Condition START Condition Figure 83. START and STOP Condition Data Validity The data on the SDA line must be stable during the high period of the SCL clock. The SDA data state can only be changed when the clock signal on the SCL line is in a low state.

  • Page 281: Addressing Format

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Addressing Format The I C interface starts to transfer data after the master device has sent the address to confirm the targeted slave device. The address frame is sent just after the START signal by master device. The addressing mode selection bit named ADRM in the I2CCR register should be defined to choose either the 7-bit or 10-bit addressing mode.

  • Page 282: Figure 86. 10-Bit Addressing Write Transmit Mode

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 10-bits Address Format In order to prevent address clashes, due to the limited range of the 7-bit addresses, a new 10-bit address scheme has been introduced. This enhancement can be mixed with the 7-bit addressing mode which increases the available address range about ten times.

  • Page 283: Data Transfer And Acknowledge

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Data Transfer and Acknowledge Once the slave device address has been matched, the data can be transmitted to or received from the slave device according to the transfer direction specified by the R/W bit. Each byte is followed by an acknowledge bit on the 9 SCL clock.

  • Page 284: Clock Synchronization

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Clock Synchronization Only one master device can generate the SCL clock under normal operation. However when there is more than one master trying to generate the SCL clock, the clock should be synchronized so that the data output can be compared.

  • Page 285: General Call Addressing

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 General Call Addressing The general call addressing function can be used to address all the devices connected to the I bus. The master device can activate the general call function by writing a value “00” into the TAR and setting the RWD bit to 0 in the I2CTAR register on the addressing frame.

  • Page 286: Figure 91. Master Transmitter Timing Diagram

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Master Transmitter Mode Start condition Users write the target slave device address and communication direction into the I2CTAR register after setting the I2CEN bit in the I2CCR register. The STA flag in the I2CSR register is set by hardware after a start condition occurs.
  • Page 287 ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Master Receiver Mode Start condition The target slave device address and communication direction must be written into the I2CTAR register. The STA flag in the I2CSR register is set by hardware after a start condition occurs. In order to send the following address frame, the STA flag must be cleared to 0 if it has been set to 1.The...

  • Page 288: Figure 92. Master Receiver Timing Diagram

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Close / Continue Transmission The master device needs to reset the AA bit in the I2CCR register to send a NACK signal to the slave device before the last data byte transfer has been completed. After the last data byte has been received from the slave device, the master device will hold the SCL line at a logic low state following after a NACK signal sent by the master device to the slave device.

  • Page 289: Figure 93. Slave Transmitter Timing Diagram

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Slave Transmitter Mode Address Frame In the 7-bit addressing mode, the ADRS bit in the I2CSR register is set after the slave device receives the calling address which matches with the slave device address. In the 10-bit addressing mode, the ADRS bit is set when the first header byte is matched and the second address byte is matched respectively.

  • Page 290: Figure 94. Slave Receiver Timing Diagram

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Slave Receiver Mode Address Frame The ADRS bit in the I2CSR register is set after the slave device receives the calling address which matches with the slave device address. After the ADRS bit has been set to 1, it must be cleared to 0 to continue the data transfer process.

  • Page 291: Conditions Of Holding Scl Line

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Conditions of Holding SCL Line The following conditions will cause the SCL line to be held at a logic low state by hardware resulting in all the I C transfers being stopped. Data transfer will be continued after the creating conditions are eliminated.

  • Page 292: I 2 C Timeout Function

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 C Timeout Function In order to reduce the occurrence of I C lockup problem due to the reception of erroneous clock source, a timeout function is provided. If the I C bus clock source is not received for a certain timeout period, then a corresponding I C timeout flag will be asserted.

  • Page 293: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Register Descriptions C Control Register – I2CCR This register specifies the corresponding I C function enable control. Offset: 0x000 (0) Reset value: 0x0000_2000 Reserved Type/Reset Reserved Type/Reset SEQFILTER COMBFILTEREn ENTOUT Reserved Type/Reset...

  • Page 294: I 2 C Interrupt Enable Register - I2Cier

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions GCEN General Call Enable 0: General call disabled 1: General call enabled When the device receives the calling address with a value of 0x00 and if both the GCEN and the AA bits are set to 1, then the I C interface is addressed as a slave and the GCS bit in the I2CSR register is set to 1.
  • Page 295 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions [16] RXDNEIE Data Register Not Empty Interrupt Enable Bit in Received Mode 0: Interrupt disabled 1: Interrupt enabled When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by hardware.

  • Page 296: I 2 C Address Register - I2Caddr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 C Address Register – I2CADDR This register specifies the I C device address. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved ADDR Type/Reset 0 RW ADDR Type/Reset 0 RW 0 RW...

  • Page 297: I 2 C Status Register - I2Csr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 C Status Register – I2CSR This register contains the I C operation status. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved TXNRX MASTER BUSBUSY RXBF TXDE RXDNE Type/Reset 0 RO 0 RO...
  • Page 298 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions [17] TXDE Data Register Empty Using in Transmitter Mode 0: Data register I2CDR not empty 1: Data register I2CDR empty This bit is set when the I2CDR register is empty in the Transmitter mode. Note that the TXDE bit will be set after the address frame is being transmitted to inform that the data to be transmitted should be loaded into the I2CDR register.
  • Page 299 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions ADRS Address Transmit (master mode) / Address Receive (slave mode) Flag Address Sent in Master Mode 0: Address frame has not been transmitted 1: Address frame has been transmitted For the 7-bit addressing mode, this bit is set after the master device receives the address frame acknowledge bit sent from the slave device.

  • Page 300: I 2 C Scl High Period Generation Register - I2Cshpgr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 C SCL High Period Generation Register – I2CSHPGR This register specifies the I C SCL clock high period interval. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset SHPG Type/Reset 0 RW...

  • Page 301: I 2 C Scl Low Period Generation Register - I2Cslpgr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 C SCL Low Period Generation Register – I2CSLPGR This register specifies the I C SCL clock low period interval. Offset: 0x014 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset SLPG Type/Reset 0 RW...

  • Page 302: C Data Register - I2Cdr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Table 39. I C Clock Setting Example × [ (SHPG + d) + (SLPG + d) ] (where d = 6) PCLK SHPG + SLPG value at PCLK C Clock 8 MHz...

  • Page 303: I 2 C Target Register - I2Ctar

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 C Target Register – I2CTAR This register specifies the target device address to be communicated. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset 0 RW 0 RW Type/Reset 0 RW...

  • Page 304: I 2 C Address Mask Register - I2Caddmr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 C Address Mask Register – I2CADDMR This register specifies which bit of the I C address is masked and not compared with corresponding bit of the received address frame. Offset: 0x020 Reset value: 0x0000_0000...

  • Page 305: I 2 C Address Snoop Register - I2Caddsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 C Address Snoop Register – I2CADDSR This register is used to indicate the address frame value appeared on the I C bus. Offset: 0x024 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved...

  • Page 306: I 2 C Timeout Register - I2Ctout

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 C Timeout Register – I2CTOUT This register specifies the I C Timeout counter preload value and clock prescaler ratio. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset 0 RW 0 RW...

  • Page 307: Serial Peripheral Interface (Spi)

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Serial Peripheral Interface (SPI) Introduction The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive functions in both master or slave mode. The SPI interface uses 4 pins, among which are serial data input and output lines MISO and MOSI, the clock line SCK, and the slave select line SEL.

  • Page 308: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Features ▄ Master or slave mode ▄ Master mode speed up to f PCLK ▄ Slave mode speed up to f PCLK ▄ Programmable data frame length up to 16 bits ▄...

  • Page 309: Spi Serial Frame Format

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 SPI Serial Frame Format The SPI interface format is base on the Clock Polarity, CPOL, and the Clock Phase, CPHA, configurations. ▄ Clock Polarity Bit – CPOL When the Clock Polarity bit is cleared to 0, the SCK line idle state is LOW. When the Clock Polarity bit is set to 1, the SCK line idle state is HIGH.

  • Page 310: Figure 98. Spi Continuous Data Transfer Timing Diagram - Cpol = 0, Cpha = 0

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Figure 101 shows the continuous data transfer timing diagram of this format. Note that the SEL signal must change to an inactive level between each data frame. SEL (SELAP=0) SEL (SELAP=1) MOSI/MISO...

  • Page 311: Figure 100. Spi Continuous Transfer Timing Diagram - Cpol = 0, Cpha = 1

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Figure 103 shows the continuous data transfer diagram timing. Note that the SEL signal must remain active until the last data transfer has completed. SEL (SELAP=0) SEL (SELAP=1) MOSI/MISO Data1 Data2 Figure 100. SPI Continuous Transfer Timing Diagram – CPOL = 0, CPHA = 1...

  • Page 312: Figure 102. Spi Continuous Transfer Timing Diagram - Cpol = 1, Cpha = 0

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Figure 105 shows the continuous data transfer timing of this format. Note that the SEL signal must change to an inactive level between each data frame. SEL (SELAP=0) SEL (SELAP=1) ½ SCK ½...

  • Page 313: Status Flags

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Status Flags TX Buffer Empty – TXBE This TXBE flag is set when the TX buffer is empty in the non-FIFO mode or when the TX FIFO data length is equal to or less than the TX FIFO threshold level as defined by the TXFTLS field in the SPIFCR register in the FIFO mode.

  • Page 314: Table 41. Spi Mode Fault Trigger Conditions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 MOSI MOSI Master Master MISO MISO I/O 0 I/O 0 I/O 1 I/O 1 I/O 2 I/O 2 MOSI Slave MISO MOSI Slave MISO Figure 105. SPI Multi-Master Slave Environment Table 41. SPI Mode Fault Trigger Conditions...

  • Page 315: Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Write Collision – WC The following conditions will assert the Write Collision Flag. ▄ The FIFOEN bit in the SPIFCR register is cleared. The write collision flag is asserted when new data is written into the SPIDR register while both the TX buffer and the shift register are already full.

  • Page 316: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Register Descriptions SPI Control Register 0 – SPICR0 This register specifies the SEL control and the SPI enable bits. offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset SELHT GUADT Type/Reset 0 RW...

  • Page 317: Spi Control Register 1 - Spicr1

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions SSELC Software Slave Select Control 0: Set the SEL output to an inactive state 1: Set the SEL output to an active state The application Software can setup the SEL output to an active or inactive state by configuring the SSELC bit.
  • Page 318 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions [13] SELM Slave Select Mode 0: SEL signal is controlled by software – asserted or de-asserted by the SSELC 1: SEL signal is controlled by hardware – generated automatically by the SPI hardware Note that SELM bit is available for master mode only –...

  • Page 319: Spi Interrupt Enable Register - Spiier

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 SPI Interrupt Enable Register – SPIIER This register contains the corresponding SPI interrupt enable control bit. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset TOIEN SAIEN MFIEN ROIEN WCIEN...

  • Page 320: Spi Clock Prescaler Register - Spicpr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions TXBEIEN TX Buffer Empty Interrupt Enable 0: Disable 1: Enable The TX buffer empty interrupt request will be generated when the TXBE flag and the TXBEIEN bit are set. In the FIFO mode, the interrupt request being generated depends upon the TX FIFO trigger level setting.

  • Page 321: Spi Data Register - Spidr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 SPI Data Register – SPIDR This register stores the SPI received or transmitted Data. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Type/Reset 0 RW 0 RW 0 RW 0 RW...
  • Page 322 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions BUSY SPI Busy flag 0: SPI not busy 1: SPI busy In the master mode, this flag is reset when the TX buffer and TX shift register are both empty and is set when the TX buffer or the TX shift register are not empty.

  • Page 323: Spi Fifo Control Register - Spifcr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 SPI FIFO Control Register – SPIFCR This register contains the related SPI FIFO control including the FIFO enable control and the FIFO trigger level selections. Offset: 0x018 Reset value: 0x0000_0000 Reserved Type/Reset...

  • Page 324: Spi Fifo Status Register - Spifsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 SPI FIFO Status Register – SPIFSR This register contains the relevant SPI FIFO status. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset RXFS TXFS Type/Reset 0 RO 0 RO...

  • Page 325: Spi Fifo Time Out Counter Register - Spiftocr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 SPI FIFO Time Out Counter Register – SPIFTOCR This register stores the SPI RX FIFO time out counter value. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Type/Reset 0 RW 0 RW...

  • Page 326: Universal Synchronous Asynchronous Receiver Transmitter (Usart)

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Universal Synchronous Asynchronous Receiver Transmitter (USART) Introduction The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. The USART is used to translate data between parallel and serial interfaces, and is also commonly used for RS232 standard communication.

  • Page 327: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Features ▄ Supports both asynchronous and clocked synchronous serial communication modes ▄ Full Duplex Communication Capability ▄ Programming baud rate up to 3 Mbit/s for asynchronous mode and 6 Mbit/s for synchronous mode ▄...

  • Page 328: Function Descriptions

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Function Descriptions Serial Data Format The USART module performs a parallel-to-serial conversion on data that is written to the transmit FIFO registers and then sends the data with the following format: Start bit, 7 ~ 9 LSB first data bits, optional Parity bit and finally 1 ~ 2 Stop bits.

  • Page 329: Baud Rate Generation

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Baud Rate Generation The baud rate for the USART receiver and transmitter are both set with the same values. The baud- rate divisor, BRD, has the following relationship with the USART clock which is known as CK_ USART.

  • Page 330: Table 45. Baud Rate Deviation Error Calculation - Ck_Usart = 20 Mhz

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Table 45. Baud Rate Deviation Error Calculation – CK_USART = 20 MHz Baud rate CK_USART = 20 MHz Kbps Actual Deviation Error rate 8333 0.00% 2083 0.02% 19.2 19.2 1042 -0.03% 57.6 57.6...

  • Page 331: Hardware Flow Control

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Hardware Flow Control The USART supports the hardware flow control function which is enabled by setting the HFCEN bit in the USRCR register to 1. It is possible to control the serial data flow between 2 USART devices by using the CTS input and the RTS output.

  • Page 332: Irda

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 CTS Flow Control If the hard flow control function is enabled, the URTXEN bit in the USRCR register will be controlled by the USART CTS input signal. If the USART CTS pin is forced to a logic low state, the URTXEN bit will automatically be set to 1 to enable the data transmission.

  • Page 333: Figure 112. Irda Modulation And Demodulation

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Data Frame START STOP TX_Data IrDA TX Modulation Signal bit width 3/16 bit width IrDA RX Demodulation Signal Data Frame STOP START RX_Data Figure 112. IrDA Modulation and Demodulation The IrDA mode provides two operation modes, one is the normal mode and the other is the low- power mode.
  • Page 334 Cortex ® -M0+ MCU HT32F52220/HT32F52230 IrDA Normal Mode For the IrDA normal mode, the width of each transmitted pulse generated by the transmitter modulator is specified as 3/16 of the baud rate clock period. The receiver pulse width for the IrDA receiver demodulator is based on the IrDA receive debounce filter which is implemented using an 8-bit down-counting counter.

  • Page 335: Rs485 Mode

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 TX_Data Transmitter Modulation TXSEL RX_Data Receiver Demodulation IrDAEN Figure 113. USART I/O and IrDA Block Diagram RS485 Mode The RS485 mode of the USART provides the data transmission on the interface transmitted over a 2-wire twisted pair bus.

  • Page 336: Figure 114. Rs485 Interface And Waveform

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 RS-485 Transceiver Differential USART TG = 4 Reference Divisor Clock Stop D6 D7 Parity Start D1 D2 D3 D4 D5 TXENP =0 TXENP =1 Figure 114. RS485 Interface and Waveform Rev. 1.10...
  • Page 337 Cortex ® -M0+ MCU HT32F52220/HT32F52230 RS485 Normal Multi-drop Operation Mode – NMM When the RS485 mode is configured as an addressable slave, it will operate in the Normal Multi- drop Operation Mode, NMM. This mode is enabled when the RSNMM field is set in the RS485CR register.

  • Page 338: Synchronous Master Mode

    ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Synchronous Master Mode The data is transmitted in a full-duplex style in the USART Synchronous Master Mode, i.e., data transmission and reception both occur at the same time and only support master mode. The USART CTS pin is the synchronous USART transmitter clock output.

  • Page 339: Figure 116. 8-Bit Format Usart Synchronous Waveform

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 (CPS=1, WLS[1:0]=0x01, PBE=0) Clock (CPO=0) Clock (CPO=1) USART TX (From Start Stop Master to Slave) USART RX (From Slave to Master) (CPS=1, WLS[1:0]=0x00, PBE=1) Clock (CPO=0) Clock (CPO=1) USART TX (From Start...

  • Page 340: Interrupts And Status

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Interrupts and Status The UART can generate interrupts when the following event occurs and corresponding interrupt enable bits are set: ▄ Receive FIFO time-out interrupt: An interrupt will be generated when the USART receive FIFO does not receive a new data packet during the specified time-out interval.

  • Page 341: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Register Descriptions USART Data Register – USRDR The register is used to access the USART transmitted and received FIFO data. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Type/Reset...

  • Page 342: Usart Control Register - Usrcr

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 USART Control Register – USRCR The register specifies the parameters such as the data length, parity and stop bit for the USART. It also contains the USART enable control bits together with the USART mode and data transfer mode selections.
  • Page 343 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions [11] Parity Bit Enable 0: Parity bit is not generated (transmitted data) or checked (receive data) during transfer 1: Parity bit is generated or checked during transfer Note: When the WLS field is set to “10” to select the 9-bit data format, writing to the PBE bit has no effect.

  • Page 344: Usart Fifo Control Register - Usrfcr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 USART FIFO Control Register – USRFCR This register specifies the USART FIFO control and configurations including threshold level and reset function together with the USART FIFO status. Offset: 0x008 Reset value: 0x0000_0000...

  • Page 345: Usart Interrupt Enable Register - Usrier

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions TX FIFO Reset Setting this bit will generate a reset pulse to reset TX FIFO which will empty the TX FIFO. i.e., the TX FIFO pointer will be reset to 0, after a reset signal. This bit returns to 0 automatically after the reset pulse is generated.

  • Page 346: Usart Status & Interrupt Flag Register - Usrsifr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions FEIE Framing Error Interrupt Enable 0: Disable interrupt 1: Enable interrupt An interrupt will be generated when the FEI bit is set in the URSIFR register. PEIE Parity Error Interrupt Enable...
  • Page 347 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions [10] CTSC CTS Status Change Flag This bit will be set whenever the CTS input pin status is changed and an Interrupt will be generated if the CTSC bit is set high and CTSIE = 1 in the USRIER register.

  • Page 348: Usart Timing Parameter Register - Usrtpr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions Overrun Error Indicator An overrun error will occur only after the RX FIFO is full and when the next character has been completely received in the RX shift register. The character in the shift register is overwritten, when an overrun event occurs.

  • Page 349: Usart Irda Control Register - Irdacr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 USART IrDA Control Register – IrDACR This register is used to control the USART IrDA mode. Offset: 0x018 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset IrDAPSC Type/Reset 0 RW 0 RW 0 RW...

  • Page 350: Usart Rs485 Control Register - Rs485Cr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions IrDAEN IrDA Enable control 0: Disable IrDA mode 1: Enable IrDA mode USART RS485 Control Register – RS485CR This register is used to control the USART RS485 mode. Offset:...

  • Page 351: Usart Synchronous Control Register - Syncr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 USART Synchronous Control Register – SYNCR This register is used to control the USART synchronous mode. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Reserved CLKEN Type/Reset 0 RW...

  • Page 352: Usart Divider Latch Register - Usrdlr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 USART Divider Latch Register – USRDLR The register is used to determine the USART clock divided ratio to generate the appropriate baud rate. Offset: 0x024 Reset value: 0x0000_0010 Reserved Type/Reset Reserved Type/Reset...

  • Page 353: Usart Test Register - Usrtstr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 USART Test Register – USRTSTR This register controls the USART debug mode. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset 0 RW Bits Field Descriptions [1:0] Loopback Test Mode Select...

  • Page 354: Universal Asynchronous Receiver Transmitter (Uart)

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Universal Asynchronous Receiver Transmitter (UART) Introduction The Universal Asynchronous Receiver Transceiver, UART, provides a flexible full duplex data exchange using asynchronous transfer. The UART is used to translate data between parallel and serial interfaces, and is also commonly used for RS232 standard communication.

  • Page 355: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Features ▄ Supports asynchronous serial communication modes ▄ Full Duplex Communication Capability ▄ Programming baud rate up to 3 Mbit/s ▄ Fully programmable serial communication functions including: ● Word length: 7, 8, or 9-bit character ●...

  • Page 356: Baud Rate Generation

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 Baud Rate Generation The baud rate for the UART receiver and transmitter are both set with the same values. The baud- rate divisor, BRD, has the following relationship with the UART clock which is known as CK_ UART.

  • Page 357: Table 50. Baud Rate Deviation Error Calculation - Ck_Uart = 20 Mhz

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Table 50. Baud Rate Deviation Error Calculation – CK_UART = 20 MHz Baud rate CK_UART = 20 MHz Kbps Actual Deviation Error rate 8333 0.00% 2083 0.02% 19.2 19.2 1042 -0.03% 57.6 57.6...

  • Page 358: Interrupts And Status

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Interrupts and Status The UART can generate interrupts when the following event occurs and corresponding interrupt enable bits are set: ▄ Receiver line status interrupts: The interrupts are generated when the UART receiver overrun error, parity error, framing error or break events occurs.

  • Page 359: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Register Descriptions UART Data Register – URDR The register is used to access the UART transmitted and received data. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Type/Reset 0 RW...
  • Page 360 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions [14] Break Control Bit When this bit is set to 1, the serial data output on the UART TX pin will be forced to the Spacing State (logic 0). This bit acts only on the UART TX output pin and has no effect on the transmitter logic.

  • Page 361: Uart Interrupt Enable Register - Urier

    Cortex ® -M0+ MCU HT32F52220/HT32F52230 UART Interrupt Enable Register – URIER This register is used to enable the related UART interrupt function. The UART module generates interrupts to the controller when the corresponding events occur and the corresponding interrupt enable bits are set.

  • Page 362: Uart Status & Interrupt Flag Register - Ursifr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions TXDEIE Transmit Data Register Empty Interrupt Enable 0: Disable interrupt 1: Enable interrupt An interrupt is generated when the transmit data register empty interrupt is enabled and the TXDE bit is set in the URSIFR register.
  • Page 363 32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 Bits Field Descriptions RXDR RX Data Ready 0: Receive data register is empty 1: Received data in the receive data register is ready to read This bit is set by hardware when the content of the receive shift register RDR has been transferred to the URDR register.

  • Page 364: Uart Divider Latch Register - Urdlr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 UART Divider Latch Register – URDLR The register is used to determine the UART clock divided ratio to generate the appropriate baud rate. Offset: 0x024 Reset value: 0x0000_0010 Reserved Type/Reset Reserved Type/Reset...

  • Page 365: Uart Test Register - Urtstr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F52220/HT32F52230 UART Test Register – URTSTR This register controls the UART debug mode. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset 0 RW Bits Field Descriptions [1:0] Loopback Test Mode Select...
  • Page 366 Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.

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