Rtc Status Register - Rtcsr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
RTC Status Register – RTCSR
This register stores the counter flags.
Offset: 0x00C
Reset value: 0x0000_0000 (Reset by V
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[2] OVFLAG
[1] CMFLAG
[0] CSECFLAG CK_SECOND Occurrence Flag
Rev. 1.00
Power Domain reset and RTCEN bit change from 1 to 0)
DD15
30 29 28
22 21 20
14 13 12
6 5 4
Reserved
Descriptions
Counter Overflow Flag
0: Counter overflow does not occur since the last RTCSR register read operation
1: Counter overflow has occurred since the last RTCSR register read operation
This bit is set by hardware when the counter value in the RTCCNT register changes
from 0xFF_FFFF to 0x00_0000 and cleared by read operation. This bit is suggested
to read in the RTC IRQ handler and should be taken care when software polling is
used.
Compare Match Condition Flag
0: Compare match condition does not occur since the last RTCSR register read
operation
1: Compare match condition has occurred since the last RTCSR register read
operation.
This bit is set by hardware on the CK_SECOND clock falling edge when the
RTCCNT register value is equal to the RTCCMP register content. It is cleared by
software reading this bit. This bit is suggested for access in the corresponding RTC
interrupt routine – do not use software polling during software free running.
0: CK_SECOND does not occur since the last RTCSR register read operation
1: CK_SECOND has occurred since the last RTCSR register read operation
This bit is set by hardware on the CK_SECOND clock falling edge. It is cleared by
software reading this bit. This bit is suggested for access in the corresponding RTC
interrupt routine – do not use software polling during software free running.
380 of 486
27 26 25
Reserved
19 18 17
Reserved
11 10
Reserved
3 2
OVFLAG CMFLAG CSECFLAG
RC 0 RC
24
16
9 8
1 0
0 RC 0
July 31, 2018