Holtek HT32F50231 User Manual page 24

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
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Inter-integrated Circuit – I
● Supports both master and slave modes with a frequency of up to 1 MHz
● Provides an arbitration function and clock synchronization
● Supports 7-bit and 10-bit addressing modes and general call addressing
● Supports slave multi-addressing mode with maskable address
▄
Serial Peripheral Interface – SPI
● Supports both master and slave modes
● Frequency of up to (f
● FIFO Depth: 8 levels
● Multi-master and multi-slave operation
▄
Universal Synchronous Asynchronous Receiver Transmitter – USART
● Supports both asynchronous and clocked synchronous serial communication modes
● Asynchronous operating baud-rate clock frequency up to (f
operating clock frequency up to (f
● Full duplex communication
● Fully programmable characteristics of serial communication including: word length, parity bit,
stop bit and bit order
● Error detection: Parity, overrun and frame error
● Auto hardware flow control mode – RTS, CTS
● IrDA SIR encoder and decoder
● RS485 mode with output enable control
● FIFO Depth: 8 × 9 bits for both receiver and transmitter
▄
Universal Asynchronous Receiver Transmitter – UART
● Asynchronous serial communication operating baud rate clock frequency of up to (f
● Capability of full duplex communication
● Fully programmable characteristics of serial communication including: word length, parity bit,
stop bit and bit order
● Error detection: Parity, overrun and frame error
▄
Hardware Divider – DIV
● Signed / unsigned 32-bit divider
● Operation in 8 clock cycles, load in 1 clock cycle
● Division by zero error flag
▄
Cyclic Redundancy Check – CRC
● Support CRC16 polynomial: 0x8005, X
● Support CCITT CRC16 polynomial: 0x1021, X
● Support IEEE-802.3 CRC32 polynomial: 0x04C11DB7, X
X + X
11 10
● Supports 1's complement, byte reverse & bit reverse operation on data and checksum
● Supports byte, half-word & word data size
● Programmable CRC initial seed value
● CRC computation executed in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for
32-bit data
▄
Debug Support
● Serial Wire Debug Port – SW-DP
● 4 comparators for hardware breakpoint or code / literal patch
● 2 comparators for hardware watchpoints
Rev. 1.00
C
2
/2) MHz for master mode and (f
PCLK
PCLK
+ X + X + X + X + X + X + 1
8 7 5 4 2
24 of 486
/3) MHz for slave mode
PCLK
/16) MHz and synchronous
PCLK
/8) MHz
16 + X 15 + X 2 + 1
16 + X 12 + X 5 + 1
+ X
32 26
/16) MHz
PCLK
+ X + X + X + X +
23 22 16 12
July 31, 2018