32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F50231/HT32F50241
The accompanying diagram shows the output states in the case of the output being enabled by
setting the CHxE bit to 1 and the complementary output being disabled by clearing the CHxNE to
0 when a break event occurs.
CHMOE
CHxOREF
CHxO
CHxNO
CHxO
CHxNO
0
Figure 123. Channel 0 ~ 2 Only One Output Enabled when Break Event Occurs
Rev. 1.00
CHxP = 0, CHxOIS = 0
CHxNP = 0, CHxOISN = 1
CHxP = 0, CHxOIS = 1
CHxNP = 0, CHxOIS = 0
319 of 486
Break event
Dead-time
Dead-time
Dead-time
July 31, 2018
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