Register Descriptions; Adc Conversion Control Register - Adccr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241

Register Descriptions

ADC Conversion Control Register – ADCCR
This register specifies the mode setting, sequence length and subgroup length of ADC conversion mode. Note
that once the content of ADCCR is changed, the conversion in progress will be aborted and the A/D converter
will return to an idle state. The application program has to wait for at least one CK_ADC clock before issuing the
next command.
Offset: 0x000
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
ADCEN ADCRST
Type/Reset RW 0 RW
Bits Field
[18:16] ADSUBL
[10:8] ADSEQL
[7] ADCEN
[6] ADCRST
Rev. 1.00
30 29 28
22 21 20
Reserved
14 13 12
Reserved
6 5 4
0
Descriptions
ADC Conversion Subgroup Length
The ADSUBL field specifies the conversion channel length of each subgroup for
regular discontinuous mode. Subgroup length = ADSUBL [2:0] + 1. If the sequence
length (ADSEQL [2:0] + 1) is not a multiple of the subgroup length (ADSUBL [2:0] + 1),
the last subgroup will be the rest of the group channels that have not been converted.
ADC Conversion Length
0x00: The channel specified by the ADSEQ0 field in the ADCLST0 register will be
converted
Others: Length of list queue = ADSEQL [2:0] + 1
The ADSEQL field specifies the whole conversion sequence length for the
conversion group.
ADC Enable
0: Disable
1: Enable
ADC Reset
0: No effect
1: Reset A/D converter except for the A/D Converter controller
170 of 486
27 26
Reserved
19 18
ADSUBL
RW 0 RW
11 10
ADSEQL
RW 0 RW
3 2
Reserved
RW
25 24
17 16
0 RW 0
9 8
0 RW 0
1 0
ADMODE
0 RW 0
July 31, 2018