Apb Peripheral Clock Selection Register 0 - Apbpcsr0 - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
APB Peripheral Clock Selection Register 0 – APBPCSR0
This register specifies APB peripheral clock prescaler selection.
Offset: 0x038
Reset value: 0x0000_0000
31
UR1PCLK
Type/Reset RW 0 RW
23
Reserved
Type/Reset
15
BFTM1PCLK
Type/Reset RW 0 RW
7
SPI1PCLK
Type/Reset RW 0 RW
Bits Field
[31:30] UR1PCLK
[29:28] UR0PCLK
[25:24] USRPCLK
[21:20] GPTMPCLK
[17:16] MCTMPCLK
Rev. 1.00
30 29 28
UR0PCLK
0 RW 0 RW
22 21 20
GPTMPCLK
RW 0 RW
14 13 12
BFTM0PCLK
0 RW 0 RW
6 5 4
SPI0PCLK
0 RW 0 RW
Descriptions
UART1 Peripheral Clock Selection
00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8
PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock
UART0 Peripheral Clock Selection
00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8
PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock
USART Peripheral Clock Selection
00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8
PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock
GPTM Peripheral Clock Selection
00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8
PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock
MCTM Peripheral Clock Selection
00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8
PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock
90 of 486
27 26
Reserved
0 RW
19 18
Reserved
0 RW
11 10
Reserved
0
3 2
I2C1PCLK
0 RW 0 RW 0 RW
25 24
USRPCLK
0 RW 0
17 16
MCTMPCLK
0 RW 0
9 8
1 0
I2C0PCLK
0 RW 0
July 31, 2018