32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F50231/HT32F50241
Asymmetric PWM Mode
Asymmetric PWM mode allows two center-aligned PWM signals to be generated with a
programmable phase shift. While the PWM frequency is determined by the value of the CRR
register, the duty cycle and the phase-shift are determined by the CHxCCR and CHxACR register.
When the counter is counting up, the PWM uses the value in CHxCCR as up-count compare value.
When the counter is into counting down stage, the PWM uses the value in CHxACR as down-
count compare value. The Figure 59 is shown as an example for asymmetric PWM mode in center-
aligned counting mode.
Note: Asymmetric PWM mode can only be operated in center-aligned counting mode.
CNTR
0
1
2
3
4
5
6
7
8
7
PWM center align mode
CRR = 8
CCR = 3, ACR = X
CHxOREF
PWM center align mode
CRR = 8
CCR = 5, ACR = X
CHxOREF
Asymetric PWM center align mode
CRR = 8
CCR = 3, ACR = 5
CHxOREF
Asymetric PWM center align mode
CRR = 8
CCR = 5, ACR = 3
CHxOREF
Figure 59. Asymmetric PWM Mode versus Center-aligned Counting Mode
Rev. 1.00
6
5
4
3
2
1
0
1
2
3
4
5
6
7
CRR = 8
208 of 486
8
7
6
5
4
3
2
1
0
1
2
3
4
5
CCR = 3
CCR = 5
CCR = 3
ACR = 5
CCR = 5
ACR = 3
6
7
8
7
6
5
4
3
2
1
Phase delay =2
July 31, 2018
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