Low Voltage / Brown Out Detect Control And Status Register - Lvdcsr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Bits Field
[2] LDOLCM
[0] PWCURST
Low Voltage / Brown Out Detect Control and Status Register – LVDCSR
This register specifies flags, enable bits and option bits for low voltage detector.
Offset: 0x110
Reset value: 0x0000_0000
31
Type/Reset
23
Reserved
Type/Reset RW
15
Type/Reset
7
Type/Reset
Bits Field
[21] LVDEWEN
[20] LVDIWEN
Rev. 1.00
Descriptions
LDO Low Current Mode
0: The LDO is operated in normal current mode
1: The LDO is operated in low current mode
Note: This bit is only available when CPU is in the run mode. The LDO output
current capability will be limited at 10 mA below and lower static current when
the LDOLCM bit is set. It is suitable for CPU, which is operated at lower speed
system clock, to get a lower current consumption. This bit will be cleared to 0
when the LDO is powered down or V
Power Control Unit Software Reset
0: No action
1: Power Control Unit Software Reset is activated
When this bit is set, it will reset all the related RTC and PWRCU registers.
30 29 28
22 21 20
LVDS [2] LVDEWEN LVDIWEN
0 RW 0 RW
14 13 12
6 5
Reserved
Descriptions
LVD Event Wakeup Enable
0: LVD event wakeup is disabled
1: LVD event wakeup is enabled
Setting this bit to 1 will enable the LVD event wakeup function to wake up the system
when an LVD condition occurs which result in the LVDF bit being asserted. If the
system requires to be woken up from the Deep-Sleep mode by an LVD condition,
this bit must be set to 1.
LVD Interrupt Wakeup Enable
0: LVD interrupt wakeup is disabled
1: LVD interrupt wakeup is enabled
Setting this bit to 1 will enable the LVD interrupt function. When an LVD condition
occurs and the LVDIWEN bit is set to 1, an LVD interrupt will be generated and sent
to the CPU NVIC unit.
68 of 486
power domain is reset.
DD
27 26
Reserved
19 18
LVDF
0 RO 0 RW
11 10
Reserved
4 3 2
BODF Reserved
RO 0
25 24
17 16
LVDS [1:0] LVDEN
0 RW 0 RW 0
9 8
1 0
BODRIS BODEN
RW 0 RW 0
July 31, 2018