Dividend Data Register - Ddr; Divisor Data Register - Dsr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Dividend Data Register – DDR
The register is used to specify the dividend data.
Offset: 0x004
Reset value: 0x0000_0000
31
Type/Reset RW 0 RW
23
Type/Reset RW 0 RW
15
Type/Reset RW 0 RW
7
Type/Reset RW 0 RW
Bits Field
[31:0] DDR
Divisor Data Register – DSR
The register is used to specify the divisor data.
Offset: 0x008
Reset value: 0x0000_0000
31
Type/Reset RW 0 RW
23
Type/Reset RW 0 RW
15
Type/Reset RW 0 RW
7
Type/Reset RW 0 RW
Bits Field
[31:0] DSR
Rev. 1.00
30 29 28
0 RW 0 RW
22 21 20
0 RW 0 RW
14 13 12
0 RW 0 RW
6 5 4
0 RW 0 RW
Descriptions
Dividend Data Register
This bit field is used to specify the dividend of the divider calculation.
30 29 28
0 RW 0 RW
22 21 20
0 RW 0 RW
14 13 12
0 RW 0 RW
6 5 4
0 RW 0 RW
Descriptions
Divisor Data Register
This bit field is used to specify the divisor of the divider calculation.
478 of 486
27 26
DDR
0 RW 0 RW 0 RW
19 18
DDR
0 RW 0 RW 0 RW
11 10
DDR
0 RW 0 RW 0 RW
3 2
DDR
0 RW 0 RW 0 RW
27 26
DSR
0 RW 0 RW 0 RW
19 18
DSR
0 RW 0 RW 0 RW
11 10
DSR
0 RW 0 RW 0 RW
3 2
DSR
0 RW 0 RW 0 RW
25 24
0 RW 0
17 16
0 RW 0
9 8
0 RW 0
1 0
0 RW 0
25 24
0 RW 0
17 16
0 RW 0
9 8
0 RW 0
1 0
0 RW 0
July 31, 2018