I 2 C Interrupt Enable Register - I2Cier - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Bits Field
[2] GCEN
[1] STOP
[0] AA
I 2 C Interrupt Enable Register – I2CIER
This register specifies the corresponding I
Offset: 0x004
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[18] RXBFIE
[17] TXDEIE
Rev. 1.00
Descriptions
General Call Enable
0: General call is disabled
1: General call is enabled
When the device receives the calling address with a value of 0x00 and if both
the GCEN and the AA bits are set to 1, then the I
slave and the GCS bit in the I2CSR register is set to 1. When the I2CEN bit is
cleared to 0, the GCEN bit is automatically cleared to 0 by hardware.
STOP Condition Control
0: No action
1: Send a STOP condition in master mode
This bit is set to 1 by software to generate a STOP condition and automatically
cleared to 0 by hardware. The STOP bit is only available for the master device.
Acknowledge Bit
0: Send a Not Acknowledge (NACK) signal after a byte is received
1: Send an Acknowledge (ACK) signal after a byte is received
When the I2CEN bit is cleared to 0, the AA bit is automatically cleared to 0 by
hardware.
2 C interrupt enable bits.
30 29 28
22 21 20
Reserved
14 13 12
Reserved
6 5 4
Reserved
Descriptions
RX Buffer Full Interrupt Enable Bit
0: Interrupt is disabled
1: Interrupt is enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware.
Data Register Empty Interrupt Enable Bit in Transmitter Mode
0: Interrupt is disabled
1: Interrupt is enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware.
407 of 486
2 C interface is addressed as a
27 26
Reserved
19 18
RXBFIE TXDEIE
RW 0 RW
11 10
TOUTIE BUSERRIE RXNACKIE ARBLOSIE
RW 0 RW 0 RW
3 2
GCSIE ADRSIE STOIE
RW 0 RW 0 RW
25 24
17 16
RXDNEIE
0 RW 0
9 8
0 RW 0
1 0
STAIE
0 RW 0
July 31, 2018