Holtek HT32F50231 User Manual page 18

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Figure 81. PWM Mode Channel Output Reference Signal and Counter in Centre-aligned Mode ........ 259
Figure 82. Update Event Setting Diagram ............................................................................................ 260
Figure 83. Single Pulse Mode ............................................................................................................... 261
Figure 84. Immediate Active Mode Minimum Delay ............................................................................. 262
Figure 85. Asymmetric PWM Mode versus Center-aligned Counting Mode ......................................... 263
Figure 86. Pausing PWM1 using the PWM0 CH0OREF Signal ........................................................... 264
Figure 87. Triggering PWM1 with PWM0 Update Event ....................................................................... 264
Figure 88. Trigger PWM0 and PWM1 with the PWM0 Timer Enable Signal ........................................ 265
Figure 89. BFTM Block Diagram .......................................................................................................... 292
Figure 90. BFTM - Repetitive Mode ..................................................................................................... 293
Figure 91. BFTM - One Shot Mode ...................................................................................................... 294
Figure 92. BFTM - One Shot Mode Counter Updating ....................................................................... 294
Figure 93. MCTM Block Diagram ......................................................................................................... 298
Figure 94. Up-counting Example .......................................................................................................... 300
Figure 95. Down-counting Example ...................................................................................................... 300
Figure 96. Center-aligned Counting Example ....................................................................................... 301
Figure 97. Update Event 1 Dependent Repetition Mechanism Example .............................................. 302
Figure 98. MCTM Clock Selection Source ............................................................................................ 303
Figure 99. Trigger Controller Block ....................................................................................................... 304
Figure 100. Slave Controller Diagram .................................................................................................. 305
Figure 101. MCTM in Restart Mode ..................................................................................................... 305
Figure 102. MCTM in Pause Mode ....................................................................................................... 306
Figure 103. MCTM in Trigger Mode ...................................................................................................... 306
Figure 104. Master MCTMn and Slave GPTM Connection .................................................................. 307
Figure 105. MTO Selection ................................................................................................................... 307
Figure 106. Capture/Compare Block Diagram ...................................................................................... 308
Figure 107. Input Capture Mode ........................................................................................................... 308
Figure 108. PWM Pulse Width Measurement Example ........................................................................ 309
Figure 109. Channel 0 and Channel 1 Input Stages ............................................................................. 310
Figure 110. Channel 2 and Channel 3 Input Stages ............................................................................. 310
Figure 111. TI0 Digital Filter Diagram with N = 2 ...................................................................................311
Figure 112. Output Stage Block Diagram ..............................................................................................311
Figure 113. Toggle Mode Channel Output Reference Signal - CHxPRE = 0 ....................................... 312
Figure 114. Toggle Mode Channel Output Reference Signal - CHxPRE = 1 ....................................... 313
Figure 115. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode .......... 313
Figure 116. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ...... 314
Figure 117. PWM Mode 1 Channel Output Reference Signal and Counter in Centre-aligned Counting
Mode ...................................................................................................................................................... 314
Figure 118. Dead-time Insertion Performed for Complementary Outputs............................................. 315
Figure 119. MCTM Break Signal Bolck Diagram .................................................................................. 316
Figure 120. MT_BRK Pin Digital Filter Diagram with N = 2 .................................................................. 316
Rev. 1.00 18 of 486 July 31, 2018