32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F50231/HT32F50241
Security Protection
FMC provides a Security protection function to prevent illegal code / data access of the Flash
memory. This function is useful for protecting the software / firmware from illegal users. The
function is activated by setting the Option Byte OB_CP [0] bit. Once the function has been
enabled, all the main Flash data access through ICP / Debug mode, programming and page erase
will not be allowed except the user's application. But the mass erase operation will still be accepted
by FMC in order to disable this function. The following table shows the access permission of Flash
memory when the security protection is enabled.
Table 8. Access Permission When Security Protection is Enabled
Operation
Read
Program
Page Erase
Mass Erase
Notes: 1. User application means the software that is executed or booted from main Flash memory
with the JTAG / SW debugger being disconnected. However, the Option Byte area and
page 0 are still under protection where the Program / Page Erase operations are not
accepted.
2. The Mass erase operation can erase the Option Byte area and disable the security
protection.
The following steps show the register access sequence for Security protection procedure.
▄
Check the OPCR register to confirm that no Flash memory operation is in progress (OPM [3:0]
equals to 0xE or 0x6). Otherwise, wait until the previous operation has been finished.
▄
Write OB_CP address to the TADR register (TADR = 0x1FF0_0010).
▄
Write the WRDR register to set the OB_CP [0] as 0.
▄
Write word programming command to the OCMR register (Set CMD [3:0] = 0x4).
▄
Commit word programming command to FMC by setting the OPCR register (Set OPM [3:0] = 0xA).
▄
Wait until all operations have been finished by checking the value of the OPCR register (OPM [3:0]
equals to 0xE).
▄
Read and verify the Option Byte if required.
▄
The OB_CK field in the Option Byte must be updated according to the Option Byte checksum rule.
▄
Apply a system reset to active the new OB_CP setting.
Rev. 1.00
Mode
User Application
O
O
(Note 1)
O
(Note 1)
O
43 of 486
(Note 1)
ICP / Debug Mode
X (read as 0)
X
X
O
July 31, 2018
Need help?
Do you have a question about the HT32F50231 and is the answer not in the manual?
Questions and answers