Register Descriptions; Global Clock Configuration Register - Gcfgr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241

Register Descriptions

Global Clock Configuration Register – GCFGR
This register specifies the low power mode status and clock source for CKOUT.
Offset: 0x000
Reset value: 0x0000_0002
31
Type/Reset RO 0 RO
23
Type/Reset
15
Type/Reset RW 0 RW
7
Type/Reset
Bits Field
[31:29] LPMOD
[15:11] CKREFPRE CK_REF Clock Prescaler Selection
[2:0] CKOUTSRC CKOUT Clock Source Selection
Rev. 1.00
30 29
LPMOD
0 RO 0
22 21
14 13
CKREFPRE
0 RW 0 RW
6 5
Reserved
Descriptions
Lower Power Mode Status
000: When Chip is in running mode
001: When Chip wants to enter Sleep mode
010: When Chip wants to enter Deep-Sleep1 mode
011: When Chip wants to enter Deep-Sleep2 mode
Others: Reserved
Set and reset by hardware.
CK_REF = CK_SYS / (CKREFPRE + 1) / 2
00000: CK_REF = CK_SYS / 2
00001: CK_REF = CK_SYS / 4
...
11111: CK_REF = CK_SYS / 64
Set and reset by software to control CK_REF clock prescaler setting.
000: (CK_SYS / (CKREFPRE + 1) / 2 ) is selected
001: (CK_AHB / 16) is selected
010: (CK_SYS / 16) is selected
011: (CK_HSE / 16) is selected
100: (CK_HSI / 16) is selected
101: CK_LSE is selected
110: CK_LSI is selected
111: Reserved
Set and reset by software.
78 of 486
28 27 26
Reserved
20 19 18
Reserved
12 11 10
0 RW 0
4 3 2
RW
25 24
17 16
9 8
Reserved
1 0
CKOUTSRC
0 RW 1 RW 0
July 31, 2018